arm: kirkwood: Pogoplug-V4 : Add board implementation files
Add board header, defconfig, and implementation files for Pogoplug V4.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
diff --git a/board/cloudengines/pogo_v4/MAINTAINERS b/board/cloudengines/pogo_v4/MAINTAINERS
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+++ b/board/cloudengines/pogo_v4/MAINTAINERS
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+POGO_V4 BOARD
+M: Tony Dinh <mibodhi@gmail.com>
+S: Maintained
+F: board/cloudengines/pogo_v4/
+F: include/configs/pogo_v4.h
+F: configs/pogo_v4_defconfig
diff --git a/board/cloudengines/pogo_v4/Makefile b/board/cloudengines/pogo_v4/Makefile
new file mode 100644
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+++ b/board/cloudengines/pogo_v4/Makefile
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+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014-2021 Tony Dinh <mibodhi@gmail.com>
+#
+# Based on
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+
+obj-y := pogo_v4.o
diff --git a/board/cloudengines/pogo_v4/kwbimage.cfg b/board/cloudengines/pogo_v4/kwbimage.cfg
new file mode 100644
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+++ b/board/cloudengines/pogo_v4/kwbimage.cfg
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+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2012
+# David Purdy <david.c.purdy@gmail.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
+
+# Boot Media configurations (DONE)
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME)
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?)
+DATA 0xffd01400 0x43000618 # DDR Configuration register
+# bit13-0: 0x200 (200 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xffd01404 0x34143000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000819 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xffd01410 0x00000001 # DDR Address Control (changed to Dockstar vals)
+# bit1-0: 00, Cs0width=x16
+# bit3-2: 10, Cs0size=512Mb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xffd01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xffd0141c 0x00000632 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5 (<===== change to CL=3 ?)
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xffd01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xffd01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 0 , no sample stage
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) (DONE)
+# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000 # DDR ODT Control (High) (DONE)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xffd0149c 0x0000e803 # CPU ODT Control (DONE)
+DATA 0xffd01480 0x00000001 # DDR Initialization Control (DONE)
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/cloudengines/pogo_v4/pogo_v4.c b/board/cloudengines/pogo_v4/pogo_v4.c
new file mode 100644
index 0000000..61ce0d5
--- /dev/null
+++ b/board/cloudengines/pogo_v4/pogo_v4.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2022 Tony Dinh <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2012 David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include <bootstage.h>
+#include <command.h>
+#include <init.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO configuration */
+#define POGO_V4_OE_LOW (~(0))
+#define POGO_V4_OE_HIGH (~(0))
+#define POGO_V4_OE_VAL_LOW BIT(29)
+#define POGO_V4_OE_VAL_HIGH 0
+
+/* button */
+#define BTN_EJECT 29
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(POGO_V4_OE_VAL_LOW,
+ POGO_V4_OE_VAL_HIGH,
+ POGO_V4_OE_LOW, POGO_V4_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_SATA1_ACTn,
+ MPP21_SATA0_ACTn,
+ MPP22_GPIO, /* Green LED */
+ MPP23_GPIO,
+ MPP24_GPIO, /* Red LED */
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO, /* Eject button */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO, /* FR6192 has only 36 GPIOs */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+ return cpu_eth_init(bis);
+}
+
+int board_late_init(void)
+{
+ /* Do late init to ensure successful enumeration of XHCI devices */
+ pci_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+#define GREEN_LED BIT(22)
+#define RED_LED BIT(24)
+#define BOTH_LEDS (GREEN_LED | RED_LED)
+#define NEITHER_LED 0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+ struct kwgpio_registers *r;
+ u32 oe;
+ u32 bl;
+
+ r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ oe = readl(&r->oe) | BOTH_LEDS;
+ writel(oe & ~leds, &r->oe); /* active low */
+ bl = readl(&r->blink_en) & ~BOTH_LEDS;
+ writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
+ set_leds(BOTH_LEDS, NEITHER_LED);
+ break;
+ case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
+ set_leds(GREEN_LED, GREEN_LED);
+ break;
+ default:
+ if (val < 0) /* error */
+ set_leds(RED_LED, RED_LED);
+ break;
+ }
+}
+#endif