bcb38434d99fd91f8190fb187202b2df8eae39fc - filogic/uboot

commit	bcb38434d99fd91f8190fb187202b2df8eae39fc	[log] [tgz]
author	Bin Meng <bmeng.cn@gmail.com>	Wed Sep 26 06:55:17 2018 -0700
committer	Andes <uboot@andestech.com>	Wed Oct 03 17:48:14 2018 +0800
tree	a344c53febb288b4e740dce7cc70c3efa91580fc
parent	8294bb518891e7e2f72807a0b295b0bb4e7e6a77 [diff]

riscv: Make start.S available for all targets

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

arch/riscv/Makefile[diff]
arch/riscv/cpu/Makefile[diff]
arch/riscv/cpu/ax25/Makefile[diff]
arch/riscv/cpu/start.S[Renamed from arch/riscv/cpu/ax25/start.S - diff]
arch/riscv/cpu/u-boot.lds[diff]

5 files changed

tree: a344c53febb288b4e740dce7cc70c3efa91580fc