Enable L2 cache for MPC8568MDS board
The L2 cache size is 512KB for 8568, print out the correct informaiton.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 7b99610..79ad20c 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -247,7 +247,7 @@
switch (cache_ctl & 0x30000000) {
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
- ver == SVR_8544) {
+ ver == SVR_8544 || ver == SVR_8568_E) {
printf ("L2 cache 512KB:");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index d5a14fc..ba744e9 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -63,9 +63,9 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.