arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to Kconfig
Move these options to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 88983f4..17f1975 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,6 +1,8 @@
config ARCH_LS1021A
bool
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -23,6 +25,15 @@
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 7aae397..28589ae 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -14,16 +14,23 @@
bool
select FSL_LSCH2
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_SRDS_2
config ARCH_LS2080A
bool
select FSL_LSCH3
+ select SYS_FSL_HAS_DP_DDR
+ select SYS_FSL_SRDS_2
config FSL_LSCH2
bool
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
config FSL_LSCH3
bool
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
@@ -65,4 +72,13 @@
config SYS_FSL_HAS_DP_DDR
bool
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
endmenu