powerpc/p4080: Add workaround for erratum CPU22
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 01c462c..d73f3d7 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -44,7 +44,9 @@
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
puts("Work-around for Erratum SERDES8 enabled\n");
#endif
-
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ puts("Work-around for Erratum CPU22 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index a90ebb1..2c3be6d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -32,6 +32,7 @@
#include <ioports.h>
#include <sata.h>
#include <asm/io.h>
+#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
@@ -245,6 +246,12 @@
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ flush_dcache();
+ mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+ sync();
+#endif
+
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 0b5b9da..53cefaf 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -136,6 +136,12 @@
mtspr L1CSR2,r8
#endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ mfspr r8,L1CSR2
+ oris r8,r8,(L1CSR2_DCWS)@h
+ mtspr L1CSR2,r8
+#endif
+
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */
msync