global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index d772249..f1ccb5f 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -7,8 +7,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
@@ -59,18 +59,18 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -94,52 +94,52 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif
/* CPLD */
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
FTIM0_GPCM_TEADC(0xf) | \
FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3
/*
* Serial Port
@@ -298,7 +298,7 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID