global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index dbf038c..e152714 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -25,10 +25,10 @@
#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
/* Application IFC CS4 MRAM */
-#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
+#define CFG_SYS_MRAM_BASE SYS_LAWAPP_BASE
#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
#define SYS_MRAM_CSPR_EXT (0x0f)
-#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \
CSPR_PORT_SIZE_8 | /* 8 bit */ \
CSPR_MSEL_GPCM | /* msel = gpcm */ \
CSPR_V /* bank is valid */)
@@ -44,14 +44,14 @@
FTIM2_GPCM_TCH(0x2) | \
FTIM2_GPCM_TWP(0x8))
#define SYS_MRAM_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
-#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
-#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
-#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
-#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
-#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
-#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
-#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
+#define CFG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
+#define CFG_SYS_CSPR4 SYS_MRAM_CSPR
+#define CFG_SYS_AMASK4 SYS_MRAM_AMASK
+#define CFG_SYS_CSOR4 SYS_MRAM_CSOR
+#define CFG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
+#define CFG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
+#define CFG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
+#define CFG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
/* Application IFC CS6: BFTIC */
#define SYS_BFTIC_BASE 0xd0000000
@@ -73,20 +73,20 @@
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define SYS_BFTIC_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
-#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
-#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
-#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
-#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
-#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
-#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
-#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
+#define CFG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
+#define CFG_SYS_CSPR6 SYS_BFTIC_CSPR
+#define CFG_SYS_AMASK6 SYS_BFTIC_AMASK
+#define CFG_SYS_CSOR6 SYS_BFTIC_CSOR
+#define CFG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
+#define CFG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
+#define CFG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
+#define CFG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
/* Application IFC CS7 PAXE */
-#define CONFIG_SYS_PAXE_BASE 0xd8000000
-#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define CFG_SYS_PAXE_BASE 0xd8000000
+#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CFG_SYS_PAXE_BASE)
#define SYS_PAXE_CSPR_EXT (0x0f)
-#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \
CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
CSPR_MSEL_GPCM | /* MSEL = GPCM */\
CSPR_V) /* valid */
@@ -102,14 +102,14 @@
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define SYS_PAXE_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
-#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
-#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
-#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
-#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
-#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
-#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
-#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
+#define CFG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
+#define CFG_SYS_CSPR7 SYS_PAXE_CSPR
+#define CFG_SYS_AMASK7 SYS_PAXE_AMASK
+#define CFG_SYS_CSOR7 SYS_PAXE_CSOR
+#define CFG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
+#define CFG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
+#define CFG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
+#define CFG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
/* PRST */
#define KM_BFTIC4_RST 0
@@ -145,25 +145,25 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
/* POST memory regions test */
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
@@ -189,12 +189,12 @@
* IFC Definitions
*/
/* NOR flash on IFC CS0 */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
- CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
+ CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR_CSPR_EXT (0x0f)
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_NOR | /* MSEL = NOR */\
@@ -217,18 +217,18 @@
FTIM2_NOR_TWPH(0x6))
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* More NOR Flash params */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC CS1*/
#define CFG_SYS_NAND_BASE 0xfa000000
@@ -266,23 +266,23 @@
FTIM2_NAND_TWHRE(0x3c))
#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
/* More NAND Flash Params */
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO on IFC CS2 */
-#define CONFIG_SYS_QRIO_BASE 0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define CFG_SYS_QRIO_BASE 0xfb000000
+#define CFG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CFG_SYS_QRIO_BASE)
#define SYS_QRIO_CSPR_EXT (0x0f)
-#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_GPCM | /* MSEL = GPCM */\
@@ -300,28 +300,28 @@
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x7))
#define SYS_QRIO_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
-#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
-#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
-#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
-#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
+#define CFG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
+#define CFG_SYS_CSPR2 SYS_QRIO_CSPR
+#define CFG_SYS_AMASK2 SYS_QRIO_AMASK
+#define CFG_SYS_CSOR2 SYS_QRIO_CSOR
+#define CFG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
+#define CFG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
+#define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
+#define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port - controlled on board with jumper J8
@@ -331,7 +331,7 @@
*/
#if !defined(CONFIG_DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500)
#endif
#ifndef __ASSEMBLY__
@@ -351,30 +351,30 @@
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
/* Qman / Bman */
/* RGMII (FM1@DTESC5) is local managemant interface */
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
+#define CFG_SYS_RGMII2_PHY_ADDR 0x11
/*
* Hardware Watchdog
@@ -387,7 +387,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
@@ -412,12 +412,12 @@
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
- "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "erase " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
- __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
"set_fdthigh=true\0" \