commit 6a5dccc02202c5bf334825ef3104f9d85c9cb678
author Tom Rini <trini@konsulko.com> Wed Nov 16 13:10:41 2022 -0500
committer Tom Rini <trini@konsulko.com> Mon Dec 05 16:06:08 2022 -0500
tree e1b9902c5257875fc5fe8243e1e759594f90beed
parent 40eb556ddee958f8452c9d987acb1140bc167ed8

global: Move remaining CONFIG_SYS_* to CFG_SYS_*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

drivers/timer/arm_global_timer.c

diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c
index 065f10b..2e50d9f 100644
--- a/drivers/timer/arm_global_timer.c
+++ b/drivers/timer/arm_global_timer.c
@@ -59,7 +59,7 @@
 			return ret;
 		uc_priv->clock_rate = ret;
 	} else {
-		uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+		uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
 	}
 
 	/* init timer */

drivers/timer/imx-gpt-timer.c

diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
index 72be297..9c3b64a 100644
--- a/drivers/timer/imx-gpt-timer.c
+++ b/drivers/timer/imx-gpt-timer.c
@@ -28,9 +28,9 @@
 #define GPT_CLKSRC_IPG_CLK		(1 << 6)
 #define GPT_CLKSRC_IPG_CLK_24M		(5 << 6)
 
-/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
-#ifndef CONFIG_SYS_HZ_CLOCK
-#define CONFIG_SYS_HZ_CLOCK		3000000
+/* If CFG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CFG_SYS_HZ_CLOCK
+#define CFG_SYS_HZ_CLOCK		3000000
 #endif
 
 struct imx_gpt_timer_regs {
@@ -60,7 +60,7 @@
 
 static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
 {
-	u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+	u32 prescaler = (rate / CFG_SYS_HZ_CLOCK) - 1;
 
 	/* Reset the timer */
 	setbits_le32(&regs->cr, GPT_CR_SWR);
@@ -138,7 +138,7 @@
 		return ret;
 	}
 
-	uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+	uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
 
 	return 0;
 }

drivers/timer/orion-timer.c

diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c
index d0eab3c..d588f0c 100644
--- a/drivers/timer/orion-timer.c
+++ b/drivers/timer/orion-timer.c
@@ -72,7 +72,7 @@
 	if (IS_ENABLED(CONFIG_ARCH_MVEBU))
 		return MVEBU_TIMER_FIXED_RATE_25MHZ;
 	else
-		return CONFIG_SYS_TCLK;
+		return CFG_SYS_TCLK;
 }
 
 /**
@@ -117,7 +117,7 @@
 	if (type == INPUT_CLOCK_25MHZ)
 		uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ;
 	else
-		uc_priv->clock_rate = CONFIG_SYS_TCLK;
+		uc_priv->clock_rate = CFG_SYS_TCLK;
 	orion_timer_init(priv->base, type);
 
 	return 0;

drivers/timer/stm32_timer.c

diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
index f07251e..1213a14 100644
--- a/drivers/timer/stm32_timer.c
+++ b/drivers/timer/stm32_timer.c
@@ -97,11 +97,11 @@
 	rate = clk_get_rate(&clk);
 
 	/* we set timer prescaler to obtain a 1MHz timer counter frequency */
-	psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+	psc = (rate / CFG_SYS_HZ_CLOCK) - 1;
 	writel(psc, &regs->psc);
 
 	/* Set timer frequency to 1MHz */
-	uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+	uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
 
 	/* Configure timer for auto-reload */
 	setbits_le32(&regs->cr1, CR1_ARPE);