diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index d31ad02..9ca350e 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -43,7 +43,7 @@
 int fsl_check_boot_mode_secure(void)
 {
 	uint32_t val;
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
 
 	val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 3424d49..285ed9a 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -85,7 +85,7 @@
 {
 	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
-	u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
+	u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE);
 	u32 flash_addr, addr;
 	int found = 0;
 	int i = 0;
@@ -160,7 +160,7 @@
 	 */
 #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
 	sg_tbl = (struct fsl_secboot_sg_table *)
-		 (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+		 (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) +
 		  flash_base_addr);
 #else
 	sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
@@ -170,7 +170,7 @@
 	/* IE Key Table is the first entry in the SG Table */
 #if defined(CONFIG_MPC85xx)
 	*ie_addr = (uintptr_t)((sg_tbl->src_addr &
-			~(CONFIG_SYS_PBI_FLASH_BASE)) +
+			~(CFG_SYS_PBI_FLASH_BASE)) +
 			flash_base_addr);
 #else
 	*ie_addr = (uintptr_t)sg_tbl->src_addr;
@@ -203,7 +203,7 @@
 /* This function returns ospr's key_revoc values.*/
 static u32 get_key_revoc(void)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 	return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
 		OSPR_KEY_REVOC_SHIFT;
 }
@@ -342,7 +342,7 @@
  */
 static void fsl_secboot_header_verification_failure(void)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 
 	/* 29th bit of OSPR is ITS */
 	u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
@@ -367,7 +367,7 @@
  */
 static void fsl_secboot_image_verification_failure(void)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 
 	u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
 
@@ -871,7 +871,7 @@
 int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
 			uintptr_t *img_addr_ptr)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 	ulong hash[SHA256_BYTES/sizeof(ulong)];
 	char hash_str[NUM_HEX_CHARS + 1];
 	struct fsl_secboot_img_priv *img;
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 8951fae..1a1e934 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -11,12 +11,12 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
 #endif
 #ifdef PIXIS_BASE_PHYS
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
@@ -24,9 +24,9 @@
 #ifdef CPLD_BASE_PHYS
 	SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CFG_SYS_NAND_BASE_PHYS
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 7302b76..1a2d9cb 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -11,20 +11,20 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 #ifdef CPLD_BASE
@@ -41,25 +41,25 @@
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 
 #if !defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 #else
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
-	 * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+	 * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR,
 	 * and virtual address is CONFIG_SYS_MONITOR_BASE
 	 */
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
-			CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
+			CFG_SYS_INIT_L3_ADDR & 0xfff00000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 #endif
@@ -80,13 +80,13 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -112,26 +112,26 @@
 		      0, 6, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x00100000,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_1M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x00100000,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_1M, 1),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_4M, 1),
 #endif
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2bb838c..da2c1de 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -29,15 +29,15 @@
 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
 #endif
 
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+	return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg);
 #else
 	struct udevice *dev;
 
-	if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+	if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev))
 		return 0xff;
 
 	return dm_i2c_reg_read(dev, reg);
@@ -48,11 +48,11 @@
 {
 	u8 val = value;
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+	i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val);
 #else
 	struct udevice *dev;
 
-	if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+	if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev))
 		dm_i2c_reg_write(dev, reg, val);
 #endif
 
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index af76327..784046a 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -100,12 +100,12 @@
 char *qixis_read_time(char *result);
 char *qixis_read_tag(char *buf);
 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg);
 void qixis_write_i2c(unsigned int reg, u8 value);
 #endif
 
-#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR)
 #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 #define QIXIS_WRITE(reg, value) \
 	qixis_write_i2c(offsetof(struct qixis, reg), value)
@@ -114,7 +114,7 @@
 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
 #endif
 
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
 #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 #define QIXIS_WRITE_I2C(reg, value) \
 			qixis_write_i2c(offsetof(struct qixis, reg), value)
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index f17a6c1..194b5d2 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -117,7 +117,7 @@
 	struct udevice *dev;
 	int ret;
 
-	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
+	ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR,
 				      1, &dev);
 	if (ret) {
 		printf("%s: Cannot find udev for a bus %d\n", __func__,
@@ -128,7 +128,7 @@
 #else
 	i2c_set_bus_num(bus_num);
 
-	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+	i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
 #endif
 
 	return 0;
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d0674d0..d5cb731 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -196,7 +196,7 @@
 	porsr1 = in_be32(&gur->porsr1);
 	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
-	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+	out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 pinctl);
 #endif
 
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 8b74d45..4f58343 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -98,7 +98,7 @@
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 static void cpld_show(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
@@ -248,7 +248,7 @@
 static void convert_serdes_mux(int type, int need_reset)
 {
 	char current_serdes;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	current_serdes = cpld_data->serdes_mux;
 
@@ -322,7 +322,7 @@
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 int config_board_mux(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	int conflict_flag;
 
 	conflict_flag = 0;
@@ -610,7 +610,7 @@
 	&& !defined(CONFIG_SPL_BUILD)
 static void convert_flash_bank(char bank)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	printf("Now switch to boot from flash bank %d.\n", bank);
 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
@@ -644,7 +644,7 @@
 static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 			  char *const argv[])
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	if (argc > 2)
 		return CMD_RET_USAGE;
@@ -671,7 +671,7 @@
 static void print_serdes_mux(void)
 {
 	char current_serdes;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	current_serdes = cpld_data->serdes_mux;
 
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 5fe40c4..841d8b5 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -57,8 +57,8 @@
 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -71,8 +71,8 @@
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -97,15 +97,15 @@
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };
@@ -126,8 +126,8 @@
 	},
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -139,8 +139,8 @@
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -152,15 +152,15 @@
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 2320356..9db3aa5 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -12,14 +12,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index a8a7263..741a4d6 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -60,15 +60,15 @@
 	},
 	{
 		"cpld",
-		CONFIG_SYS_CPLD_CSPR,
-		CONFIG_SYS_CPLD_CSPR_EXT,
-		CONFIG_SYS_CPLD_AMASK,
-		CONFIG_SYS_CPLD_CSOR,
+		CFG_SYS_CPLD_CSPR,
+		CFG_SYS_CPLD_CSPR_EXT,
+		CFG_SYS_CPLD_AMASK,
+		CFG_SYS_CPLD_CSOR,
 		{
-			CONFIG_SYS_CPLD_FTIM0,
-			CONFIG_SYS_CPLD_FTIM1,
-			CONFIG_SYS_CPLD_FTIM2,
-			CONFIG_SYS_CPLD_FTIM3
+			CFG_SYS_CPLD_FTIM0,
+			CFG_SYS_CPLD_FTIM1,
+			CFG_SYS_CPLD_FTIM2,
+			CFG_SYS_CPLD_FTIM3
 		},
 	}
 };
@@ -102,15 +102,15 @@
 	},
 	{
 		"cpld",
-		CONFIG_SYS_CPLD_CSPR,
-		CONFIG_SYS_CPLD_CSPR_EXT,
-		CONFIG_SYS_CPLD_AMASK,
-		CONFIG_SYS_CPLD_CSOR,
+		CFG_SYS_CPLD_CSPR,
+		CFG_SYS_CPLD_CSPR_EXT,
+		CFG_SYS_CPLD_AMASK,
+		CFG_SYS_CPLD_CSOR,
 		{
-			CONFIG_SYS_CPLD_FTIM0,
-			CONFIG_SYS_CPLD_FTIM1,
-			CONFIG_SYS_CPLD_FTIM2,
-			CONFIG_SYS_CPLD_FTIM3
+			CFG_SYS_CPLD_FTIM0,
+			CFG_SYS_CPLD_FTIM1,
+			CFG_SYS_CPLD_FTIM2,
+			CFG_SYS_CPLD_FTIM3
 		},
 	}
 };
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 97d71db..3d08816 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -41,8 +41,8 @@
 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -55,8 +55,8 @@
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -81,15 +81,15 @@
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };
@@ -110,8 +110,8 @@
 	},
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -123,8 +123,8 @@
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -136,15 +136,15 @@
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };
diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c
index 548601a..ee19d4f 100644
--- a/board/freescale/ls1046ardb/cpld.c
+++ b/board/freescale/ls1046ardb/cpld.c
@@ -12,14 +12,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index ff3abc8..0d3f22c 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -41,8 +41,8 @@
 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR_EARLY,
-		CONFIG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR0_CSPR_EARLY,
+		CFG_SYS_NOR0_CSPR_EXT,
 		CFG_SYS_NOR_AMASK,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -52,13 +52,13 @@
 			CFG_SYS_NOR_FTIM3
 		},
 		0,
-		CONFIG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR,
 		0,
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR_EARLY,
-		CONFIG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR1_CSPR_EARLY,
+		CFG_SYS_NOR0_CSPR_EXT,
 		CFG_SYS_NOR_AMASK_EARLY,
 		CFG_SYS_NOR_CSOR,
 		{
@@ -68,7 +68,7 @@
 			CFG_SYS_NOR_FTIM3
 		},
 		0,
-		CONFIG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR,
 		CFG_SYS_NOR_AMASK,
 	},
 	{
@@ -86,10 +86,10 @@
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
 		SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSOR,
 		{
 			SYS_FPGA_CS_FTIM0,
 			SYS_FPGA_CS_FTIM1,
@@ -121,10 +121,10 @@
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
 		SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSOR,
 		{
 			SYS_FPGA_CS_FTIM0,
 			SYS_FPGA_CS_FTIM1,
@@ -746,12 +746,12 @@
 
 	/* Read the BRDCFG54 via CLPD */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
+	ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR,
 		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 #else
 	struct udevice *dev;
 
-	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+	ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev);
 	if (!ret)
 		ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 				  (void *)&brdcfg4, 1);
@@ -766,7 +766,7 @@
 
 	/* Write to the BRDCFG4 */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
+	ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR,
 			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 #else
 	ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 971633c..a4cb1a6 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -118,10 +118,10 @@
 Environment Variables
 ---------------------
 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
-  the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+  the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
 
 - mcmemsize: MC DRAM block size. If this variable is not defined
-  the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+  the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
 -------------------------------------------------------------------
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 5df8572..91db618 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -217,7 +217,7 @@
 
 #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 #if CONFIG_IS_ENABLED(DM_I2C)
-	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
+	rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR);
 #else
 	rtc_enable_32khz_output();
 #endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 4376755..cf5b1ee 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -57,9 +57,9 @@
 
 static struct pl01x_serial_plat serial0 = {
 #if CONFIG_CONS_INDEX == 0
-	.base = CONFIG_SYS_SERIAL0,
+	.base = CFG_SYS_SERIAL0,
 #elif CONFIG_CONS_INDEX == 1
-	.base = CONFIG_SYS_SERIAL1,
+	.base = CFG_SYS_SERIAL1,
 #else
 #error "Unsupported console index value."
 #endif
@@ -72,7 +72,7 @@
 };
 
 static struct pl01x_serial_plat serial1 = {
-	.base = CONFIG_SYS_SERIAL1,
+	.base = CFG_SYS_SERIAL1,
 	.type = TYPE_PL011,
 };
 
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index efff055..d67db24 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -26,7 +26,7 @@
 	/*
 	 * Set LED on
 	 */
-	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED;
 	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
 
 	return 0;
@@ -42,13 +42,13 @@
 	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
 	 */
 
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
 	/*
 	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
 	 */
 	mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CONFIG_SYS_PLL_BYPASS
+#elif CFG_SYS_PLL_BYPASS
 	/*
 	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index bff1ac5..fbd4835 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -42,7 +42,7 @@
 	ulong size = 0;
 	ulong fbase = 0;
 
-	fbase = (ulong) CONFIG_SYS_FLASH_BASE;
+	fbase = (ulong) CFG_SYS_FLASH_BASE;
 	flash_get_size((FPWV *) fbase, &flash_info[0]);
 	flash_get_offsets((ulong) fbase, &flash_info[0]);
 	fbase += flash_info[0].size;
@@ -64,9 +64,9 @@
 
 		info->start[0] = base;
 		info->protect[0] = 0;
-		for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+		for (i = 1; i < CFG_SYS_SST_SECT; i++) {
 			info->start[i] = info->start[i - 1]
-						+ CONFIG_SYS_SST_SECTSZ;
+						+ CFG_SYS_SST_SECTSZ;
 			info->protect[i] = 0;
 		}
 	}
@@ -162,8 +162,8 @@
 
 	info->sector_count = 0;
 	info->size = 0;
-	info->sector_count = CONFIG_SYS_SST_SECT;
-	info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
+	info->sector_count = CFG_SYS_SST_SECT;
+	info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ;
 
 	/* reset ID mode */
 	*addr = (FPWV) 0x00F000F0;
@@ -222,7 +222,7 @@
 
 	start = get_timer(0);
 
-	if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
+	if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) {
 		if (prot == 0) {
 			addr = (FPWV *) info->start[0];
 
@@ -259,7 +259,7 @@
 				enable_interrupts();
 
 			return 0;
-		} else if (prot == CONFIG_SYS_SST_SECT) {
+		} else if (prot == CFG_SYS_SST_SECT) {
 			return 1;
 		}
 	}
@@ -282,7 +282,7 @@
 
 					flag = disable_interrupts();
 
-					base = (FPWV *) (CONFIG_SYS_FLASH_BASE);	/* First sector */
+					base = (FPWV *) (CFG_SYS_FLASH_BASE);	/* First sector */
 
 					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
 					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
@@ -411,7 +411,7 @@
 		return (2);
 	}
 
-	base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+	base = (FPWV *) (CFG_SYS_FLASH_BASE);
 
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 179a2a2..c1cff52 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -36,7 +36,7 @@
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
 		u32 RC, temp;
 
-		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+		RC = (CFG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
 
 		/* Initialize DRAM Control Register: DCR */
@@ -113,7 +113,7 @@
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 
 #define CALC_TIMING(t) (t + period - 1) / period
-		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
+		period = 1000000000 / (CFG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
 		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
index 0de36a7..34f05f3 100644
--- a/board/freescale/m53017evb/README
+++ b/board/freescale/m53017evb/README
@@ -68,7 +68,7 @@
 CONFIG_M53017EVB		-- define for M53017EVB board
 
 CONFIG_MCFUART			-- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CFG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
 CONFIG_BAUDRATE			-- define UART baudrate
 
 CONFIG_MCFRTC			-- define to use common CF RTC driver
@@ -96,11 +96,11 @@
 CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
 CONFIG_SYS_IMMR			-- define for MBAR offset
 
-CONFIG_SYS_MBAR			-- define MBAR offset
+CFG_SYS_MBAR			-- define MBAR offset
 
 CONFIG_MONITOR_IS_IN_RAM	-- Not support
 
-CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5301x internal SRAM
+CFG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5301x internal SRAM
 
 CONFIG_SYS_CSn_BASE		-- defines the Chip Select Base register
 CONFIG_SYS_CSn_MASK		-- defines the Chip Select Mask register
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index a10c365..d921eef 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -23,7 +23,7 @@
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd_to_nand(mtdinfo);
-	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+	volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
index bfbcd5d..7240648 100644
--- a/board/freescale/m5373evb/README
+++ b/board/freescale/m5373evb/README
@@ -67,7 +67,7 @@
 CONFIG_M5373EVB		-- define for M5373EVB board
 
 CONFIG_MCFUART		-- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CFG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
 CONFIG_BAUDRATE		-- define UART baudrate
 
 CONFIG_MCFRTC		-- define to use common CF RTC driver
@@ -95,11 +95,11 @@
 CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
 CONFIG_SYS_IMMR		-- define for MBAR offset
 
-CONFIG_SYS_MBAR		-- define MBAR offset
+CFG_SYS_MBAR		-- define MBAR offset
 
 CONFIG_MONITOR_IS_IN_RAM -- Not support
 
-CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5373 internal SRAM
+CFG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5373 internal SRAM
 
 CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
 CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index fdf3e0a..6d825a6 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -23,7 +23,7 @@
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd_to_nand(mtdinfo);
-	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+	volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 85d43cc..4a14554 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -22,7 +22,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
 int
 testdram(void)
 {
@@ -103,25 +103,25 @@
 	im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+	im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
 	udelay(50000);
 
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
 	udelay(1000);
 
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG;
 	udelay(1000);
 
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CFG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL;
 	sync();
 	udelay(1000);
 
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index d194388..7b6ef5b 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -12,7 +12,7 @@
 
 struct law_entry law_table[] = {
 	/* LBC window - maps 256M */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index e4c951f..73e024e 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -103,11 +103,11 @@
 
 	uint idx;
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 
 	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+	print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 		   "\n");
 
 	/*
@@ -115,17 +115,17 @@
 	 */
 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->lbcr = CFG_SYS_LBC_LBCR;
 	asm("msync");
 
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CFG_SYS_LBC_LSRT;
+	lbc->mrtpr = CFG_SYS_LBC_MRTPR;
 	asm("msync");
 
 	/*
 	 * MPC8548 uses "new" 15-16 style addressing.
 	 */
-	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON;
 	lsdmr_common |= LSDMR_BSMA1516;
 
 	/*
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index 9c8e948..994a32d 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -11,16 +11,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -29,7 +29,7 @@
 	 * Entry 0:
 	 * FLASH(cover boot page)	16M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -37,7 +37,7 @@
 	 * Entry 1:
 	 * CCSRBAR	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1M, 1),
 
@@ -45,8 +45,8 @@
 	 * Entry 2:
 	 * LBC SDRAM	64M	Cacheable, non-guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
-		      CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE,
+		      CFG_SYS_LBC_SDRAM_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 2, BOOKE_PAGESZ_64M, 1),
 
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 4f27d3e..d447ad8 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -42,7 +42,7 @@
 
 	int rev = readl(&fuse->gp[6]);
 
-	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+	if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR))
 		rev = 0;
 
 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
@@ -81,7 +81,7 @@
 	int ret;
 	struct pmic *p;
 
-	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+	if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) {
 		ret = pmic_dialog_init(I2C_PMIC);
 		if (ret)
 			return ret;
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
index 2dcee79..13fc2fa 100644
--- a/board/freescale/p1010rdb/law.c
+++ b/board/freescale/p1010rdb/law.c
@@ -8,8 +8,8 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 };
 
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index ab3b2e3..0f01482 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -83,7 +83,7 @@
 int board_early_init_f(void)
 {
 	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 	/* Clock configuration to access CPLD using IFC(GPCM) */
 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 	/*
@@ -97,7 +97,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -118,12 +118,12 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel, BOOKE_PAGESZ_16M, 1);
 
 	set_tlb(1, flashbase + 0x1000000,
-			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+			CFG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 	return 0;
@@ -138,7 +138,7 @@
 	struct udevice *dev;
 	int ret;
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 				      I2C_PCA9557_ADDR1, 1, &dev);
@@ -254,7 +254,7 @@
 #endif
 #else
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	switch (ctrl_type) {
 	case MUX_TYPE_IFC:
@@ -404,7 +404,7 @@
 int checkboard(void)
 {
 	struct cpu_type *cpu;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	u8 val;
 
 	cpu = gd->arch.cpu;
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 9bf948c..e450f62 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -29,7 +29,7 @@
 {
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 
 	console_init_f();
 
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 5e1fa70..265cde8 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -8,19 +8,19 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -36,17 +36,17 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_16M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
-			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000,
+			CFG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 3, BOOKE_PAGESZ_16M, 1),
 
@@ -64,7 +64,7 @@
 #endif
 
 	/* *I*G - Board CPLD  */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_256K, 1),
 
@@ -73,14 +73,14 @@
 			0, 7, BOOKE_PAGESZ_1M, 1),
 
 #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
 	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1)
 #endif
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index f896fd7..5f16779 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -201,7 +201,7 @@
 }
 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
 
-#ifdef CONFIG_SYS_DDR_CS0_BNDS
+#ifdef CFG_SYS_DDR_CS0_BNDS
 /* Fixed sdram init -- doesn't use serial presence detect. */
 phys_size_t fixed_sdram(void)
 {
@@ -209,35 +209,35 @@
 	char buf[32];
 	size_t ddr_size;
 	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
-		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+		.cs[0].bnds = CFG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CFG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2,
 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
-		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
-		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+		.cs[1].bnds = CFG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CFG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2,
 #endif
-		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
-		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
-		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
-		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
-		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
-		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
-		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CFG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CFG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CFG_SYS_DDR_INTERVAL,
 		.ddr_data_init = 0xdeadbeef, /* Poison value */
-		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
-		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+		.ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CFG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CFG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CFG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2
 	};
 
 	get_sys_info(&sysinfo);
@@ -248,7 +248,7 @@
 
 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
-	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+	if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE,
 				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
 		printf("ERROR setting Local Access Windows for DDR\n");
 		return 0;
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 8f3f484..6085984 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -8,11 +8,11 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_VSC7385_ENET
-	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 #ifdef CFG_SYS_NAND_BASE_PHYS
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
 #endif
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 2999c85..ab79724 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -90,20 +90,20 @@
 	 * This ensures that external watchdog does not trigger
 	 * another reset or possible infinite reset loop.
 	 */
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
 	in_8(&cpld_data->wd_cfg); /* Read back to sync write */
 }
 
 void board_reset_last(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	out_8(&cpld_data->system_rst, 1);
 }
 
 void board_cpld_init(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
 
 	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
@@ -226,7 +226,7 @@
 
 int checkboard(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u8 in, out, invert, io_config, val;
 	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
@@ -246,7 +246,7 @@
 	struct udevice *dev;
 	int ret;
 
-	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
+	ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR,
 				      1, &dev);
 	if (ret) {
 		printf("%s: Cannot find udev for a bus %d\n", __func__,
@@ -264,10 +264,10 @@
 	#else /* Non DM I2C support - will be removed */
 	i2c_set_bus_num(bus_num);
 
-	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
-	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
-	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
-	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
+	if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
+	    i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+	    i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
+	    i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
 	}
@@ -319,7 +319,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 #ifdef CONFIG_VSC7385_ENET
 	unsigned int vscfw_addr;
@@ -344,7 +344,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
 
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 4cc5e01..9477396 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -8,20 +8,20 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+			CFG_SYS_INIT_RAM_ADDR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -32,14 +32,14 @@
 			0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_64M, 1),
 
@@ -57,13 +57,13 @@
 
 #ifdef CONFIG_VSC7385_ENET
 	/* *I*G - VSC7385 Switch */
-	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 5, BOOKE_PAGESZ_1M, 1),
 #endif
 #endif /* not SPL */
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
 
@@ -76,27 +76,27 @@
 
 #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
 	/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
 	/* **M** - 2G DDR on P1020MBG, map the second 1G */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif /* RAMBOOT/SPL */
 
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
 	/* ***G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1),
 #if CONFIG_SYS_L2_SIZE >= (256 << 10)
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000,
+		      CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 12, BOOKE_PAGESZ_256K, 1)
 #endif
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 23ec32b..3e12c81 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -35,10 +35,10 @@
 };
 
 static int riser_phy_addr[] = {
-	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
 };
 
 /*
@@ -101,12 +101,12 @@
 		slot = lane_to_slot[lane];
 		if (slot) {
 			sprintf(phy, "phy_sgmii_%x",
-					CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+					CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
 					+ (port - FM1_DTSEC1));
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		} else {
 			sprintf(phy, "phy_sgmii_%x",
-					CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
+					CFG_SYS_FM1_DTSEC1_PHY_ADDR
 					+ (port - FM1_DTSEC1));
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		}
@@ -158,9 +158,9 @@
 	 * is RGMII, we'll also override its PHY address later. We assume that
 	 * DTSEC4 and DTSEC5 are used for RGMII.
 	 */
-	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR);
 
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1;
@@ -180,8 +180,8 @@
 		case PHY_INTERFACE_MODE_RGMII_ID:
 			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
 			fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
-					CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
-					CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+					CFG_SYS_FM1_DTSEC5_PHY_ADDR :
+					CFG_SYS_FM1_DTSEC4_PHY_ADDR);
 			break;
 		default:
 			printf("Fman1: DTSEC%u set to unknown interface %i\n",
@@ -198,7 +198,7 @@
 		slot = lane_to_slot[lane];
 		if (slot)
 			fm_info_set_phy_address(FM1_10GEC1,
-					CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+					CFG_SYS_FM1_10GEC1_PHY_ADDR);
 	}
 
 	fm_info_set_mdio(FM1_10GEC1,
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 1b12630..575259b 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -119,7 +119,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -140,7 +140,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c
index 47c3b16..17a6226 100644
--- a/board/freescale/t102xrdb/cpld.c
+++ b/board/freescale/t102xrdb/cpld.c
@@ -14,14 +14,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index 818c20c..1b41739 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -222,7 +222,7 @@
 #if defined(CONFIG_DEEP_SLEEP)
 void board_mem_sleep_setup(void)
 {
-	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+	void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
 
 	/* does not provide HW signals for power management */
 	clrbits_8(cpld_base + 0x17, 0x40);
diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
index 850ece0..d636bef 100644
--- a/board/freescale/t102xrdb/law.c
+++ b/board/freescale/t102xrdb/law.c
@@ -9,19 +9,19 @@
 
 struct law_entry law_table[] = {
 #ifdef CONFIG_MTD_NOR_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CFG_SYS_NAND_BASE_PHYS
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index f777f5a..baa5961 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -130,8 +130,8 @@
 
 int board_early_init_r(void)
 {
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 	/*
 	 * Remap Boot flash region to caching-inhibited
@@ -150,7 +150,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
index 74744c8..2519a9e 100644
--- a/board/freescale/t102xrdb/tlb.c
+++ b/board/freescale/t102xrdb/tlb.c
@@ -8,31 +8,31 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
 	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 #else
@@ -42,13 +42,13 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -64,27 +64,27 @@
 		      0, 4, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 #endif
@@ -93,18 +93,18 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1),
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
index ac34095..9ac57bb 100644
--- a/board/freescale/t104xrdb/cpld.c
+++ b/board/freescale/t104xrdb/cpld.c
@@ -7,7 +7,7 @@
  *
  * The following macros need to be defined:
  *
- * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
+ * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
  */
 
 #include <common.h>
@@ -18,14 +18,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 539a36d..02ddb66 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -115,7 +115,7 @@
 #if defined(CONFIG_DEEP_SLEEP)
 void board_mem_sleep_setup(void)
 {
-	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+	void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
 
 	/* does not provide HW signals for power management */
 	clrbits_8(cpld_base + 0x17, 0x40);
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 5ce24b4..fe51d68 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -49,7 +49,7 @@
 			 * DTSEC3
 			 */
 			fm_info_set_phy_address(FM1_DTSEC3,
-						CONFIG_SYS_SGMII1_PHY_ADDR);
+						CFG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
 #ifdef CONFIG_TARGET_T1042RDB
@@ -59,7 +59,7 @@
 				fm_info_set_phy_address(i, 0);
 			/* T1042RDB only supports SGMII on DTSEC3 */
 			fm_info_set_phy_address(FM1_DTSEC3,
-						CONFIG_SYS_SGMII1_PHY_ADDR);
+						CFG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
 #ifdef CONFIG_TARGET_T1042D4RDB
@@ -68,11 +68,11 @@
 			 *  & DTSEC3
 			 */
 			if (FM1_DTSEC1 == i)
-				phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+				phy_addr = CFG_SYS_SGMII1_PHY_ADDR;
 			if (FM1_DTSEC2 == i)
-				phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+				phy_addr = CFG_SYS_SGMII2_PHY_ADDR;
 			if (FM1_DTSEC3 == i)
-				phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+				phy_addr = CFG_SYS_SGMII3_PHY_ADDR;
 			fm_info_set_phy_address(i, phy_addr);
 			break;
 #endif
@@ -81,9 +81,9 @@
 		case PHY_INTERFACE_MODE_RGMII_RXID:
 		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (FM1_DTSEC4 == i)
-				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+				phy_addr = CFG_SYS_RGMII1_PHY_ADDR;
 			if (FM1_DTSEC5 == i)
-				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+				phy_addr = CFG_SYS_RGMII2_PHY_ADDR;
 			fm_info_set_phy_address(i, phy_addr);
 			break;
 		case PHY_INTERFACE_MODE_QSGMII:
@@ -112,7 +112,7 @@
 	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
 		for (i = 0; i < 4; i++) {
 			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-			phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+			phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i;
 			phy_int = PHY_INTERFACE_MODE_QSGMII;
 
 			vsc9953_port_info_set_mdio(i, bus);
@@ -124,7 +124,7 @@
 	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
 		for (i = 4; i < 8; i++) {
 			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-			phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+			phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
 			phy_int = PHY_INTERFACE_MODE_QSGMII;
 
 			vsc9953_port_info_set_mdio(i, bus);
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
index 2f00d80..a0d6eb5 100644
--- a/board/freescale/t104xrdb/law.c
+++ b/board/freescale/t104xrdb/law.c
@@ -9,19 +9,19 @@
 
 struct law_entry law_table[] = {
 #ifdef CONFIG_MTD_NOR_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CFG_SYS_NAND_BASE_PHYS
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 66a142b..dd8283f 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -46,7 +46,7 @@
 		porsr1 = in_be32(&gur->porsr1);
 		pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
 			  | 0x24800000);
-		out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+		out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000),
 			 pinctl);
 	}
 #endif
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 7d3fd29..45ebdd3 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -62,8 +62,8 @@
 
 int board_early_init_r(void)
 {
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -84,7 +84,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 905e477..10be580 100644
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -8,32 +8,32 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \
 	!defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
 	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 
@@ -44,8 +44,8 @@
 	 * and virtual address is 0xfffc0000
 	 */
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
-		      CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR,
+		      CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 #else
@@ -55,13 +55,13 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -77,27 +77,27 @@
 		      0, 4, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 #endif
@@ -111,18 +111,18 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1),
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
index f97467e..3cdd493 100644
--- a/board/freescale/t208xqds/law.c
+++ b/board/freescale/t208xqds/law.c
@@ -11,19 +11,19 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
 #ifdef QIXIS_BASE_PHYS
 	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CFG_SYS_NAND_BASE_PHYS
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 82710cf..8be55e5 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -282,7 +282,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -303,7 +303,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index f2448e8..3d220af 100644
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -11,31 +11,31 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_1M, 1),
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -54,13 +54,13 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -92,27 +92,27 @@
 		      0, 7, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
@@ -143,7 +143,7 @@
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c
index b9ba62a..933fa0d 100644
--- a/board/freescale/t208xrdb/cpld.c
+++ b/board/freescale/t208xrdb/cpld.c
@@ -11,14 +11,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }
diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c
index 3ff4c77..53a1369 100644
--- a/board/freescale/t208xrdb/law.c
+++ b/board/freescale/t208xrdb/law.c
@@ -11,19 +11,19 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CFG_SYS_NAND_BASE_PHYS
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 1c8017b..04cb313 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -77,7 +77,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 	/*
 	 * Remap Boot flash + PROMJET region to caching-inhibited
@@ -96,7 +96,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 45c27c0..688a208 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -11,31 +11,31 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_1M, 1),
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -54,13 +54,13 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -92,27 +92,27 @@
 		      0, 7, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
@@ -126,8 +126,8 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
 #endif
@@ -142,7 +142,7 @@
 		      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
index d484509..8b10120 100644
--- a/board/freescale/t4rdb/cpld.c
+++ b/board/freescale/t4rdb/cpld.c
@@ -9,7 +9,7 @@
  *
  * The following macros need to be defined:
  *
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CFG_SYS_CPLD_BASE - The virtual address of the base of the
  * CPLD register map
  *
  */
@@ -22,14 +22,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }
diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
index 4385896..43eeb88 100644
--- a/board/freescale/t4rdb/law.c
+++ b/board/freescale/t4rdb/law.c
@@ -8,19 +8,19 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CFG_SYS_NAND_BASE_PHYS
 	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 20ce752..0bd0ba9 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -54,7 +54,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -75,7 +75,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index c57af30..f5af893 100644
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -8,29 +8,29 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 512K SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_512K, 1),
 #else
@@ -40,13 +40,13 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -73,28 +73,28 @@
 		      0, 6, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
 
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
@@ -108,13 +108,13 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 18, BOOKE_PAGESZ_2G, 1)
 #endif