global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2c320b2..f07e8ab 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -165,7 +165,7 @@
for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
- struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+ struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR);
if (law.index == -1) {
printf("\nFatal error happened\n");
@@ -315,15 +315,15 @@
{
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_pll_ratio;
- u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
- u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
- u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
+ u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
+ u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
+ u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80);
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
- u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
- u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
+ u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40);
+ u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48);
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
- u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
- u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
+ u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60);
+ u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68);
#endif
#endif
/*
@@ -378,7 +378,7 @@
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
@@ -403,7 +403,7 @@
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
/* Disable the LAW created for NOR flash by the PBI commands */
- law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+ law = find_law(CFG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
@@ -430,7 +430,7 @@
/* Invalidate the CPC before DDR gets enabled */
invalidate_cpc();
- #ifdef CONFIG_SYS_DCSRBAR_PHYS
+ #ifdef CFG_SYS_DCSRBAR_PHYS
/* set DCSRCR so that DCSR space is 1G */
setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
in_be32(&gur->dcsrcr);
@@ -533,7 +533,7 @@
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR)
if (cache_ctl & MPC85xx_L2CTL_L2E) {
/* Clear L2 SRAM memory-mapped base address */
out_be32(&l2cache->l2srbar0, 0x0);
@@ -590,15 +590,15 @@
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
puts("already enabled");
-#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE)
u32 l2srbar = l2cache->l2srbar0;
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
- && l2srbar >= CONFIG_SYS_FLASH_BASE) {
- l2srbar = CONFIG_SYS_INIT_L2_ADDR;
+ && l2srbar >= CFG_SYS_FLASH_BASE) {
+ l2srbar = CFG_SYS_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
- printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
+ printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR);
}
-#endif /* CONFIG_SYS_INIT_L2_ADDR */
+#endif /* CFG_SYS_INIT_L2_ADDR */
puts("\n");
} else {
asm("msync;isync");
@@ -625,9 +625,9 @@
#endif
/* enable the cache */
- mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
+ mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0);
- if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
+ if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
;
print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
@@ -656,7 +656,7 @@
int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
@@ -763,13 +763,13 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
int i;
- __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+ __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
for (i = 0; i < 12; i++) {
p += i + (i > 5 ? 11 : 0);
out_be32(p, 0x2);
}
- p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+ p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108;
out_be32(p, 0x34);
}
#endif
@@ -799,18 +799,18 @@
{
if (SVR_MAJ(svr) < 3) {
void *p;
- p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ p = (void *)CFG_SYS_DCSRBAR + 0x20520;
setbits_be32(p, 1 << (31 - 14));
}
}
#endif
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing
* speed for NOR flash.
*/
- clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+ clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
@@ -850,7 +850,7 @@
*/
if (IS_SVR_REV(get_svr(), 1, 0)) {
struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
- (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
+ (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET);
setbits_be32(&dcfg->ecccr1,
(DCSR_DCFG_ECC_DISABLE_USB1 |
DCSR_DCFG_ECC_DISABLE_USB2));