global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 1f8cdf8..67ad5e5 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -659,7 +659,7 @@
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
/* The L2 cache is already disabled at this point */
@@ -691,7 +691,7 @@
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 3b96188..e6383d4 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -54,7 +54,7 @@
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
-#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
+#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
@@ -146,7 +146,7 @@
#define BOOT_FROM_UART 0x30
#define BOOT_FROM_SPI 0x38
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
200000000 : 166000000)
#elif defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
@@ -169,7 +169,7 @@
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
200000000 : 250000000)
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
@@ -188,7 +188,7 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+#define CFG_SYS_TCLK 200000000 /* 200MHz */
#elif defined(CONFIG_ARMADA_XP)
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
@@ -209,7 +209,7 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+#define CFG_SYS_TCLK 250000000 /* 250MHz */
#endif
#endif /* _MVEBU_SOC_H */
diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S
index 60c2072..6c9783a 100644
--- a/arch/arm/mach-mvebu/lowlevel.S
+++ b/arch/arm/mach-mvebu/lowlevel.S
@@ -35,10 +35,10 @@
* Disable L2 cache
*
* NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
- * but CONFIG_SYS_PL310_BASE is already calculated from base
+ * but CFG_SYS_PL310_BASE is already calculated from base
* address SOC_REGS_PHY_BASE.
*/
- ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
+ ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
ldr r0, [r1, #L2X0_CTRL_OFF]
bic r0, #L2X0_CTRL_EN
str r0, [r1, #L2X0_CTRL_OFF]