diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 0000000..db0b4cb
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/spl.h>
+#include <asm/io.h>
+#include <log.h>
+#include <spl.h>
+
+#define JH7110_CLK_CPU_ROOT_OFFSET		0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT		24
+#define JH7110_CLK_CPU_ROOT_MASK		GENMASK(29, 24)
+
+int spl_board_init_f(void)
+{
+	int ret;
+
+	ret = spl_soc_init();
+	if (ret) {
+		debug("JH7110 SPL init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode;
+
+	mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+				& JH7110_BOOT_MODE_SELECT_MASK;
+	switch (mode) {
+	case 0:
+		return BOOT_DEVICE_SPI;
+
+	case 1:
+		return BOOT_DEVICE_MMC2;
+
+	case 2:
+		return BOOT_DEVICE_MMC1;
+
+	case 3:
+		return BOOT_DEVICE_UART;
+
+	default:
+		debug("Unsupported boot device 0x%x.\n", mode);
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	ret = spl_early_init();
+	if (ret)
+		panic("spl_early_init() failed: %d\n", ret);
+
+	riscv_cpu_setup(NULL, NULL);
+	preloader_console_init();
+
+	/* Set the parent clock of cpu_root clock to pll0,
+	 * it must be initialized here
+	 */
+	clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
+			JH7110_CLK_CPU_ROOT_MASK,
+			BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+
+	ret = spl_board_init_f();
+	if (ret) {
+		debug("spl_board_init_f init failed: %d\n", ret);
+		return;
+	}
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif