| commit | 517912b2c3a76cfdbe873fbed94e0fc2d505c972 | [log] [tgz] |
|---|---|---|
| author | Aneesh V <aneesh@ti.com> | Thu Aug 11 04:35:44 2011 +0000 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sun Sep 04 11:36:16 2011 +0200 |
| tree | ba83eab86729a1871261d10512178ccc1d2c9a65 | |
| parent | 572134b3275742ed0ebbe5784a7a32e8da9a16f5 [diff] |
armv7: stronger barrier for cache-maintenance operations set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V <aneesh@ti.com>