| commit | 6e2af916e852c735f094042119d80dba6b1fbe38 | [log] [tgz] |
|---|---|---|
| author | Bai Ping <ping.bai@nxp.com> | Mon Jul 22 01:24:45 2019 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Tue Oct 08 16:35:16 2019 +0200 |
| tree | 2167028c54a52fb6cd19a5b57be02c2099e2407c | |
| parent | b1b61c639326d7bfb37cc8f0d0852301a78f22b7 [diff] |
i.MX7ULP: Correct the clock index On i.MX7ULP, value zero is reserved in SCG1 RCCR register, so the val should be decreased by 1 to get the correct clock source index. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>