net: ftgmac100: Fixed the cache coherency issues of rx memory
When executing TFTP, the ARP will be replied to after receiving
the ARP. U-boot's ARP routine modifies the data in the receive
packet in response to the ARP packet and then copies it
into the transmit packet.
At this point, the received packet cache is inconsistent.
It is possible that the cache will perform a writeback action to
affect the MAC receiving packets.
Avoid the same problem that occurs in other networking protocols.
In the free_pkt function, ensure cache and memory consistency.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 8781e50..853a991 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -410,6 +410,14 @@
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ /*
+ * Make sure there are no stale data in write-back over this area, which
+ * might get written into the memory while the ftgmac100 also writes
+ * into the same memory area.
+ */
+ flush_dcache_range((ulong)net_rx_packets[priv->rx_index],
+ (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN);
+
/* Release buffer to DMA and flush descriptor */
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
flush_dcache_range(des_start, des_end);