tree 457eb9e9d46d4dbc476ca3d4a649ef6313083d2a
parent 7cff76b5c13421c2470f962eecbd5d0563dcc84f
author Alexander Dahl <ada@thorsis.com> 1713167875 +0200
committer Eugen Hristev <eugen.hristev@linaro.org> 1739350196 +0200

mtd: nand: raw: atmel: Fix pulse read timing for certain NAND flashes

From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse time must be at least tREA.

Without this fix we got PMECC errors when reading, after switching to
ONFI timing mode 3 on SAM9X60 SoC with S34ML02G1 raw NAND flash chip.

The approach to set timings used before worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.

The approach to fix the issue was carried over from at91bootstrap, and
has been successfully tested in at91bootstrap, U-Boot and Linux.

Link: https://github.com/linux4sam/at91bootstrap/issues/174
Cc: Li Bin <bin.li@microchip.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>