drivers: mtd: nand: cadence: Use bounce buffer
Enable nand to use bounce buffer. In bounce buffer,
read/write buf will use cadence->buf which has been allocated
using malloc. This will align the memory and avoid memory to be
allocated in different addresses.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c
index e571e5a..27aa7f9 100644
--- a/drivers/mtd/nand/raw/cadence_nand.c
+++ b/drivers/mtd/nand/raw/cadence_nand.c
@@ -980,7 +980,7 @@
cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT);
if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
- cadence->caps2.data_control_supp) {
+ cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
u8 *oob;
if (oob_required)
@@ -1156,7 +1156,7 @@
* is supported then transfer data and oob directly.
*/
if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
- cadence->caps2.data_control_supp) {
+ cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
u8 *oob;
if (oob_required)
@@ -1859,6 +1859,7 @@
return ret;
}
+ chip->options |= NAND_USE_BOUNCE_BUFFER;
chip->bbt_options |= NAND_BBT_USE_FLASH;
chip->bbt_options |= NAND_BBT_NO_OOB;
chip->ecc.mode = NAND_ECC_HW_SYNDROME;