| commit | 1b1e5cf63712251da294ac06a0df081fec174dfc | [log] [tgz] |
|---|---|---|
| author | Zang Roy-R61911 <tie-fei.zang@freescale.com> | Thu Nov 28 13:23:37 2013 +0800 |
| committer | York Sun <yorksun@freescale.com> | Wed Dec 04 14:54:42 2013 -0800 |
| tree | 29daad933328ec9d6d20b8861399ec8f68319e45 | |
| parent | fed1d31589e28e0780b6fdd6084d0dad7700e8d2 [diff] |
T4240: Address T4240/T4160 Rev2.0 DDR clock change MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>