configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index af93aef..6f221a3 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -54,13 +54,35 @@
CONFIG_LBLAW1_BASE=0xE0600000
CONFIG_LBLAW1_NAME="FPGA0"
CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
-CONFIG_SICR_GPIO_A_GPIO=y
-CONFIG_SICR_GPIO_B_GPIO=y
CONFIG_SICR_IEEE1588_A_GPIO=y
CONFIG_SICR_GTM_GPIO=y
CONFIG_SICR_ETSEC2_GPIO=y
@@ -70,6 +92,8 @@
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -103,31 +127,3 @@
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_MACHINE_GPCM=y
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_MACHINE_GPCM=y
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y