| commit | 66803dedfd11e4af5ffac33700a3923444aec7be | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Mon May 07 22:22:26 2018 +0200 |
| committer | Marek Vasut <marex@denx.de> | Wed Jul 25 00:13:32 2018 +0200 |
| tree | e81ae5caa33279729457ea7ab0e93ff6c7ef5417 | |
| parent | 3e034a3e3b074697e1478e211603cb0c3ffa7fa0 [diff] |
ARM: dts: socfpga: Adjust NAND register layout on Arria10 Adjust the NAND register size on Arria10 to reflect reality. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>