| commit | 3b5179f68fbaa5e07970248374e9cbbe3297452b | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Mon Oct 08 07:44:31 2012 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Mon Oct 22 14:31:33 2012 -0500 |
| tree | 36010ca075f6ce2e62902c4b6321eff04f8cd5b4 | |
| parent | 2394a0f45bb2e673210d90f1ef10330594efe3ba [diff] |
powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>