diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f28fc37..d6f7996 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -379,6 +379,8 @@
 	fsl-ls2088a-rdb-qspi.dtb \
 	fsl-ls1088a-rdb.dtb \
 	fsl-ls1088a-qds.dtb \
+	fsl-ls1088a-qds-21-x.dtb \
+	fsl-ls1088a-qds-29-x.dtb \
 	fsl-ls1028a-rdb.dtb \
 	fsl-ls1028a-qds-duart.dtb \
 	fsl-ls1028a-qds-lpuart.dtb \
diff --git a/arch/arm/dts/fsl-ls1088a-qds-21-x.dts b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts
new file mode 100644
index 0000000..a877964
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES protocol 21.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a-qds-sd1-21.dtsi"
+
+/ {
+	model = "NXP Layerscape 1088a QDS Board (DTS 21-x)";
+	compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-29-x.dts b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts
new file mode 100644
index 0000000..29c4ec5
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES protocol 29.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a-qds-sd1-29.dtsi"
+
+/ {
+	model = "NXP Layerscape 1088a QDS Board (DTS 29-x)";
+	compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
new file mode 100644
index 0000000..e0a6c04
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15)
+ *
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls1088a-qds.dtsi"
+
+&dpmac1 {
+	status = "okay";
+	phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-connection-type = "xfi";
+};
+
+&dpmac4 {
+	status = "okay";
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+};
+
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&rgmii_phy2>;
+	phy-connection-type = "rgmii-id";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
new file mode 100644
index 0000000..65e95300
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 29 (0x1d)
+ *
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls1088a-qds.dtsi"
+
+&dpmac1 {
+	status = "okay";
+	phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-connection-type = "xfi";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts
index 4f37a28..8e64e71 100644
--- a/arch/arm/dts/fsl-ls1088a-qds.dts
+++ b/arch/arm/dts/fsl-ls1088a-qds.dts
@@ -1,132 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * NXP ls1088a QDS board device tree source
+ * NXP ls1088a QDS default board device tree source
  *
- * Copyright 2017 NXP
+ * Copyright 2020 NXP
  */
 
 /dts-v1/;
 
-#include "fsl-ls1088a.dtsi"
+#include "fsl-ls1088a-qds.dtsi"
 
 / {
 	model = "NXP Layerscape 1088a QDS Board";
 	compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
-	aliases {
-		spi0 = &qspi;
-		spi1 = &dspi;
-	};
-};
-
-&i2c0 {
-	status = "okay";
-	u-boot,dm-pre-reloc;
-
-	i2c-mux@77 {
-		compatible = "nxp,pca9547";
-		reg = <0x77>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		i2c@3 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x3>;
-
-			rtc@51 {
-				compatible = "pcf2127-rtc";
-				reg = <0x51>;
-			};
-		};
-	};
-};
-
-&ifc {
-	#address-cells = <2>;
-	#size-cells = <1>;
-	/* NOR, NAND Flashes and FPGA on board */
-	ranges = <0 0 0x5 0x80000000 0x08000000
-			2 0 0x5 0x30000000 0x00010000
-			3 0 0x5 0x20000000 0x00010000>;
-	status = "okay";
-
-	nor@0,0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "cfi-flash";
-		reg = <0x0 0x0 0x8000000>;
-		bank-width = <2>;
-		device-width = <1>;
-	};
-
-	nand@2,0 {
-		compatible = "fsl,ifc-nand";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x1 0x0 0x10000>;
-	};
-
-	fpga: board-control@3,0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "simple-bus", "fsl,ls1088aqds-fpga",
-				"fsl,fpga-qixis";
-		reg = <0x2 0x0 0x0000100>;
-		bank-width = <1>;
-		device-width = <1>;
-		ranges = <0 2 0 0x100>;
-	};
-};
-
-&dspi {
-	bus-num = <0>;
-	status = "okay";
-
-	dflash0: n25q128a {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <1000000>; /* input clock */
-	};
-
-	dflash1: sst25wf040b {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3500000>;
-		reg = <1>;
-	};
-
-	dflash2: en25s64 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <3500000>;
-		reg = <2>;
-	};
-};
-
-&qspi {
-	status = "okay";
-
-	s25fs512s0: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-	};
-
-	s25fs512s1: flash@1 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-		reg = <1>;
-	 };
-};
-
-&sata {
-	status = "okay";
 };
diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi
new file mode 100644
index 0000000..a7d0edc
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1088a QDS common board device tree source
+ *
+ * Copyright 2017-2020 NXP
+ */
+
+#include "fsl-ls1088a.dtsi"
+
+/ {
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi;
+	};
+};
+
+&emdio1 {
+	status = "okay";
+};
+
+&emdio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	fpga@66 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "simple-mfd";
+		reg = <0x66>;
+
+		mux-mdio@54 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mdio-mux-i2creg";
+			reg = <0x54>;
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
+			mdio-parent-bus = <&emdio1>;
+
+			mdio@00 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x00>;
+
+				rgmii_phy1: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+			};
+			mdio@20 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x20>;
+
+				rgmii_phy2: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+
+			emdio1_slot1: mdio@40 { /* I/O Slot #1 */
+				reg = <0x40>;
+				device-name = "emdio1_slot1";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			emdio1_slot3: mdio@60 { /* I/O Slot #3 */
+				reg = <0x60>;
+				device-name = "emdio1_slot3";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			rtc@51 {
+				compatible = "pcf2127-rtc";
+				reg = <0x51>;
+			};
+		};
+	};
+};
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR, NAND Flashes and FPGA on board */
+	ranges = <0 0 0x5 0x80000000 0x08000000
+			2 0 0x5 0x30000000 0x00010000
+			3 0 0x5 0x20000000 0x00010000>;
+	status = "okay";
+
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x8000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
+
+	nand@2,0 {
+		compatible = "fsl,ifc-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x1 0x0 0x10000>;
+	};
+
+	fpga: board-control@3,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus", "fsl,ls1088aqds-fpga",
+				"fsl,fpga-qixis";
+		reg = <0x2 0x0 0x0000100>;
+		bank-width = <1>;
+		device-width = <1>;
+		ranges = <0 2 0 0x100>;
+	};
+};
+
+&dspi {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q128a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <1000000>; /* input clock */
+	};
+
+	dflash1: sst25wf040b {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <3500000>;
+		reg = <1>;
+	};
+
+	dflash2: en25s64 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <3500000>;
+		reg = <2>;
+	};
+};
+
+&qspi {
+	status = "okay";
+
+	s25fs512s0: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	s25fs512s1: flash@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	 };
+};
+
+&sata {
+	status = "okay";
+};