tree 13eb99a9c67cb1a21cadfb5089249310be548abd
parent f5ff7bc7d6ef0863b3aa49772f90dbb8776b9936
author Michal Simek <michal.simek@xilinx.com> 1368020248 +0200
committer Michal Simek <michal.simek@xilinx.com> 1376290795 +0200

zynq: slcr: Wait 100ms till clk is properly setup

If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>