| commit | 65ed12cf6fd714ed58c189fe06942ff298e9b9d1 | [log] [tgz] |
|---|---|---|
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | Fri Feb 26 14:21:38 2016 +0900 |
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | Mon Feb 29 03:50:16 2016 +0900 |
| tree | bdc2a6417b93553f6c641d77bc7e5fd7547364e8 | |
| parent | f98edfebfc4d9295145ebf599f3adc26b2067cfe [diff] |
ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings These settings were used only for the PH1-sLD3 and older SoCs. The PH1-LD4 and newer one just ignore them because their DDR-PHY take care of such timing parameters instead. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>