WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
index 6d77ad3..4b96d4a 100644
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -45,7 +45,7 @@
#define TIMER 0 /* Use TIMER 0 */
/* Each timer has 3 match registers */
#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 7def44a..5266515 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -64,18 +64,18 @@
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
- .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
- .word 0xe5901008 // ldr r1, [r0, #8]
- .word 0xe129f001 // msr CPSR_fc, r1
+ .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
+ .word 0xe5901008 // ldr r1, [r0, #8]
+ .word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
- .word 0xe590d000 // ldr sp, [r0]
- .word 0xe590e004 // ldr lr, [r0, #4]
- .word 0xe5901010 // ldr r1, [r0, #16]
- .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
- .word 0xe590100c // ldr r1, [r0, #12]
- .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
+ .word 0xe590d000 // ldr sp, [r0]
+ .word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901010 // ldr r1, [r0, #16]
+ .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
+ .word 0xe590100c // ldr r1, [r0, #12]
+ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
- .word 0xe12fff1e // bx lr ; return to FEL
+ .word 0xe12fff1e // bx lr ; return to FEL
fel_stash_addr:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 6c98d99..9119d60 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -42,22 +42,22 @@
pre-silicon platforms (simulator and emulator):
-------------------------
- | FIT Image |
+ | FIT Image |
| (linux + DTB + RFS) |
------------------------- ----> 0x0120_0000
- | Debug Server FW |
+ | Debug Server FW |
------------------------- ----> 0x00C0_0000
- | AIOP FW |
+ | AIOP FW |
------------------------- ----> 0x0070_0000
- | MC FW |
+ | MC FW |
------------------------- ----> 0x006C_0000
- | MC DPL Blob |
+ | MC DPL Blob |
------------------------- ----> 0x0020_0000
- | BootLoader + Env|
+ | BootLoader + Env|
------------------------- ----> 0x0000_1000
- | PBI |
+ | PBI |
------------------------- ----> 0x0000_0080
- | RCW |
+ | RCW |
------------------------- ----> 0x0000_0000
32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
@@ -70,45 +70,45 @@
----------------------------------------- ----> 0x5_8790_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8510_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_84F0_0000 | 64K
| Debug Server FW (2M) | | Alt
----------------------------------------- ----> 0x5_84D0_0000 | Bank
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8490_0000 (vbank4)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8480_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8470_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8430_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8420_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8410_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8400_0000 ---
| .. Unused .. (7M) | |
----------------------------------------- ----> 0x5_8390_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8110_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_80F0_0000 | 64K
| Debug Server FW (2M) | | Bank
----------------------------------------- ----> 0x5_80D0_0000 |
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8090_0000 (vbank0)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8080_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8070_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8030_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8020_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8010_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8000_0000 ---
128-MB NOR flash layout for QDS and RDB boards
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index d880373..3aa1a9c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -250,7 +250,7 @@
* b. We use only Region0 whose NSAID write/read is EN
*
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
- * placeholders.
+ * placeholders.
*/
.macro tzasc_prog, xreg
@@ -259,7 +259,7 @@
mov x16, #0x10000
mul x14, \xreg, x16
add x14, x14,x12
- mov x1, #0x8
+ mov x1, #0x8
add x1, x1, x14
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h
index 9456719..e079edf 100644
--- a/arch/arm/dts/vf610-pinfunc.h
+++ b/arch/arm/dts/vf610-pinfunc.h
@@ -424,7 +424,7 @@
#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
-#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
index a808ee8..cd837ea 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -17,7 +17,7 @@
/*
* Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
*
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
/* UART1 */
#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 5780969..d5ea868 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -50,11 +50,11 @@
/* Enhanced SDRAM Controller (ESDRAMC) registers */
struct esdramc_regs {
- u32 ctl0; /* control 0 */
- u32 cfg0; /* configuration 0 */
- u32 ctl1; /* control 1 */
- u32 cfg1; /* configuration 1 */
- u32 misc; /* miscellaneous */
+ u32 ctl0; /* control 0 */
+ u32 cfg0; /* configuration 0 */
+ u32 ctl1; /* control 1 */
+ u32 cfg1; /* configuration 1 */
+ u32 misc; /* miscellaneous */
u32 pad[3];
u32 cdly1; /* Delay Line 1 configuration debug */
u32 cdly2; /* delay line 2 configuration debug */
@@ -66,11 +66,11 @@
/* General Purpose Timer (GPT) registers */
struct gpt_regs {
- u32 ctrl; /* control */
- u32 pre; /* prescaler */
- u32 stat; /* status */
- u32 intr; /* interrupt */
- u32 cmp[3]; /* output compare 1-3 */
+ u32 ctrl; /* control */
+ u32 pre; /* prescaler */
+ u32 stat; /* status */
+ u32 intr; /* interrupt */
+ u32 cmp[3]; /* output compare 1-3 */
u32 capt[2]; /* input capture 1-2 */
u32 counter; /* counter */
};
@@ -456,7 +456,7 @@
#define GPT_CTRL_TEN 1 /* Timer enable */
/* WDOG enable */
-#define WCR_WDE 0x04
+#define WCR_WDE 0x04
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 2731b7f..f763749 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -43,7 +43,7 @@
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
@@ -97,7 +97,7 @@
#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
index 7e61d22..4d12c68 100644
--- a/arch/arm/include/asm/arch-mx6/mx6_plugin.S
+++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
@@ -7,10 +7,10 @@
#ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#else
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
-#define ROM_VERSION_OFFSET 0x48
+#define ROM_VERSION_OFFSET 0x48
#endif
#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
diff --git a/arch/arm/include/asm/arch-mx7/mx7_plugin.S b/arch/arm/include/asm/arch-mx7/mx7_plugin.S
index c7a84e8..b552542 100644
--- a/arch/arm/include/asm/arch-mx7/mx7_plugin.S
+++ b/arch/arm/include/asm/arch-mx7/mx7_plugin.S
@@ -6,7 +6,7 @@
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S
index bcc804b..5089b1d 100644
--- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S
+++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S
@@ -6,7 +6,7 @@
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
-#define ROM_VERSION_OFFSET 0x80
+#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 316c67c..ed2a612 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -126,17 +126,17 @@
/* GLB_RST_CON */
PMU_GLB_SRST_CTRL_SHIFT = 2,
PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
- PMU_RST_BY_FST_GLB_SRST = 0,
- PMU_RST_BY_SND_GLB_SRST = 1,
+ PMU_RST_BY_FST_GLB_SRST = 0,
+ PMU_RST_BY_SND_GLB_SRST = 1,
PMU_RST_DISABLE = 2,
WDT_GLB_SRST_CTRL_SHIFT = 1,
WDT_GLB_SRST_CTRL_MASK = BIT(1),
- WDT_TRIGGER_SND_GLB_SRST = 0,
- WDT_TRIGGER_FST_GLB_SRST = 1,
- TSADC_GLB_SRST_CTRL_SHIFT = 0,
- TSADC_GLB_SRST_CTRL_MASK = BIT(0),
- TSADC_TRIGGER_SND_GLB_SRST = 0,
- TSADC_TRIGGER_FST_GLB_SRST = 1,
+ WDT_TRIGGER_SND_GLB_SRST = 0,
+ WDT_TRIGGER_FST_GLB_SRST = 1,
+ TSADC_GLB_SRST_CTRL_SHIFT = 0,
+ TSADC_GLB_SRST_CTRL_MASK = BIT(0),
+ TSADC_TRIGGER_SND_GLB_SRST = 0,
+ TSADC_TRIGGER_FST_GLB_SRST = 1,
};
#endif
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 8ba03e5..94ab059 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -163,13 +163,13 @@
VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+ VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
- VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
- VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index e1eefc2..ec0171e 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -154,7 +154,7 @@
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
#else
- b \master_label
+ b \master_label
#endif
.endm
diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index 28842c3..ffaac68 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -12,9 +12,9 @@
#include <linux/mtd/rawnand.h>
#include <asm/arch/hardware.h>
-#define NAND_READ_START 0x00
-#define NAND_READ_END 0x30
-#define NAND_STATUS 0x70
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
#define MASK_CLE 0x10
#define MASK_ALE 0x08
diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S
index f224587..c6ea3e3 100644
--- a/arch/arm/lib/ccn504.S
+++ b/arch/arm/lib/ccn504.S
@@ -12,7 +12,7 @@
/*************************************************************************
*
* void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
- * CCI_MN_DVM_DOMAIN_CTL_SET);
+ * CCI_MN_DVM_DOMAIN_CTL_SET);
*
* Add fully-coherent masters to DVM domain
*
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 3ef1ce1..a83e337 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -34,12 +34,12 @@
* This is meant to be used by do_div() from include/asm/div64.h only.
*
* Input parameters:
- * xh-xl = dividend (clobbered)
- * r4 = divisor (preserved)
+ * xh-xl = dividend (clobbered)
+ * r4 = divisor (preserved)
*
* Output values:
- * yh-yl = result
- * xh = remainder
+ * yh-yl = result
+ * xh = remainder
*
* Clobbered regs: xl, ip
*/
@@ -85,7 +85,7 @@
#endif
@ The division loop for needed upper bit positions.
- @ Break out early if dividend reaches 0.
+ @ Break out early if dividend reaches 0.
2: cmp xh, yl
orrcs yh, yh, ip
subscs xh, xh, yl
diff --git a/arch/arm/mach-at91/include/mach/at91_mc.h b/arch/arm/mach-at91/include/mach/at91_mc.h
index 18b0e16..7cf6cdf 100644
--- a/arch/arm/mach-at91/include/mach/at91_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91_mc.h
@@ -16,7 +16,7 @@
#ifndef __ASSEMBLY__
typedef struct at91_ebi {
- u32 csa; /* 0x00 Chip Select Assignment Register */
+ u32 csa; /* 0x00 Chip Select Assignment Register */
u32 cfgr; /* 0x04 Configuration Register */
u32 reserved[2];
} at91_ebi_t;
@@ -28,20 +28,20 @@
#define AT91_EBI_CSA_CS4A 0x0010
typedef struct at91_sdramc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
- u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
- u32 cr; /* 0x08 SDRAMC Configuration Register */
- u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
- u32 lpr; /* 0x10 SDRAMC Low Power Register */
- u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
- u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
- u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
- u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
+ u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
+ u32 cr; /* 0x08 SDRAMC Configuration Register */
+ u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
+ u32 lpr; /* 0x10 SDRAMC Low Power Register */
+ u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
+ u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
+ u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
+ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
u32 reserved[3];
} at91_sdramc_t;
typedef struct at91_smc {
- u32 csr[8]; /* 0x00 SDRAMC Mode Register */
+ u32 csr[8]; /* 0x00 SDRAMC Mode Register */
} at91_smc_t;
#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
@@ -60,7 +60,7 @@
#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
typedef struct at91_bfc {
- u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 mr; /* 0x00 SDRAMC Mode Register */
} at91_bfc_t;
typedef struct at91_mc {
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index ec4658a..f91cec9 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -24,6 +24,6 @@
#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
#define AT91_ST_WDMR_RSTEN 0x00010000
-#define AT91_ST_WDMR_EXTEN 0x00020000
+#define AT91_ST_WDMR_EXTEN 0x00020000
#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx-usb.h b/arch/arm/mach-davinci/include/mach/da8xx-usb.h
index 215706e..99d403c 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx-usb.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx-usb.h
@@ -29,22 +29,22 @@
struct da8xx_usb_regs {
dv_reg revision;
dv_reg control;
- dv_reg status;
- dv_reg emulation;
- dv_reg mode;
- dv_reg autoreq;
- dv_reg srpfixtime;
- dv_reg teardown;
- dv_reg intsrc;
- dv_reg intsrc_set;
- dv_reg intsrc_clr;
- dv_reg intmsk;
- dv_reg intmsk_set;
- dv_reg intmsk_clr;
- dv_reg intsrcmsk;
- dv_reg eoi;
- dv_reg intvector;
- dv_reg grndis_size[4];
+ dv_reg status;
+ dv_reg emulation;
+ dv_reg mode;
+ dv_reg autoreq;
+ dv_reg srpfixtime;
+ dv_reg teardown;
+ dv_reg intsrc;
+ dv_reg intsrc_set;
+ dv_reg intsrc_clr;
+ dv_reg intmsk;
+ dv_reg intmsk_set;
+ dv_reg intmsk_clr;
+ dv_reg intsrcmsk;
+ dv_reg eoi;
+ dv_reg intvector;
+ dv_reg grndis_size[4];
};
#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
@@ -68,13 +68,13 @@
#define CFGCHIP2_OTGMODE (3 << 13)
#define CFGCHIP2_NO_OVERRIDE (0 << 13)
#define CFGCHIP2_FORCE_HOST (1 << 13)
-#define CFGCHIP2_FORCE_DEVICE (2 << 13)
+#define CFGCHIP2_FORCE_DEVICE (2 << 13)
#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
#define CFGCHIP2_PHYPWRDN (1 << 10)
#define CFGCHIP2_OTGPWRDN (1 << 9)
-#define CFGCHIP2_DATPOL (1 << 8)
+#define CFGCHIP2_DATPOL (1 << 8)
#define CFGCHIP2_USB1SUSPENDM (1 << 7)
#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h
index a40de0c..1133a23 100644
--- a/arch/arm/mach-davinci/include/mach/davinci_misc.h
+++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h
@@ -23,7 +23,7 @@
/* pin table definition */
struct pinmux_resource {
const struct pinmux_config *pins;
- const int n_pins;
+ const int n_pins;
};
#define PINMUX_ITEM(item) { \
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0ef2695..63e28c6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -34,7 +34,7 @@
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7))
-obj-y += cpu.o
+obj-y += cpu.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
@@ -43,7 +43,7 @@
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
-obj-y += cache.o init.o
+obj-y += cache.o init.o
obj-$(CONFIG_FEC_MXC) += mac.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
ifneq ($(CONFIG_SPL_BUILD),y)
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 0c5dc6a..98a8f05 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -148,8 +148,8 @@
#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
-#define KS2_UART0_BASE 0x02530c00
-#define KS2_UART1_BASE 0x02531000
+#define KS2_UART0_BASE 0x02530c00
+#define KS2_UART1_BASE 0x02531000
/* Boot Config */
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
@@ -210,7 +210,7 @@
#endif
/* AEMIF */
-#define KS2_AEMIF_CNTRL_BASE 0x21000a00
+#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* Flag from ks2_debug options to check if DSPs need to stay ON */
diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c
index 73ab5fb..1d8eab2 100644
--- a/arch/arm/mach-omap2/clocks-common.c
+++ b/arch/arm/mach-omap2/clocks-common.c
@@ -552,7 +552,7 @@
if (pv->value[opp]) {
/* Handle non-empty members only */
pv->value[opp] = optimize_vcore_voltage(pv, opp);
- px = (struct volts *)vcores;
+ px = (struct volts *)vcores;
j = 0;
while (px < pv) {
/*
diff --git a/arch/arm/mach-omap2/omap5/prcm-regs.c b/arch/arm/mach-omap2/omap5/prcm-regs.c
index b5baebc..28c4f4f 100644
--- a/arch/arm/mach-omap2/omap5/prcm-regs.c
+++ b/arch/arm/mach-omap2/omap5/prcm-regs.c
@@ -300,7 +300,7 @@
.control_std_fuse_die_id_1 = 0x4A002208,
.control_std_fuse_die_id_2 = 0x4A00220C,
.control_std_fuse_die_id_3 = 0x4A002210,
- .control_phy_power_usb = 0x4A002370,
+ .control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c
index 0adf3dc..d7ea2e3 100644
--- a/arch/arm/mach-orion5x/timer.c
+++ b/arch/arm/mach-orion5x/timer.c
@@ -69,7 +69,7 @@
#define TVR_ARM_TIMER_OFFS 0
#define TVR_ARM_TIMER_MASK 0xffffffff
#define TVR_ARM_TIMER_MAX 0xffffffff
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff
static inline ulong read_timer(void)
{
diff --git a/arch/arm/mach-rmobile/pfc-r8a7790.h b/arch/arm/mach-rmobile/pfc-r8a7790.h
index e911be4..3b36548 100644
--- a/arch/arm/mach-rmobile/pfc-r8a7790.h
+++ b/arch/arm/mach-rmobile/pfc-r8a7790.h
@@ -82,7 +82,7 @@
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
#define CPU_32_PORT0_16(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), \
+ PORT_10(fn, pfx, sfx), \
PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
index 3bddc10..5910f20 100644
--- a/arch/arm/mach-rockchip/rk3368/Makefile
+++ b/arch/arm/mach-rockchip/rk3368/Makefile
@@ -3,4 +3,4 @@
# Copyright (c) 2016 Andreas Färber
obj-y += clk_rk3368.o
obj-y += rk3368.o
-obj-y += syscon_rk3368.o
+obj-y += syscon_rk3368.o
diff --git a/arch/arm/mach-s5pc1xx/include/mach/sromc.h b/arch/arm/mach-s5pc1xx/include/mach/sromc.h
index 45de4a7..a8eb2a3 100644
--- a/arch/arm/mach-s5pc1xx/include/mach/sromc.h
+++ b/arch/arm/mach-s5pc1xx/include/mach/sromc.h
@@ -4,9 +4,9 @@
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* Note: This file contains the register description for Memory subsystem
- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
*
- * Only SROMC is defined as of now
+ * Only SROMC is defined as of now
*/
#ifndef __ASM_ARCH_SROMC_H_
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 0487082..7ab9517 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -14,8 +14,8 @@
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
@@ -26,9 +26,9 @@
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
@@ -50,9 +50,9 @@
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
diff --git a/arch/arm/mach-sunxi/dram_sun4i.c b/arch/arm/mach-sunxi/dram_sun4i.c
index 76d6982..80a6c4b 100644
--- a/arch/arm/mach-sunxi/dram_sun4i.c
+++ b/arch/arm/mach-sunxi/dram_sun4i.c
@@ -279,7 +279,7 @@
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
- } else {
+ } else {
/* any other frequency that is a multiple of 24 */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index d99a38b..367b740 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
@@ -126,8 +126,8 @@
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
/* Set work mode register */
mctl_set_cr(para);
diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
index 611eaa3..2136ca3 100644
--- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
+++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
@@ -30,7 +30,7 @@
* MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
* write levelling disabled, TDQS disabled, output buffer enabled
* MR2: manual full array self refresh, dynamic ODT off,
- * CAS write latency (CWL): 8
+ * CAS write latency (CWL): 8
*/
static u32 mr_ddr3[7] = {
0x00001c70, 0x00000040, 0x00000018, 0x00000000,