ARM: dts: stm32: DT sync with kernel v5.10-rc1 for MCU's boards
Device tree alignment with kernel v5.10-rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi
index db0b82e..a81e916 100644
--- a/arch/arm/dts/stm32f429.dtsi
+++ b/arch/arm/dts/stm32f429.dtsi
@@ -39,7 +39,7 @@
};
soc {
- romem: nvmem@1fff7800 {
+ romem: efuse@1fff7800 {
compatible = "st,stm32f4-otp";
reg = <0x1fff7800 0x400>;
#address-cells = <1>;
@@ -277,12 +277,10 @@
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
- clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
- interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@@ -362,6 +360,18 @@
status = "disabled";
};
+ i2c3: i2c@40005c00 {
+ compatible = "st,stm32f4-i2c";
+ reg = <0x40005c00 0x400>;
+ interrupts = <72>,
+ <73>;
+ resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
dac: dac@40007400 {
compatible = "st,stm32f4-dac-core";
reg = <0x40007400 0x400>;
@@ -374,14 +384,14 @@
dac1: dac@1 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <2>;
status = "disabled";
};
@@ -546,8 +556,8 @@
status = "disabled";
};
- syscfg: system-config@40013800 {
- compatible = "syscon";
+ syscfg: syscon@40013800 {
+ compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
};
@@ -620,6 +630,9 @@
reg = <0x40015000 0x400>;
interrupts = <85>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
+ dmas = <&dma2 3 2 0x400 0x0>,
+ <&dma2 4 2 0x400 0x0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -634,7 +647,7 @@
};
pwrcfg: power-config@40007000 {
- compatible = "syscon";
+ compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
};
@@ -748,7 +761,6 @@
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
- interrupts = <80>;
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
};