MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index ff02236..74c632a 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -15,10 +15,13 @@
config SYS_DCACHE_SIZE
default 32768
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
config SYS_ICACHE_SIZE
default 65536
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
default 32
endif