diff --git a/Makefile b/Makefile
index dc04179..2d18d27 100644
--- a/Makefile
+++ b/Makefile
@@ -398,6 +398,7 @@
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
+ALL-$(CONFIG_RAMBOOT_PBL) += $(obj)u-boot.pbl
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
 ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.img
 ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index c441bd2..1e5a43f 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <command.h>
 #include <linux/compiler.h>
+#include <asm/fsl_errata.h>
 #include <asm/processor.h>
 #include "fsl_corenet_serdes.h"
 
@@ -245,6 +246,10 @@
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 	puts("Work-around for Erratum A006593 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+	if (has_erratum_a006379())
+		puts("Work-around for Erratum A006379 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 	if (IS_SVR_REV(svr, 1, 0))
 		puts("Work-around for Erratum A003571 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6036333..b31efb7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include <asm/fsl_errata.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
@@ -160,6 +161,12 @@
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 		setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+		if (has_erratum_a006379()) {
+			setbits_be32(&cpc->cpchdbcr0,
+				     CPC_HDBCR0_SPLRU_LEVEL_EN);
+		}
+#endif
 
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
@@ -284,7 +291,7 @@
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 int enable_cluster_l2(void)
 {
 	int i = 0;
@@ -350,7 +357,7 @@
 #endif
 #ifdef CONFIG_L2_CACHE
 	ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
-#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
@@ -533,7 +540,7 @@
 	}
 
 skip_l2:
-#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	if (l2cache->l2csr0 & L2CSR0_L2E)
 		print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
 			   " enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 533d47a..2ccd9c7 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -273,7 +273,7 @@
 		if (has_l2) {
 #ifdef CONFIG_SYS_CACHE_STASHING
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 			/* Only initialize every eighth thread */
 			if (reg && !((*reg) % 8))
 #else
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 4b8d928..d08a8d2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -18,6 +18,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
+#endif
 /* --------------------------------------------------------------- */
 
 void get_sys_info(sys_info_t *sys_info)
@@ -30,6 +34,9 @@
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+#endif
 
 	const u8 core_cplx_PLL[16] = {
 		[ 0] = 0,	/* CC1 PPL / 1 */
@@ -60,8 +67,11 @@
 		[13] = 2,	/* CC4 PPL / 2 */
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
-	uint i, freq_cc_pll[6], rcw_tmp;
-	uint ratio[6];
+	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+	uint rcw_tmp;
+#endif
+	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	uint mem_pll_rat;
 
@@ -81,37 +91,36 @@
 	else
 		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
 
-	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
-	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
-	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
-	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
-	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
-	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
-	for (i = 0; i < 6; i++) {
+	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
 		if (ratio[i] > 4)
-			freq_cc_pll[i] = sysclk * ratio[i];
+			freq_c_pll[i] = sysclk * ratio[i];
 		else
-			freq_cc_pll[i] = sys_info->freq_systembus * ratio[i];
+			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 	}
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 	/*
+	 * As per CHASSIS2 architeture total 12 clusters are posible and
 	 * Each cluster has up to 4 cores, sharing the same PLL selection.
-	 * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
-	 * cluster group A, feeding cores on cluster 1 and cluster 2.
-	 * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
-	 * and cluster 4 if existing.
+	 * The cluster clock assignment is SoC defined.
+	 *
+	 * Total 4 clock groups are possible with 3 PLLs each.
+	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
+	 * clock group B has 3, 4, 6 and so on.
+	 *
+	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
+	 * depends upon the SoC architeture. Same applies to other
+	 * clock groups and clusters.
+	 *
 	 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 		int cluster = fsl_qoriq_core_to_cluster(cpu);
 		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
 				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
-		if (cplx_pll > 3)
-			printf("Unsupported architecture configuration"
-				" in function %s\n", __func__);
-		cplx_pll += (cluster / 2) * 3;
+		cplx_pll += cc_group[cluster] - 1;
 		sys_info->freq_processor[cpu] =
-			 freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 #ifdef CONFIG_PPC_B4860
 #define FM1_CLK_SEL	0xe0000000
@@ -122,27 +131,30 @@
 #define FM1_CLK_SEL	0x1c000000
 #define FM1_CLK_SHIFT	26
 #endif
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
+#endif
 
 #ifdef CONFIG_SYS_DPAA_PME
+#ifndef CONFIG_PME_PLAT_CLK_DIV
 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_pme = freq_cc_pll[0];
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
 		break;
 	case 2:
-		sys_info->freq_pme = freq_cc_pll[0] / 2;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_pme = freq_cc_pll[0] / 3;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_pme = freq_cc_pll[0] / 4;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
 		break;
 	case 6:
-		sys_info->freq_pme = freq_cc_pll[1] / 2;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_pme = freq_cc_pll[1] / 3;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown PME clock select!\n");
@@ -151,6 +163,10 @@
 		break;
 
 	}
+#else
+	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
+
+#endif
 #endif
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
@@ -158,27 +174,28 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_FM_PLAT_CLK_DIV
 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[0] = freq_cc_pll[3];
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
 		break;
 	case 2:
-		sys_info->freq_fman[0] = freq_cc_pll[3] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[0] = freq_cc_pll[3] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[0] = freq_cc_pll[3] / 4;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[0] = sys_info->freq_systembus;
 		break;
 	case 6:
-		sys_info->freq_fman[0] = freq_cc_pll[4] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[0] = freq_cc_pll[4] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan1 clock select!\n");
@@ -187,27 +204,28 @@
 		break;
 	}
 #if (CONFIG_SYS_NUM_FMAN) == 2
+#ifdef CONFIG_SYS_FM2_CLK
 #define FM2_CLK_SEL	0x00000038
 #define FM2_CLK_SHIFT	3
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
 	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[1] = freq_cc_pll[4];
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
 		break;
 	case 2:
-		sys_info->freq_fman[1] = freq_cc_pll[4] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[1] = freq_cc_pll[4] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[1] = freq_cc_pll[4] / 4;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
 		break;
 	case 6:
-		sys_info->freq_fman[1] = freq_cc_pll[3] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[1] = freq_cc_pll[3] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan2 clock select!\n");
@@ -215,8 +233,12 @@
 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 		break;
 	}
+#endif
 #endif	/* CONFIG_SYS_NUM_FMAN == 2 */
-#endif	/* CONFIG_SYS_DPAA_FMAN */
+#else
+	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
+#endif
+#endif
 
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
@@ -226,7 +248,7 @@
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 
 		sys_info->freq_processor[cpu] =
-			 freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 #define PME_CLK_SEL	0x80000000
 #define FM1_CLK_SEL	0x40000000
@@ -246,9 +268,9 @@
 #ifdef CONFIG_SYS_DPAA_PME
 	if (rcw_tmp & PME_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
-			sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4;
+			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
 		else
-			sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2;
+			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_pme = sys_info->freq_systembus / 2;
 	}
@@ -257,18 +279,18 @@
 #ifdef CONFIG_SYS_DPAA_FMAN
 	if (rcw_tmp & FM1_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
-			sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4;
+			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
 		else
-			sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2;
+			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 	}
 #if (CONFIG_SYS_NUM_FMAN) == 2
 	if (rcw_tmp & FM2_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
-			sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4;
+			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
 		else
-			sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2;
+			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index d329aa8..6a81fa7 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -699,7 +699,7 @@
 
 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
 
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 create_ccsr_l2_tlb:
 	/*
 	 * Create a TLB for the MMR location of CCSR
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
index 06706ed..17d8d9f 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
@@ -12,39 +12,39 @@
 typedef struct {
 	/* parameters to constrict */
 
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmax_ps;
-	unsigned int tCKmax_max_ps;
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
+	unsigned int tckmin_x_ps;
+	unsigned int tckmax_ps;
+	unsigned int tckmax_max_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
 
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;	/* maximum = 255 ns + 256 ns + .75 ns
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;	/* maximum = 255 ns + 256 ns + .75 ns
 					   = 511750 ps */
 
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
 
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
 
 	unsigned int ndimms_present;
 	unsigned int lowest_common_SPD_caslat;
 	unsigned int highest_common_derated_caslat;
 	unsigned int additive_latency;
-	unsigned int all_DIMMs_burst_lengths_bitmask;
-	unsigned int all_DIMMs_registered;
-	unsigned int all_DIMMs_unbuffered;
-	unsigned int all_DIMMs_ECC_capable;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	unsigned int all_dimms_ecc_capable;
 
 	unsigned long long total_mem;
 	unsigned long long base_address;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 242eb47..d7333ba 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -353,14 +353,14 @@
 	/* Control Adjust */
 	unsigned int cntl_adj = 0;
 
-	ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
-	ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
-	ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
+	ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
+	ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
+	ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 	ext_caslat = (2 * cas_latency - 1) >> 4;
-	ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
-	ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
-		(popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
+	ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+		(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 
 	ddr->timing_cfg_3 = (0
 		| ((ext_pretoact & 0x1) << 28)
@@ -400,9 +400,9 @@
 	static const u8 wrrec_table[] = {
 		1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 
-	pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
-	acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
-	acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
+	pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
+	acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
+	acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 
 	/*
 	 * Translate CAS Latency to a DDR controller field value:
@@ -433,17 +433,17 @@
 	caslat_ctrl = 2 * cas_latency - 1;
 #endif
 
-	refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
+	refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
+	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 
 	if (wrrec_mclk > 16)
 		printf("Error: WRREC doesn't support more than 16 clocks\n");
 	else
 		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
-	if (popts->OTF_burst_chop_en)
+	if (popts->otf_burst_chop_en)
 		wrrec_mclk += 2;
 
-	acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
+	acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 	/*
 	 * JEDEC has min requirement for tRRD
 	 */
@@ -451,7 +451,7 @@
 	if (acttoact_mclk < 4)
 		acttoact_mclk = 4;
 #endif
-	wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
+	wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 	/*
 	 * JEDEC has some min requirements for tWTR
 	 */
@@ -462,7 +462,7 @@
 	if (wrtord_mclk < 4)
 		wrtord_mclk = 4;
 #endif
-	if (popts->OTF_burst_chop_en)
+	if (popts->otf_burst_chop_en)
 		wrtord_mclk += 2;
 
 	ddr->timing_cfg_1 = (0
@@ -518,7 +518,7 @@
 	wr_lat = compute_cas_write_latency();
 #endif
 
-	rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
+	rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 	/*
 	 * JEDEC has some min requirements for tRTP
 	 */
@@ -531,12 +531,12 @@
 #endif
 	if (additive_latency)
 		rd_to_pre += additive_latency;
-	if (popts->OTF_burst_chop_en)
+	if (popts->otf_burst_chop_en)
 		rd_to_pre += 2; /* according to UM */
 
 	wr_data_delay = popts->write_data_delay;
-	cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
-	four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
+	cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
+	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 
 	ddr->timing_cfg_2 = (0
 		| ((add_lat_mclk & 0xf) << 28)
@@ -555,8 +555,8 @@
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm)
 {
-	if (common_dimm->all_DIMMs_registered
-		&& !common_dimm->all_DIMMs_unbuffered) {
+	if (common_dimm->all_dimms_registered &&
+	    !common_dimm->all_dimms_unbuffered)	{
 		if (popts->rcw_override) {
 			ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 			ddr->ddr_sdram_rcw_2 = popts->rcw_2;
@@ -599,8 +599,8 @@
 	unsigned int dbw;		/* DRAM dta bus width */
 	unsigned int eight_be = 0;	/* 8-beat burst enable, DDR2 is zero */
 	unsigned int ncap = 0;		/* Non-concurrent auto-precharge */
-	unsigned int threeT_en;		/* Enable 3T timing */
-	unsigned int twoT_en;		/* Enable 2T timing */
+	unsigned int threet_en;		/* Enable 3T timing */
+	unsigned int twot_en;		/* Enable 2T timing */
 	unsigned int ba_intlv_ctl;	/* Bank (CS) interleaving control */
 	unsigned int x32_en = 0;	/* x32 enable */
 	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
@@ -610,20 +610,20 @@
 
 	mem_en = 1;
 	sren = popts->self_refresh_in_sleep;
-	if (common_dimm->all_DIMMs_ECC_capable) {
+	if (common_dimm->all_dimms_ecc_capable) {
 		/* Allow setting of ECC only if all DIMMs are ECC. */
-		ecc_en = popts->ECC_mode;
+		ecc_en = popts->ecc_mode;
 	} else {
 		ecc_en = 0;
 	}
 
-	if (common_dimm->all_DIMMs_registered
-		&& !common_dimm->all_DIMMs_unbuffered) {
+	if (common_dimm->all_dimms_registered &&
+	    !common_dimm->all_dimms_unbuffered)	{
 		rd_en = 1;
-		twoT_en = 0;
+		twot_en = 0;
 	} else {
 		rd_en = 0;
-		twoT_en = popts->twoT_en;
+		twot_en = popts->twot_en;
 	}
 
 	sdram_type = CONFIG_FSL_SDRAM_TYPE;
@@ -643,7 +643,7 @@
 			eight_be = 1;
 	}
 
-	threeT_en = popts->threeT_en;
+	threet_en = popts->threet_en;
 	ba_intlv_ctl = popts->ba_intlv_ctl;
 	hse = popts->half_strength_driver_enable;
 
@@ -657,8 +657,8 @@
 			| ((dbw & 0x3) << 19)
 			| ((eight_be & 0x1) << 18)
 			| ((ncap & 0x1) << 17)
-			| ((threeT_en & 0x1) << 16)
-			| ((twoT_en & 0x1) << 15)
+			| ((threet_en & 0x1) << 16)
+			| ((twot_en & 0x1) << 15)
 			| ((ba_intlv_ctl & 0x7F) << 8)
 			| ((x32_en & 0x1) << 5)
 			| ((pchb8 & 0x1) << 4)
@@ -691,7 +691,7 @@
 	int i;
 
 	dll_rst_dis = 1;	/* Make this configurable */
-	dqs_cfg = popts->DQS_config;
+	dqs_cfg = popts->dqs_config;
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (popts->cs_local_opts[i].odt_rd_cfg
 			|| popts->cs_local_opts[i].odt_wr_cfg) {
@@ -710,7 +710,7 @@
 	 *      << DDR_SDRAM_INTERVAL[REFINT]
 	 */
 #if defined(CONFIG_FSL_DDR3)
-	obc_cfg = popts->OTF_burst_chop_en;
+	obc_cfg = popts->otf_burst_chop_en;
 #else
 	obc_cfg = 0;
 #endif
@@ -730,7 +730,7 @@
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/* Use the DDR controller to auto initialize memory. */
-	d_init = popts->ECC_init_using_memctl;
+	d_init = popts->ecc_init_using_memctl;
 	ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 #else
@@ -939,7 +939,7 @@
 	 */
 	dll_on = 1;
 
-	wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
+	wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
 	if (wr_mclk <= 16) {
 		wr = wr_table[wr_mclk - 5];
 	} else {
@@ -1101,7 +1101,7 @@
 #if defined(CONFIG_FSL_DDR2)
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
 #endif
-	dqs_en = !popts->DQS_config;
+	dqs_en = !popts->dqs_config;
 	rtt = fsl_ddr_get_rtt();
 
 	al = additive_latency;
@@ -1130,7 +1130,7 @@
 #if defined(CONFIG_FSL_DDR1)
 	wr = 0;       /* Historical */
 #elif defined(CONFIG_FSL_DDR2)
-	wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
+	wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
 #endif
 	dll_res = 0;
 	mode = 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index c173a5a..e3b414e 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -72,7 +72,7 @@
 				const dimm_params_t *dimm_params,
 				common_timing_params_t *outpdimm,
 				unsigned int number_of_dimms);
-unsigned int populate_memctl_options(int all_DIMMs_registered,
+unsigned int populate_memctl_options(int all_dimms_registered,
 				memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
index 376be2f..f137fce 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
@@ -287,57 +287,57 @@
 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
 	 * nanoseconds and represented as BCD.
 	 */
-	pdimm->tCKmin_X_ps
+	pdimm->tckmin_x_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
-	pdimm->tCKmin_X_minus_1_ps
+	pdimm->tckmin_x_minus_1_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
-	pdimm->tCKmin_X_minus_2_ps
+	pdimm->tckmin_x_minus_2_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
 
-	pdimm->tCKmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
+	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
 
 	/*
 	 * Compute CAS latencies defined by SPD
-	 * The SPD caslat_X should have at least 1 and at most 3 bits set.
+	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
 	 *
 	 * If cas_lat after masking is 0, the __ilog2 function returns
 	 * 255 into the variable.   This behavior is abused once.
 	 */
-	pdimm->caslat_X  = __ilog2(spd->cas_lat);
-	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X));
-	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X)
-					  & ~(1 << pdimm->caslat_X_minus_1));
+	pdimm->caslat_x  = __ilog2(spd->cas_lat);
+	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x));
+	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x)
+					  & ~(1 << pdimm->caslat_x_minus_1));
 
 	/* Compute CAS latencies below that defined by SPD */
 	pdimm->caslat_lowest_derated
 		= compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
 
 	/* Compute timing parameters */
-	pdimm->tRCD_ps = spd->trcd * 250;
-	pdimm->tRP_ps = spd->trp * 250;
-	pdimm->tRAS_ps = spd->tras * 1000;
+	pdimm->trcd_ps = spd->trcd * 250;
+	pdimm->trp_ps = spd->trp * 250;
+	pdimm->tras_ps = spd->tras * 1000;
 
-	pdimm->tWR_ps = mclk_to_picos(3);
-	pdimm->tWTR_ps = mclk_to_picos(1);
-	pdimm->tRFC_ps = compute_trfc_ps_from_spd(0, spd->trfc);
+	pdimm->twr_ps = mclk_to_picos(3);
+	pdimm->twtr_ps = mclk_to_picos(1);
+	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
 
-	pdimm->tRRD_ps = spd->trrd * 250;
-	pdimm->tRC_ps = compute_trc_ps_from_spd(0, spd->trc);
+	pdimm->trrd_ps = spd->trrd * 250;
+	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
 
 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
 
-	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
-	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
-	pdimm->tDS_ps
+	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
+	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
+	pdimm->tds_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
-	pdimm->tDH_ps
+	pdimm->tdh_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
 
-	pdimm->tRTP_ps = mclk_to_picos(2);	/* By the book. */
-	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
-	pdimm->tQHS_ps = spd->tqhs * 10;
+	pdimm->trtp_ps = mclk_to_picos(2);	/* By the book. */
+	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
+	pdimm->tqhs_ps = spd->tqhs * 10;
 
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
index f637f3d..e4d02e8 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
@@ -286,57 +286,57 @@
 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
 	 * nanoseconds and represented as BCD.
 	 */
-	pdimm->tCKmin_X_ps
+	pdimm->tckmin_x_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
-	pdimm->tCKmin_X_minus_1_ps
+	pdimm->tckmin_x_minus_1_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
-	pdimm->tCKmin_X_minus_2_ps
+	pdimm->tckmin_x_minus_2_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
 
-	pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
+	pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
 
 	/*
 	 * Compute CAS latencies defined by SPD
-	 * The SPD caslat_X should have at least 1 and at most 3 bits set.
+	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
 	 *
 	 * If cas_lat after masking is 0, the __ilog2 function returns
 	 * 255 into the variable.   This behavior is abused once.
 	 */
-	pdimm->caslat_X  = __ilog2(spd->cas_lat);
-	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X));
-	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X)
-					  & ~(1 << pdimm->caslat_X_minus_1));
+	pdimm->caslat_x  = __ilog2(spd->cas_lat);
+	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x));
+	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x)
+					  & ~(1 << pdimm->caslat_x_minus_1));
 
 	/* Compute CAS latencies below that defined by SPD */
 	pdimm->caslat_lowest_derated
 		= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
 
 	/* Compute timing parameters */
-	pdimm->tRCD_ps = spd->trcd * 250;
-	pdimm->tRP_ps = spd->trp * 250;
-	pdimm->tRAS_ps = spd->tras * 1000;
+	pdimm->trcd_ps = spd->trcd * 250;
+	pdimm->trp_ps = spd->trp * 250;
+	pdimm->tras_ps = spd->tras * 1000;
 
-	pdimm->tWR_ps = spd->twr * 250;
-	pdimm->tWTR_ps = spd->twtr * 250;
-	pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
+	pdimm->twr_ps = spd->twr * 250;
+	pdimm->twtr_ps = spd->twtr * 250;
+	pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
 
-	pdimm->tRRD_ps = spd->trrd * 250;
-	pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
+	pdimm->trrd_ps = spd->trrd * 250;
+	pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
 
 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
 
-	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
-	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
-	pdimm->tDS_ps
+	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
+	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
+	pdimm->tds_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
-	pdimm->tDH_ps
+	pdimm->tdh_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
 
-	pdimm->tRTP_ps = spd->trtp * 250;
-	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
-	pdimm->tQHS_ps = spd->tqhs * 10;
+	pdimm->trtp_ps = spd->trtp * 250;
+	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
+	pdimm->tqhs_ps = spd->tqhs * 10;
 
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index b67158c..d82eb67 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -210,12 +210,12 @@
 	 * sdram minimum cycle time
 	 * we assume the MTB is 0.125ns
 	 * eg:
-	 * tCK_min=15 MTB (1.875ns) ->DDR3-1066
+	 * tck_min=15 MTB (1.875ns) ->DDR3-1066
 	 *        =12 MTB (1.5ns) ->DDR3-1333
 	 *        =10 MTB (1.25ns) ->DDR3-1600
 	 */
-	pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps +
-		(spd->fine_tCK_min * ftb_10th_ps) / 10;
+	pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
+		(spd->fine_tck_min * ftb_10th_ps) / 10;
 
 	/*
 	 * CAS latency supported
@@ -223,55 +223,55 @@
 	 * bit5 - CL5
 	 * bit18 - CL18
 	 */
-	pdimm->caslat_X  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
+	pdimm->caslat_x  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
 
 	/*
 	 * min CAS latency time
-	 * eg: tAA_min =
+	 * eg: taa_min =
 	 * DDR3-800D	100 MTB (12.5ns)
 	 * DDR3-1066F	105 MTB (13.125ns)
 	 * DDR3-1333H	108 MTB (13.5ns)
 	 * DDR3-1600H	90 MTB (11.25ns)
 	 */
-	pdimm->tAA_ps = spd->tAA_min * mtb_ps +
-		(spd->fine_tAA_min * ftb_10th_ps) / 10;
+	pdimm->taa_ps = spd->taa_min * mtb_ps +
+		(spd->fine_taa_min * ftb_10th_ps) / 10;
 
 	/*
 	 * min write recovery time
 	 * eg:
-	 * tWR_min = 120 MTB (15ns) -> all speed grades.
+	 * twr_min = 120 MTB (15ns) -> all speed grades.
 	 */
-	pdimm->tWR_ps = spd->tWR_min * mtb_ps;
+	pdimm->twr_ps = spd->twr_min * mtb_ps;
 
 	/*
 	 * min RAS to CAS delay time
-	 * eg: tRCD_min =
+	 * eg: trcd_min =
 	 * DDR3-800	100 MTB (12.5ns)
 	 * DDR3-1066F	105 MTB (13.125ns)
 	 * DDR3-1333H	108 MTB (13.5ns)
 	 * DDR3-1600H	90 MTB (11.25)
 	 */
-	pdimm->tRCD_ps = spd->tRCD_min * mtb_ps +
-		(spd->fine_tRCD_min * ftb_10th_ps) / 10;
+	pdimm->trcd_ps = spd->trcd_min * mtb_ps +
+		(spd->fine_trcd_min * ftb_10th_ps) / 10;
 
 	/*
 	 * min row active to row active delay time
-	 * eg: tRRD_min =
+	 * eg: trrd_min =
 	 * DDR3-800(1KB page)	80 MTB (10ns)
 	 * DDR3-1333(1KB page)	48 MTB (6ns)
 	 */
-	pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
+	pdimm->trrd_ps = spd->trrd_min * mtb_ps;
 
 	/*
 	 * min row precharge delay time
-	 * eg: tRP_min =
+	 * eg: trp_min =
 	 * DDR3-800D	100 MTB (12.5ns)
 	 * DDR3-1066F	105 MTB (13.125ns)
 	 * DDR3-1333H	108 MTB (13.5ns)
 	 * DDR3-1600H	90 MTB (11.25ns)
 	 */
-	pdimm->tRP_ps = spd->tRP_min * mtb_ps +
-		(spd->fine_tRP_min * ftb_10th_ps) / 10;
+	pdimm->trp_ps = spd->trp_min * mtb_ps +
+		(spd->fine_trp_min * ftb_10th_ps) / 10;
 
 	/* min active to precharge delay time
 	 * eg: tRAS_min =
@@ -280,7 +280,7 @@
 	 * DDR3-1333H	288 MTB (36ns)
 	 * DDR3-1600H	280 MTB (35ns)
 	 */
-	pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
+	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
 			* mtb_ps;
 	/*
 	 * min active to actice/refresh delay time
@@ -290,8 +290,8 @@
 	 * DDR3-1333H	396 MTB (49.5ns)
 	 * DDR3-1600H	370 MTB (46.25ns)
 	 */
-	pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
-			* mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10;
+	pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
+			* mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
 	/*
 	 * min refresh recovery delay time
 	 * eg: tRFC_min =
@@ -299,21 +299,21 @@
 	 * 1Gb		880 MTB (110ns)
 	 * 2Gb		1280 MTB (160ns)
 	 */
-	pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
+	pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
 			* mtb_ps;
 	/*
 	 * min internal write to read command delay time
-	 * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
+	 * eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
 	 * tWRT is at least 4 mclk independent of operating freq.
 	 */
-	pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
+	pdimm->twtr_ps = spd->twtr_min * mtb_ps;
 
 	/*
 	 * min internal read to precharge command delay time
-	 * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
+	 * eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
 	 * tRTP is at least 4 mclk independent of operating freq.
 	 */
-	pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
+	pdimm->trtp_ps = spd->trtp_min * mtb_ps;
 
 	/*
 	 * Average periodic refresh interval
@@ -324,13 +324,13 @@
 
 	/*
 	 * min four active window delay time
-	 * eg: tFAW_min =
+	 * eg: tfaw_min =
 	 * DDR3-800(1KB page)	320 MTB (40ns)
 	 * DDR3-1066(1KB page)	300 MTB (37.5ns)
 	 * DDR3-1333(1KB page)	240 MTB (30ns)
 	 * DDR3-1600(1KB page)	240 MTB (30ns)
 	 */
-	pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)
+	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
 			* mtb_ps;
 
 	return 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index 260fce5..3b66112 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -150,33 +150,33 @@
 	common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 
 	static const struct options_string options[] = {
-		COMMON_TIMING(tCKmin_X_ps),
-		COMMON_TIMING(tCKmax_ps),
-		COMMON_TIMING(tCKmax_max_ps),
-		COMMON_TIMING(tRCD_ps),
-		COMMON_TIMING(tRP_ps),
-		COMMON_TIMING(tRAS_ps),
-		COMMON_TIMING(tWR_ps),
-		COMMON_TIMING(tWTR_ps),
-		COMMON_TIMING(tRFC_ps),
-		COMMON_TIMING(tRRD_ps),
-		COMMON_TIMING(tRC_ps),
+		COMMON_TIMING(tckmin_x_ps),
+		COMMON_TIMING(tckmax_ps),
+		COMMON_TIMING(tckmax_max_ps),
+		COMMON_TIMING(trcd_ps),
+		COMMON_TIMING(trp_ps),
+		COMMON_TIMING(tras_ps),
+		COMMON_TIMING(twr_ps),
+		COMMON_TIMING(twtr_ps),
+		COMMON_TIMING(trfc_ps),
+		COMMON_TIMING(trrd_ps),
+		COMMON_TIMING(trc_ps),
 		COMMON_TIMING(refresh_rate_ps),
-		COMMON_TIMING(tIS_ps),
-		COMMON_TIMING(tIH_ps),
-		COMMON_TIMING(tDS_ps),
-		COMMON_TIMING(tDH_ps),
-		COMMON_TIMING(tRTP_ps),
-		COMMON_TIMING(tDQSQ_max_ps),
-		COMMON_TIMING(tQHS_ps),
+		COMMON_TIMING(tis_ps),
+		COMMON_TIMING(tih_ps),
+		COMMON_TIMING(tds_ps),
+		COMMON_TIMING(tdh_ps),
+		COMMON_TIMING(trtp_ps),
+		COMMON_TIMING(tdqsq_max_ps),
+		COMMON_TIMING(tqhs_ps),
 		COMMON_TIMING(ndimms_present),
 		COMMON_TIMING(lowest_common_SPD_caslat),
 		COMMON_TIMING(highest_common_derated_caslat),
 		COMMON_TIMING(additive_latency),
-		COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
-		COMMON_TIMING(all_DIMMs_registered),
-		COMMON_TIMING(all_DIMMs_unbuffered),
-		COMMON_TIMING(all_DIMMs_ECC_capable),
+		COMMON_TIMING(all_dimms_burst_lengths_bitmask),
+		COMMON_TIMING(all_dimms_registered),
+		COMMON_TIMING(all_dimms_unbuffered),
+		COMMON_TIMING(all_dimms_ecc_capable),
 		COMMON_TIMING(total_mem),
 		COMMON_TIMING(base_address),
 	};
@@ -214,34 +214,34 @@
 		DIMM_PARM(burst_lengths_bitmask),
 		DIMM_PARM(row_density),
 
-		DIMM_PARM(tCKmin_X_ps),
-		DIMM_PARM(tCKmin_X_minus_1_ps),
-		DIMM_PARM(tCKmin_X_minus_2_ps),
-		DIMM_PARM(tCKmax_ps),
+		DIMM_PARM(tckmin_x_ps),
+		DIMM_PARM(tckmin_x_minus_1_ps),
+		DIMM_PARM(tckmin_x_minus_2_ps),
+		DIMM_PARM(tckmax_ps),
 
-		DIMM_PARM(caslat_X),
-		DIMM_PARM(caslat_X_minus_1),
-		DIMM_PARM(caslat_X_minus_2),
+		DIMM_PARM(caslat_x),
+		DIMM_PARM(caslat_x_minus_1),
+		DIMM_PARM(caslat_x_minus_2),
 
 		DIMM_PARM(caslat_lowest_derated),
 
-		DIMM_PARM(tRCD_ps),
-		DIMM_PARM(tRP_ps),
-		DIMM_PARM(tRAS_ps),
-		DIMM_PARM(tWR_ps),
-		DIMM_PARM(tWTR_ps),
-		DIMM_PARM(tRFC_ps),
-		DIMM_PARM(tRRD_ps),
-		DIMM_PARM(tRC_ps),
+		DIMM_PARM(trcd_ps),
+		DIMM_PARM(trp_ps),
+		DIMM_PARM(tras_ps),
+		DIMM_PARM(twr_ps),
+		DIMM_PARM(twtr_ps),
+		DIMM_PARM(trfc_ps),
+		DIMM_PARM(trrd_ps),
+		DIMM_PARM(trc_ps),
 		DIMM_PARM(refresh_rate_ps),
 
-		DIMM_PARM(tIS_ps),
-		DIMM_PARM(tIH_ps),
-		DIMM_PARM(tDS_ps),
-		DIMM_PARM(tDH_ps),
-		DIMM_PARM(tRTP_ps),
-		DIMM_PARM(tDQSQ_max_ps),
-		DIMM_PARM(tQHS_ps),
+		DIMM_PARM(tis_ps),
+		DIMM_PARM(tih_ps),
+		DIMM_PARM(tds_ps),
+		DIMM_PARM(tdh_ps),
+		DIMM_PARM(trtp_ps),
+		DIMM_PARM(tdqsq_max_ps),
+		DIMM_PARM(tqhs_ps),
 
 		DIMM_PARM(rank_density),
 		DIMM_PARM(capacity),
@@ -271,34 +271,34 @@
 		DIMM_PARM(edc_config),
 		DIMM_PARM(n_banks_per_sdram_device),
 
-		DIMM_PARM(tCKmin_X_ps),
-		DIMM_PARM(tCKmin_X_minus_1_ps),
-		DIMM_PARM(tCKmin_X_minus_2_ps),
-		DIMM_PARM(tCKmax_ps),
+		DIMM_PARM(tckmin_x_ps),
+		DIMM_PARM(tckmin_x_minus_1_ps),
+		DIMM_PARM(tckmin_x_minus_2_ps),
+		DIMM_PARM(tckmax_ps),
 
-		DIMM_PARM(caslat_X),
-		DIMM_PARM(tAA_ps),
-		DIMM_PARM(caslat_X_minus_1),
-		DIMM_PARM(caslat_X_minus_2),
+		DIMM_PARM(caslat_x),
+		DIMM_PARM(taa_ps),
+		DIMM_PARM(caslat_x_minus_1),
+		DIMM_PARM(caslat_x_minus_2),
 		DIMM_PARM(caslat_lowest_derated),
 
-		DIMM_PARM(tRCD_ps),
-		DIMM_PARM(tRP_ps),
-		DIMM_PARM(tRAS_ps),
-		DIMM_PARM(tWR_ps),
-		DIMM_PARM(tWTR_ps),
-		DIMM_PARM(tRFC_ps),
-		DIMM_PARM(tRRD_ps),
-		DIMM_PARM(tRC_ps),
+		DIMM_PARM(trcd_ps),
+		DIMM_PARM(trp_ps),
+		DIMM_PARM(tras_ps),
+		DIMM_PARM(twr_ps),
+		DIMM_PARM(twtr_ps),
+		DIMM_PARM(trfc_ps),
+		DIMM_PARM(trrd_ps),
+		DIMM_PARM(trc_ps),
 		DIMM_PARM(refresh_rate_ps),
 
-		DIMM_PARM(tIS_ps),
-		DIMM_PARM(tIH_ps),
-		DIMM_PARM(tDS_ps),
-		DIMM_PARM(tDH_ps),
-		DIMM_PARM(tRTP_ps),
-		DIMM_PARM(tDQSQ_max_ps),
-		DIMM_PARM(tQHS_ps),
+		DIMM_PARM(tis_ps),
+		DIMM_PARM(tih_ps),
+		DIMM_PARM(tds_ps),
+		DIMM_PARM(tdh_ps),
+		DIMM_PARM(trtp_ps),
+		DIMM_PARM(tdqsq_max_ps),
+		DIMM_PARM(tqhs_ps),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
@@ -325,41 +325,41 @@
 		const common_timing_params_t *plcd_dimm_params)
 {
 	static const struct options_string options[] = {
-		COMMON_TIMING(tCKmax_max_ps),
-		COMMON_TIMING(tRCD_ps),
-		COMMON_TIMING(tRP_ps),
-		COMMON_TIMING(tRAS_ps),
-		COMMON_TIMING(tWR_ps),
-		COMMON_TIMING(tWTR_ps),
-		COMMON_TIMING(tRFC_ps),
-		COMMON_TIMING(tRRD_ps),
-		COMMON_TIMING(tRC_ps),
+		COMMON_TIMING(tckmax_max_ps),
+		COMMON_TIMING(trcd_ps),
+		COMMON_TIMING(trp_ps),
+		COMMON_TIMING(tras_ps),
+		COMMON_TIMING(twr_ps),
+		COMMON_TIMING(twtr_ps),
+		COMMON_TIMING(trfc_ps),
+		COMMON_TIMING(trrd_ps),
+		COMMON_TIMING(trc_ps),
 		COMMON_TIMING(refresh_rate_ps),
-		COMMON_TIMING(tIS_ps),
-		COMMON_TIMING(tDS_ps),
-		COMMON_TIMING(tDH_ps),
-		COMMON_TIMING(tRTP_ps),
-		COMMON_TIMING(tDQSQ_max_ps),
-		COMMON_TIMING(tQHS_ps),
+		COMMON_TIMING(tis_ps),
+		COMMON_TIMING(tds_ps),
+		COMMON_TIMING(tdh_ps),
+		COMMON_TIMING(trtp_ps),
+		COMMON_TIMING(tdqsq_max_ps),
+		COMMON_TIMING(tqhs_ps),
 		COMMON_TIMING(lowest_common_SPD_caslat),
 		COMMON_TIMING(highest_common_derated_caslat),
 		COMMON_TIMING(additive_latency),
 		COMMON_TIMING(ndimms_present),
-		COMMON_TIMING(all_DIMMs_registered),
-		COMMON_TIMING(all_DIMMs_unbuffered),
-		COMMON_TIMING(all_DIMMs_ECC_capable),
+		COMMON_TIMING(all_dimms_registered),
+		COMMON_TIMING(all_dimms_unbuffered),
+		COMMON_TIMING(all_dimms_ecc_capable),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
 	/* Clock frequencies */
-	printf("tCKmin_X_ps = %u (%u MHz)\n",
-	       plcd_dimm_params->tCKmin_X_ps,
-	       picos_to_mhz(plcd_dimm_params->tCKmin_X_ps));
-	printf("tCKmax_ps = %u (%u MHz)\n",
-	       plcd_dimm_params->tCKmax_ps,
-	       picos_to_mhz(plcd_dimm_params->tCKmax_ps));
-	printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
-	       plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
+	printf("tckmin_x_ps = %u (%u MHz)\n",
+	       plcd_dimm_params->tckmin_x_ps,
+	       picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
+	printf("tckmax_ps = %u (%u MHz)\n",
+	       plcd_dimm_params->tckmax_ps,
+	       picos_to_mhz(plcd_dimm_params->tckmax_ps));
+	printf("all_dimms_burst_lengths_bitmask = %02X\n",
+	       plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 
 	print_option_table(options, n_opts, plcd_dimm_params);
 
@@ -421,9 +421,9 @@
 		CTRL_OPTIONS(memctl_interleaving),
 		CTRL_OPTIONS(memctl_interleaving_mode),
 		CTRL_OPTIONS(ba_intlv_ctl),
-		CTRL_OPTIONS(ECC_mode),
-		CTRL_OPTIONS(ECC_init_using_memctl),
-		CTRL_OPTIONS(DQS_config),
+		CTRL_OPTIONS(ecc_mode),
+		CTRL_OPTIONS(ecc_init_using_memctl),
+		CTRL_OPTIONS(dqs_config),
 		CTRL_OPTIONS(self_refresh_in_sleep),
 		CTRL_OPTIONS(dynamic_power),
 		CTRL_OPTIONS(data_bus_width),
@@ -442,8 +442,8 @@
 		 * These can probably be changed to 2T_EN and 3T_EN
 		 * (using a leading numerical character) without problem
 		 */
-		CTRL_OPTIONS(twoT_en),
-		CTRL_OPTIONS(threeT_en),
+		CTRL_OPTIONS(twot_en),
+		CTRL_OPTIONS(threet_en),
 		CTRL_OPTIONS(ap_en),
 		CTRL_OPTIONS(x4_en),
 		CTRL_OPTIONS(bstopre),
@@ -455,8 +455,8 @@
 		CTRL_OPTIONS(rcw_2),
 		CTRL_OPTIONS(ddr_cdr1),
 		CTRL_OPTIONS(ddr_cdr2),
-		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
-		CTRL_OPTIONS(tFAW_window_four_activates_ps),
+		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
+		CTRL_OPTIONS(tfaw_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
 		CTRL_OPTIONS(trwt),
 	};
@@ -666,9 +666,9 @@
 		CTRL_OPTIONS(memctl_interleaving),
 		CTRL_OPTIONS(memctl_interleaving_mode),
 		CTRL_OPTIONS_HEX(ba_intlv_ctl),
-		CTRL_OPTIONS(ECC_mode),
-		CTRL_OPTIONS(ECC_init_using_memctl),
-		CTRL_OPTIONS(DQS_config),
+		CTRL_OPTIONS(ecc_mode),
+		CTRL_OPTIONS(ecc_init_using_memctl),
+		CTRL_OPTIONS(dqs_config),
 		CTRL_OPTIONS(self_refresh_in_sleep),
 		CTRL_OPTIONS(dynamic_power),
 		CTRL_OPTIONS(data_bus_width),
@@ -686,8 +686,8 @@
 		 * These can probably be changed to 2T_EN and 3T_EN
 		 * (using a leading numerical character) without problem
 		 */
-		CTRL_OPTIONS(twoT_en),
-		CTRL_OPTIONS(threeT_en),
+		CTRL_OPTIONS(twot_en),
+		CTRL_OPTIONS(threet_en),
 		CTRL_OPTIONS(registered_dimm_en),
 		CTRL_OPTIONS(ap_en),
 		CTRL_OPTIONS(x4_en),
@@ -700,8 +700,8 @@
 		CTRL_OPTIONS(rcw_2),
 		CTRL_OPTIONS_HEX(ddr_cdr1),
 		CTRL_OPTIONS_HEX(ddr_cdr2),
-		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
-		CTRL_OPTIONS(tFAW_window_four_activates_ps),
+		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
+		CTRL_OPTIONS(tfaw_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
 		CTRL_OPTIONS(trwt),
 	};
@@ -958,10 +958,10 @@
 	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 	printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
 	       " spd->pll_relock,  * 46 PLL Relock time *");
-	printf("%-3d    : %02x %s\n", 47, spd->Tcasemax,
-	       " spd->Tcasemax,    * 47 Tcasemax *");
-	printf("%-3d    : %02x %s\n", 48, spd->psiTAdram,
-	       " spd->psiTAdram,   * 48 Thermal Resistance of DRAM Package "
+	printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
+	       " spd->t_casemax,    * 47 t_casemax *");
+	printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
+	       " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
 	       "from Top (Case) to Ambient (Psi T-A DRAM) *");
 	printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
 	       " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
@@ -996,11 +996,11 @@
 	       " spd->dt7,         * 57 DRAM Case Temperature Rise from "
 	       "Ambient due to Bank Interleave Reads with "
 	       "Auto-Precharge (DT7) *");
-	printf("%-3d    : %02x %s\n", 58, spd->psiTApll,
-	       " spd->psiTApll,    * 58 Thermal Resistance of PLL Package form"
+	printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
+	       " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
 	       " Top (Case) to Ambient (Psi T-A PLL) *");
-	printf("%-3d    : %02x %s\n", 59, spd->psiTAreg,
-	       " spd->psiTAreg,    * 59 Thermal Reisitance of Register Package"
+	printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
+	       " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
 	       " from Top (Case) to Ambient (Psi T-A Register) *");
 	printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
 	       " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
@@ -1087,43 +1087,43 @@
 		"mtb_dividend   Medium Timebase (MTB) Dividend");
 	PRINT_NXS(11, spd->mtb_divisor,
 		"mtb_divisor    Medium Timebase (MTB) Divisor");
-	PRINT_NXS(12, spd->tCK_min,
-		"tCK_min        SDRAM Minimum Cycle Time");
+	PRINT_NXS(12, spd->tck_min,
+		  "tck_min        SDRAM Minimum Cycle Time");
 	PRINT_NXS(13, spd->res_13,
 		"res_13         Reserved");
 	PRINT_NXS(14, spd->caslat_lsb,
 		"caslat_lsb     CAS Latencies Supported, LSB");
 	PRINT_NXS(15, spd->caslat_msb,
 		"caslat_msb     CAS Latencies Supported, MSB");
-	PRINT_NXS(16, spd->tAA_min,
-		"tAA_min        Min CAS Latency Time");
-	PRINT_NXS(17, spd->tWR_min,
-		"tWR_min        Min Write REcovery Time");
-	PRINT_NXS(18, spd->tRCD_min,
-		"tRCD_min       Min RAS# to CAS# Delay Time");
-	PRINT_NXS(19, spd->tRRD_min,
-		"tRRD_min       Min Row Active to Row Active Delay Time");
-	PRINT_NXS(20, spd->tRP_min,
-		"tRP_min        Min Row Precharge Delay Time");
-	PRINT_NXS(21, spd->tRAS_tRC_ext,
-		"tRAS_tRC_ext   Upper Nibbles for tRAS and tRC");
-	PRINT_NXS(22, spd->tRAS_min_lsb,
-		"tRAS_min_lsb   Min Active to Precharge Delay Time, LSB");
-	PRINT_NXS(23, spd->tRC_min_lsb,
-		"tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB");
-	PRINT_NXS(24, spd->tRFC_min_lsb,
-		"tRFC_min_lsb   Min Refresh Recovery Delay Time LSB");
-	PRINT_NXS(25, spd->tRFC_min_msb,
-		"tRFC_min_msb   Min Refresh Recovery Delay Time MSB");
-	PRINT_NXS(26, spd->tWTR_min,
-		"tWTR_min       Min Internal Write to Read Command Delay Time");
-	PRINT_NXS(27, spd->tRTP_min,
-		"tRTP_min "
-		"Min Internal Read to Precharge Command Delay Time");
-	PRINT_NXS(28, spd->tFAW_msb,
-		"tFAW_msb       Upper Nibble for tFAW");
-	PRINT_NXS(29, spd->tFAW_min,
-		"tFAW_min       Min Four Activate Window Delay Time");
+	PRINT_NXS(16, spd->taa_min,
+		  "taa_min        Min CAS Latency Time");
+	PRINT_NXS(17, spd->twr_min,
+		  "twr_min        Min Write REcovery Time");
+	PRINT_NXS(18, spd->trcd_min,
+		  "trcd_min       Min RAS# to CAS# Delay Time");
+	PRINT_NXS(19, spd->trrd_min,
+		  "trrd_min       Min Row Active to Row Active Delay Time");
+	PRINT_NXS(20, spd->trp_min,
+		  "trp_min        Min Row Precharge Delay Time");
+	PRINT_NXS(21, spd->tras_trc_ext,
+		  "tras_trc_ext   Upper Nibbles for tRAS and tRC");
+	PRINT_NXS(22, spd->tras_min_lsb,
+		  "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
+	PRINT_NXS(23, spd->trc_min_lsb,
+		  "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
+	PRINT_NXS(24, spd->trfc_min_lsb,
+		  "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
+	PRINT_NXS(25, spd->trfc_min_msb,
+		  "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
+	PRINT_NXS(26, spd->twtr_min,
+		  "twtr_min Min Internal Write to Read Command Delay Time");
+	PRINT_NXS(27, spd->trtp_min,
+		  "trtp_min "
+		  "Min Internal Read to Precharge Command Delay Time");
+	PRINT_NXS(28, spd->tfaw_msb,
+		  "tfaw_msb       Upper Nibble for tFAW");
+	PRINT_NXS(29, spd->tfaw_min,
+		  "tfaw_min       Min Four Activate Window Delay Time");
 	PRINT_NXS(30, spd->opt_features,
 		"opt_features   SDRAM Optional Features");
 	PRINT_NXS(31, spd->therm_ref_opt,
@@ -1132,16 +1132,16 @@
 		"therm_sensor  SDRAM Thermal Sensor");
 	PRINT_NXS(33, spd->device_type,
 		"device_type  SDRAM Device Type");
-	PRINT_NXS(34, spd->fine_tCK_min,
-		"fine_tCK_min  Fine offset for tCKmin");
-	PRINT_NXS(35, spd->fine_tAA_min,
-		"fine_tAA_min  Fine offset for tAAmin");
-	PRINT_NXS(36, spd->fine_tRCD_min,
-		"fine_tRCD_min Fine offset for tRCDmin");
-	PRINT_NXS(37, spd->fine_tRP_min,
-		"fine_tRP_min  Fine offset for tRPmin");
-	PRINT_NXS(38, spd->fine_tRC_min,
-		"fine_tRC_min  Fine offset for tRCmin");
+	PRINT_NXS(34, spd->fine_tck_min,
+		  "fine_tck_min  Fine offset for tCKmin");
+	PRINT_NXS(35, spd->fine_taa_min,
+		  "fine_taa_min  Fine offset for tAAmin");
+	PRINT_NXS(36, spd->fine_trcd_min,
+		  "fine_trcd_min Fine offset for tRCDmin");
+	PRINT_NXS(37, spd->fine_trp_min,
+		  "fine_trp_min  Fine offset for tRPmin");
+	PRINT_NXS(38, spd->fine_trc_min,
+		  "fine_trc_min  Fine offset for tRCmin");
 
 	printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
 
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 56128a7..3affcee 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -18,8 +18,8 @@
 			 unsigned int number_of_dimms)
 {
 	unsigned int i;
-	unsigned int tAAmin_ps = 0;
-	unsigned int tCKmin_X_ps = 0;
+	unsigned int taamin_ps = 0;
+	unsigned int tckmin_x_ps = 0;
 	unsigned int common_caslat;
 	unsigned int caslat_actual;
 	unsigned int retry = 16;
@@ -27,26 +27,26 @@
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
 
 	/* compute the common CAS latency supported between slots */
-	tmp = dimm_params[0].caslat_X;
+	tmp = dimm_params[0].caslat_x;
 	for (i = 1; i < number_of_dimms; i++) {
 		if (dimm_params[i].n_ranks)
-			tmp &= dimm_params[i].caslat_X;
+			tmp &= dimm_params[i].caslat_x;
 	}
 	common_caslat = tmp;
 
 	/* compute the max tAAmin tCKmin between slots */
 	for (i = 0; i < number_of_dimms; i++) {
-		tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
-		tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
+		taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+		tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
 	}
 	/* validate if the memory clk is in the range of dimms */
-	if (mclk_ps < tCKmin_X_ps) {
+	if (mclk_ps < tckmin_x_ps) {
 		printf("DDR clock (MCLK cycle %u ps) is faster than "
 			"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
-			mclk_ps, tCKmin_X_ps);
+			mclk_ps, tckmin_x_ps);
 	}
 	/* determine the acutal cas latency */
-	caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
+	caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
 	/* check if the dimms support the CAS latency */
 	while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
 		caslat_actual++;
@@ -80,25 +80,25 @@
 {
 	unsigned int i, j;
 
-	unsigned int tCKmin_X_ps = 0;
-	unsigned int tCKmax_ps = 0xFFFFFFFF;
-	unsigned int tCKmax_max_ps = 0;
-	unsigned int tRCD_ps = 0;
-	unsigned int tRP_ps = 0;
-	unsigned int tRAS_ps = 0;
-	unsigned int tWR_ps = 0;
-	unsigned int tWTR_ps = 0;
-	unsigned int tRFC_ps = 0;
-	unsigned int tRRD_ps = 0;
-	unsigned int tRC_ps = 0;
+	unsigned int tckmin_x_ps = 0;
+	unsigned int tckmax_ps = 0xFFFFFFFF;
+	unsigned int tckmax_max_ps = 0;
+	unsigned int trcd_ps = 0;
+	unsigned int trp_ps = 0;
+	unsigned int tras_ps = 0;
+	unsigned int twr_ps = 0;
+	unsigned int twtr_ps = 0;
+	unsigned int trfc_ps = 0;
+	unsigned int trrd_ps = 0;
+	unsigned int trc_ps = 0;
 	unsigned int refresh_rate_ps = 0;
-	unsigned int tIS_ps = 0;
-	unsigned int tIH_ps = 0;
-	unsigned int tDS_ps = 0;
-	unsigned int tDH_ps = 0;
-	unsigned int tRTP_ps = 0;
-	unsigned int tDQSQ_max_ps = 0;
-	unsigned int tQHS_ps = 0;
+	unsigned int tis_ps = 0;
+	unsigned int tih_ps = 0;
+	unsigned int tds_ps = 0;
+	unsigned int tdh_ps = 0;
+	unsigned int trtp_ps = 0;
+	unsigned int tdqsq_max_ps = 0;
+	unsigned int tqhs_ps = 0;
 
 	unsigned int temp1, temp2;
 	unsigned int additive_latency = 0;
@@ -141,39 +141,39 @@
 		}
 #endif
 		/*
-		 * Find minimum tCKmax_ps to find fastest slow speed,
+		 * Find minimum tckmax_ps to find fastest slow speed,
 		 * i.e., this is the slowest the whole system can go.
 		 */
-		tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
+		tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
 
 		/* Either find maximum value to determine slowest
 		 * speed, delay, time, period, etc */
-		tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
-		tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
-		tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
-		tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
-		tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
-		tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
-		tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
-		tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
-		tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
-		tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
-		tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
-		tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
-		tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
-		tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
-		tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
-		tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
+		tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
+		tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
+		trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
+		trp_ps = max(trp_ps, dimm_params[i].trp_ps);
+		tras_ps = max(tras_ps, dimm_params[i].tras_ps);
+		twr_ps = max(twr_ps, dimm_params[i].twr_ps);
+		twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
+		trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
+		trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
+		trc_ps = max(trc_ps, dimm_params[i].trc_ps);
+		tis_ps = max(tis_ps, dimm_params[i].tis_ps);
+		tih_ps = max(tih_ps, dimm_params[i].tih_ps);
+		tds_ps = max(tds_ps, dimm_params[i].tds_ps);
+		tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
+		trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
+		tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
 		refresh_rate_ps = max(refresh_rate_ps,
 				      dimm_params[i].refresh_rate_ps);
 
 		/*
-		 * Find maximum tDQSQ_max_ps to find slowest.
+		 * Find maximum tdqsq_max_ps to find slowest.
 		 *
 		 * FIXME: is finding the slowest value the correct
 		 * strategy for this parameter?
 		 */
-		tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
+		tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
 	}
 
 	outpdimm->ndimms_present = number_of_dimms - temp1;
@@ -183,25 +183,25 @@
 		return 0;
 	}
 
-	outpdimm->tCKmin_X_ps = tCKmin_X_ps;
-	outpdimm->tCKmax_ps = tCKmax_ps;
-	outpdimm->tCKmax_max_ps = tCKmax_max_ps;
-	outpdimm->tRCD_ps = tRCD_ps;
-	outpdimm->tRP_ps = tRP_ps;
-	outpdimm->tRAS_ps = tRAS_ps;
-	outpdimm->tWR_ps = tWR_ps;
-	outpdimm->tWTR_ps = tWTR_ps;
-	outpdimm->tRFC_ps = tRFC_ps;
-	outpdimm->tRRD_ps = tRRD_ps;
-	outpdimm->tRC_ps = tRC_ps;
+	outpdimm->tckmin_x_ps = tckmin_x_ps;
+	outpdimm->tckmax_ps = tckmax_ps;
+	outpdimm->tckmax_max_ps = tckmax_max_ps;
+	outpdimm->trcd_ps = trcd_ps;
+	outpdimm->trp_ps = trp_ps;
+	outpdimm->tras_ps = tras_ps;
+	outpdimm->twr_ps = twr_ps;
+	outpdimm->twtr_ps = twtr_ps;
+	outpdimm->trfc_ps = trfc_ps;
+	outpdimm->trrd_ps = trrd_ps;
+	outpdimm->trc_ps = trc_ps;
 	outpdimm->refresh_rate_ps = refresh_rate_ps;
-	outpdimm->tIS_ps = tIS_ps;
-	outpdimm->tIH_ps = tIH_ps;
-	outpdimm->tDS_ps = tDS_ps;
-	outpdimm->tDH_ps = tDH_ps;
-	outpdimm->tRTP_ps = tRTP_ps;
-	outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
-	outpdimm->tQHS_ps = tQHS_ps;
+	outpdimm->tis_ps = tis_ps;
+	outpdimm->tih_ps = tih_ps;
+	outpdimm->tds_ps = tds_ps;
+	outpdimm->tdh_ps = tdh_ps;
+	outpdimm->trtp_ps = trtp_ps;
+	outpdimm->tdqsq_max_ps = tdqsq_max_ps;
+	outpdimm->tqhs_ps = tqhs_ps;
 
 	/* Determine common burst length for all DIMMs. */
 	temp1 = 0xff;
@@ -210,7 +210,7 @@
 			temp1 &= dimm_params[i].burst_lengths_bitmask;
 		}
 	}
-	outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
+	outpdimm->all_dimms_burst_lengths_bitmask = temp1;
 
 	/* Determine if all DIMMs registered buffered. */
 	temp1 = temp2 = 0;
@@ -232,19 +232,19 @@
 		}
 	}
 
-	outpdimm->all_DIMMs_registered = 0;
-	outpdimm->all_DIMMs_unbuffered = 0;
+	outpdimm->all_dimms_registered = 0;
+	outpdimm->all_dimms_unbuffered = 0;
 	if (temp1 && !temp2) {
-		outpdimm->all_DIMMs_registered = 1;
+		outpdimm->all_dimms_registered = 1;
 	} else if (!temp1 && temp2) {
-		outpdimm->all_DIMMs_unbuffered = 1;
+		outpdimm->all_dimms_unbuffered = 1;
 	} else {
 		printf("ERROR:  Mix of registered buffered and unbuffered "
 				"DIMMs detected!\n");
 	}
 
 	temp1 = 0;
-	if (outpdimm->all_DIMMs_registered)
+	if (outpdimm->all_dimms_registered)
 		for (j = 0; j < 16; j++) {
 			outpdimm->rcw[j] = dimm_params[0].rcw[j];
 			for (i = 1; i < number_of_dimms; i++) {
@@ -279,13 +279,13 @@
 	for (i = 0; i < number_of_dimms; i++) {
 		if (dimm_params[i].n_ranks) {
 			temp2 = 0;
-			temp2 |= 1 << dimm_params[i].caslat_X;
-			temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
-			temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
+			temp2 |= 1 << dimm_params[i].caslat_x;
+			temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
+			temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
 			/*
 			 * FIXME: If there was no entry for X-2 (X-1) in
-			 * the SPD, then caslat_X_minus_2
-			 * (caslat_X_minus_1) contains either 255 or
+			 * the SPD, then caslat_x_minus_2
+			 * (caslat_x_minus_1) contains either 255 or
 			 * 0xFFFFFFFF because that's what the glorious
 			 * __ilog2 function returns for an input of 0.
 			 * On 32-bit PowerPC, left shift counts with bit
@@ -313,42 +313,42 @@
 			if (!dimm_params[i].n_ranks) {
 				continue;
 			}
-			if (dimm_params[i].caslat_X == temp2) {
-				if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
+			if (dimm_params[i].caslat_x == temp2) {
+				if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
 					debug("CL = %u ok on DIMM %u at tCK=%u"
 					    " ps with its tCKmin_X_ps of %u\n",
 					       temp2, i, mclk_ps,
-					       dimm_params[i].tCKmin_X_ps);
+					       dimm_params[i].tckmin_x_ps);
 					continue;
 				} else {
 					not_ok++;
 				}
 			}
 
-			if (dimm_params[i].caslat_X_minus_1 == temp2) {
-				unsigned int tCKmin_X_minus_1_ps
-					= dimm_params[i].tCKmin_X_minus_1_ps;
-				if (mclk_ps >= tCKmin_X_minus_1_ps) {
+			if (dimm_params[i].caslat_x_minus_1 == temp2) {
+				unsigned int tckmin_x_minus_1_ps
+					= dimm_params[i].tckmin_x_minus_1_ps;
+				if (mclk_ps >= tckmin_x_minus_1_ps) {
 					debug("CL = %u ok on DIMM %u at "
 						"tCK=%u ps with its "
-						"tCKmin_X_minus_1_ps of %u\n",
+						"tckmin_x_minus_1_ps of %u\n",
 					       temp2, i, mclk_ps,
-					       tCKmin_X_minus_1_ps);
+					       tckmin_x_minus_1_ps);
 					continue;
 				} else {
 					not_ok++;
 				}
 			}
 
-			if (dimm_params[i].caslat_X_minus_2 == temp2) {
-				unsigned int tCKmin_X_minus_2_ps
-					= dimm_params[i].tCKmin_X_minus_2_ps;
-				if (mclk_ps >= tCKmin_X_minus_2_ps) {
+			if (dimm_params[i].caslat_x_minus_2 == temp2) {
+				unsigned int tckmin_x_minus_2_ps
+					= dimm_params[i].tckmin_x_minus_2_ps;
+				if (mclk_ps >= tckmin_x_minus_2_ps) {
 					debug("CL = %u ok on DIMM %u at "
 						"tCK=%u ps with its "
-						"tCKmin_X_minus_2_ps of %u\n",
+						"tckmin_x_minus_2_ps of %u\n",
 					       temp2, i, mclk_ps,
-					       tCKmin_X_minus_2_ps);
+					       tckmin_x_minus_2_ps);
 					continue;
 				} else {
 					not_ok++;
@@ -397,11 +397,11 @@
 	} else {
 		debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
 	}
-	outpdimm->all_DIMMs_ECC_capable = temp1;
+	outpdimm->all_dimms_ecc_capable = temp1;
 
 #ifndef CONFIG_FSL_DDR3
 	/* FIXME: move to somewhere else to validate. */
-	if (mclk_ps > tCKmax_max_ps) {
+	if (mclk_ps > tckmax_max_ps) {
 		printf("Warning: some of the installed DIMMs "
 				"can not operate this slowly.\n");
 		return 1;
@@ -464,10 +464,10 @@
 
 #if defined(CONFIG_FSL_DDR2)
 	if (lowest_good_caslat < 4) {
-		additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
-			? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
-		if (mclk_to_picos(additive_latency) > tRCD_ps) {
-			additive_latency = picos_to_mclk(tRCD_ps);
+		additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
+			? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
+		if (mclk_to_picos(additive_latency) > trcd_ps) {
+			additive_latency = picos_to_mclk(trcd_ps);
 			debug("setting additive_latency to %u because it was "
 				" greater than tRCD_ps\n", additive_latency);
 		}
@@ -487,7 +487,7 @@
 	 *
 	 * AL <= tRCD(min)
 	 */
-	if (mclk_to_picos(additive_latency) > tRCD_ps) {
+	if (mclk_to_picos(additive_latency) > trcd_ps) {
 		printf("Error: invalid additive latency exceeds tRCD(min).\n");
 		return 1;
 	}
@@ -507,15 +507,15 @@
 	 */
 	outpdimm->additive_latency = additive_latency;
 
-	debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
-	debug("tRCD_ps   = %u\n", outpdimm->tRCD_ps);
-	debug("tRP_ps    = %u\n", outpdimm->tRP_ps);
-	debug("tRAS_ps   = %u\n", outpdimm->tRAS_ps);
-	debug("tWR_ps    = %u\n", outpdimm->tWR_ps);
-	debug("tWTR_ps   = %u\n", outpdimm->tWTR_ps);
-	debug("tRFC_ps   = %u\n", outpdimm->tRFC_ps);
-	debug("tRRD_ps   = %u\n", outpdimm->tRRD_ps);
-	debug("tRC_ps    = %u\n", outpdimm->tRC_ps);
+	debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
+	debug("trcd_ps   = %u\n", outpdimm->trcd_ps);
+	debug("trp_ps    = %u\n", outpdimm->trp_ps);
+	debug("tras_ps   = %u\n", outpdimm->tras_ps);
+	debug("twr_ps    = %u\n", outpdimm->twr_ps);
+	debug("twtr_ps   = %u\n", outpdimm->twtr_ps);
+	debug("trfc_ps   = %u\n", outpdimm->trfc_ps);
+	debug("trrd_ps   = %u\n", outpdimm->trrd_ps);
+	debug("trc_ps    = %u\n", outpdimm->trc_ps);
 
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 842bf19..b9ae950 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -457,7 +457,7 @@
 			 * which is currently STEP_ASSIGN_ADDRESSES.
 			 */
 			populate_memctl_options(
-					timing_params[i].all_DIMMs_registered,
+					timing_params[i].all_dimms_registered,
 					&pinfo->memctl_opts[i],
 					pinfo->dimm_params[i], i);
 			/*
@@ -466,7 +466,7 @@
 			 * using fixed parameters, this function should be
 			 * be called from board init file.
 			 */
-			if (timing_params[i].all_DIMMs_registered)
+			if (timing_params[i].all_dimms_registered)
 				assert_reset = 1;
 		}
 		if (assert_reset) {
@@ -589,7 +589,7 @@
 	 */
 	deassert_reset = board_need_mem_reset();
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (info.common_timing_params[i].all_DIMMs_registered)
+		if (info.common_timing_params[i].all_dimms_registered)
 			deassert_reset = 1;
 	}
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 30cdca4..1297845 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -499,7 +499,7 @@
 	return 0;
 }
 
-unsigned int populate_memctl_options(int all_DIMMs_registered,
+unsigned int populate_memctl_options(int all_dimms_registered,
 			memctl_options_t *popts,
 			dimm_params_t *pdimm,
 			unsigned int ctrl_num)
@@ -635,20 +635,20 @@
 	popts->ba_intlv_ctl = 0;
 
 	/* Memory Organization Parameters */
-	popts->registered_dimm_en = all_DIMMs_registered;
+	popts->registered_dimm_en = all_dimms_registered;
 
 	/* Operational Mode Paramters */
 
 	/* Pick ECC modes */
-	popts->ECC_mode = 0;		  /* 0 = disabled, 1 = enabled */
+	popts->ecc_mode = 0;		  /* 0 = disabled, 1 = enabled */
 #ifdef CONFIG_DDR_ECC
 	if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 		if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
-			popts->ECC_mode = 1;
+			popts->ecc_mode = 1;
 	} else
-		popts->ECC_mode = 1;
+		popts->ecc_mode = 1;
 #endif
-	popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+	popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 
 	/*
 	 * Choose DQS config
@@ -656,9 +656,9 @@
 	 * 1 for DDR2
 	 */
 #if defined(CONFIG_FSL_DDR1)
-	popts->DQS_config = 0;
+	popts->dqs_config = 0;
 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
-	popts->DQS_config = 1;
+	popts->dqs_config = 1;
 #endif
 
 	/* Choose self-refresh during sleep. */
@@ -705,15 +705,15 @@
 	/* Choose burst length. */
 #if defined(CONFIG_FSL_DDR3)
 #if defined(CONFIG_E500MC)
-	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
+	popts->otf_burst_chop_en = 0;	/* on-the-fly burst chop disable */
 	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
 #else
 	if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 		/* 32-bit or 16-bit bus */
-		popts->OTF_burst_chop_en = 0;
+		popts->otf_burst_chop_en = 0;
 		popts->burst_length = DDR_BL8;
 	} else {
-		popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
+		popts->otf_burst_chop_en = 1;	/* on-the-fly burst chop */
 		popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
 	}
 #endif
@@ -756,8 +756,8 @@
 	 *	- number of components, number of active ranks
 	 *	- how much time you want to spend playing around
 	 */
-	popts->twoT_en = 0;
-	popts->threeT_en = 0;
+	popts->twot_en = 0;
+	popts->threet_en = 0;
 
 	/* for RDIMM, address parity enable */
 	popts->ap_en = 1;
@@ -775,7 +775,7 @@
 	popts->bstopre = 0x100;
 
 	/* Minimum CKE pulse width -- tCKE(MIN) */
-	popts->tCKE_clock_pulse_width_ps
+	popts->tcke_clock_pulse_width_ps
 		= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 
 	/*
@@ -786,17 +786,17 @@
 	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
 	 */
 #if defined(CONFIG_FSL_DDR1)
-	popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
+	popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
 
 #elif defined(CONFIG_FSL_DDR2)
 	/*
 	 * x4/x8;  some datasheets have 35000
 	 * x16 wide columns only?  Use 50000?
 	 */
-	popts->tFAW_window_four_activates_ps = 37500;
+	popts->tfaw_window_four_activates_ps = 37500;
 
 #elif defined(CONFIG_FSL_DDR3)
-	popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
+	popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
 #endif
 	popts->zq_en = 0;
 	popts->wrlvl_en = 0;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index bec8966..946ea97 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -20,6 +20,7 @@
 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
 
 #define FSL_DDR_VER_4_7	47
+#define FSL_DDR_VER_5_0	50
 
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
@@ -557,6 +558,7 @@
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #ifdef CONFIG_PPC_T4240
 #define CONFIG_MAX_CPUS			12
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	8
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_SYS_NUM_FM2_DTSEC	8
@@ -564,6 +566,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	3
 #else
 #define CONFIG_MAX_CPUS			8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	7
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_DTSEC	7
@@ -578,9 +581,12 @@
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_PME_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM1_CLK		3
+#define CONFIG_SYS_FM2_CLK		3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
@@ -593,6 +599,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -608,6 +615,7 @@
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
@@ -617,6 +625,7 @@
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
@@ -624,6 +633,7 @@
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	2
@@ -635,6 +645,7 @@
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 #define CONFIG_SYS_NUM_FM1_10GEC	0
 #define CONFIG_NUM_DDR_CONTROLLERS	1
@@ -646,22 +657,30 @@
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
 #define CONFIG_MAX_CPUS			4
-#define CONFIG_SYS_FSL_NUM_CC_PLLS	5
+#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#define CONFIG_MAX_CPUS			2
+#endif
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
+#define CONFIG_SYS_SDHC_CLOCK		0
 #define CONFIG_SYS_FSL_NUM_LAWS		16
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SEC_COMPAT	5
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_NUM_DDR_CONTROLLERS	1
-#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
+#define CONFIG_PME_PLAT_CLK_DIV		2
+#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_FM_PLAT_CLK_DIV	1
+#define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index bd312ad..2cad6e2 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -45,48 +45,48 @@
 
 	unsigned int mtb_ps;	/* medium timebase ps, only for ddr3 */
 	unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
-	unsigned int tAA_ps;	/* minimum CAS latency time, only for ddr3 */
-	unsigned int tFAW_ps;	/* four active window delay, only for ddr3 */
+	unsigned int taa_ps;	/* minimum CAS latency time, only for ddr3 */
+	unsigned int tfaw_ps;	/* four active window delay, only for ddr3 */
 
 	/*
 	 * SDRAM clock periods
 	 * The range for these are 1000-10000 so a short should be sufficient
 	 */
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmin_X_minus_1_ps;
-	unsigned int tCKmin_X_minus_2_ps;
-	unsigned int tCKmax_ps;
+	unsigned int tckmin_x_ps;
+	unsigned int tckmin_x_minus_1_ps;
+	unsigned int tckmin_x_minus_2_ps;
+	unsigned int tckmax_ps;
 
 	/* SPD-defined CAS latencies */
-	unsigned int caslat_X;
-	unsigned int caslat_X_minus_1;
-	unsigned int caslat_X_minus_2;
+	unsigned int caslat_x;
+	unsigned int caslat_x_minus_1;
+	unsigned int caslat_x_minus_2;
 
 	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
 
 	/* basic timing parameters */
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
 
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;   /* max = 255 ns + 256 ns + .75 ns
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;   /* max = 255 ns + 256 ns + .75 ns
 				       = 511750 ps */
 
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
 
 	/* DDR3 doesn't need these as below */
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
 
 	/* DDR3 RDIMM */
 	unsigned char rcw[16];	/* Register Control Word 0-15 */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index f4eec82..2c3c514 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -219,13 +219,13 @@
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
-	unsigned int all_DIMMs_ECC_capable;
-	unsigned int all_DIMMs_tCKmax_ps;
-	unsigned int all_DIMMs_burst_lengths_bitmask;
-	unsigned int all_DIMMs_registered;
-	unsigned int all_DIMMs_unbuffered;
+	unsigned int all_dimms_ecc_capable;
+	unsigned int all_dimms_tckmax_ps;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
 	/*	unsigned int lowest_common_SPD_caslat; */
-	unsigned int all_DIMMs_minimum_tRCD_ps;
+	unsigned int all_dimms_minimum_trcd_ps;
 } memctl_options_partial_t;
 
 #define DDR_DATA_BUS_WIDTH_64 0
@@ -261,10 +261,10 @@
 	unsigned int addr_hash;
 
 	/* Operational mode parameters */
-	unsigned int ECC_mode;	 /* Use ECC? */
+	unsigned int ecc_mode;	 /* Use ECC? */
 	/* Initialize ECC using memory controller? */
-	unsigned int ECC_init_using_memctl;
-	unsigned int DQS_config;	/* Use DQS? maybe only with DDR2? */
+	unsigned int ecc_init_using_memctl;
+	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
 	/* SREN - self-refresh during sleep */
 	unsigned int self_refresh_in_sleep;
 	unsigned int dynamic_power;	/* DYN_PWR */
@@ -272,7 +272,7 @@
 	unsigned int data_bus_width;
 	unsigned int burst_length;	/* BL4, OTF and BL8 */
 	/* On-The-Fly Burst Chop enable */
-	unsigned int OTF_burst_chop_en;
+	unsigned int otf_burst_chop_en;
 	/* mirrior DIMMs for DDR3 */
 	unsigned int mirrored_dimm;
 	unsigned int quad_rank_present;
@@ -297,11 +297,11 @@
 	unsigned int wrlvl_ctl_3;
 
 	unsigned int half_strength_driver_enable;
-	unsigned int twoT_en;
-	unsigned int threeT_en;
+	unsigned int twot_en;
+	unsigned int threet_en;
 	unsigned int bstopre;
-	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
-	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
+	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
+	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
 
 	/* Rtt impedance */
 	unsigned int rtt_override;		/* rtt_override enable */
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
new file mode 100644
index 0000000..3cac2d4
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_FSL_ERRATA_H
+#define _ASM_FSL_ERRATA_H
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+static inline bool has_erratum_a006379(void)
+{
+	u32 svr = get_svr();
+	if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2))
+		return true;
+
+	return false;
+}
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 749411c..5be718b 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -18,24 +18,6 @@
 /* Freescale-specific PCI config registers */
 #define FSL_PCI_PBFR		0x44
 
-#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
-/* Currently only the PCIe capability is used, so hardcode the offset.
- * if more capabilities need to be justified, the capability link method
- * should be applied here
- */
-#define FSL_PCIE_CAP_ID		0x70
-#define PCI_DCR		0x78    /* PCIe Device Control Register */
-#define PCI_DSR		0x7a    /* PCIe Device Status Register */
-#define PCI_LSR		0x82    /* PCIe Link Status Register */
-#define PCI_LCR		0x80    /* PCIe Link Control Register */
-#else
-#define FSL_PCIE_CAP_ID		0x4c
-#define PCI_DCR		0x54    /* PCIe Device Control Register */
-#define PCI_DSR		0x56    /* PCIe Device Status Register */
-#define PCI_LSR		0x5e    /* PCIe Link Status Register */
-#define PCI_LCR		0x5c    /* PCIe Link Control Register */
-#endif
-
 #define FSL_PCIE_CFG_RDY	0x4b0
 #define FSL_PROG_IF_AGENT	0x1
 
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index c36f3c3..4c7f0b1 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -7,6 +7,7 @@
 #ifndef __FSL_SECURE_BOOT_H
 #define __FSL_SECURE_BOOT_H
 
+#ifdef CONFIG_SECURE_BOOT
 #if defined(CONFIG_FSL_CORENET)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
 #else
@@ -15,3 +16,4 @@
 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
 
 #endif
+#endif
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 01c9eff..814a535 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -279,8 +279,8 @@
 	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
 	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
 	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
-	u32 DQS_config_offset_count;	/* DQS Config Offset Count */
-	u32 DQS_config_offset_time;	/* DQS Config Offset Time */
+	u32 dqs_config_offset_count;	/* DQS Config Offset Count */
+	u32 dqs_config_offset_time;	/* DQS Config Offset Time */
 	u32 DQS_delay_status;	/* DQS Delay Status */
 	u32 res0[0xF];
 	u32 prioman_config1;	/* Priority Manager Configuration */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3a10d77..e516e07 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1671,6 +1671,7 @@
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN	0x003c0000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
@@ -2016,20 +2017,13 @@
 		u8  res_004[0x0c];
 		u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
 		u8  res_014[0x0c];
-	} clkcsr[8];
-	u8	res_100[0x700]; /* 0x100 */
-	u32	pllc1gsr;	/* 0x800 Cluster PLL 1 General Status */
-	u8	res10[0x1c];
-	u32	pllc2gsr;	/* 0x820 Cluster PLL 2 General Status */
-	u8	res11[0x1c];
-	u32	pllc3gsr;	/* 0x840 Cluster PLL 3 General Status */
-	u8	res12[0x1c];
-	u32	pllc4gsr;	/* 0x860 Cluster PLL 4 General Status */
-	u8	res13[0x1c];
-	u32	pllc5gsr;	/* 0x880 Cluster PLL 5 General Status */
-	u8	res14[0x1c];
-	u32	pllc6gsr;	/* 0x8a0 Cluster PLL 6 General Status */
-	u8	res15[0x35c];
+	} clkcsr[12];
+	u8	res_100[0x680]; /* 0x100 */
+	struct {
+		u32 pllcngsr;
+		u8 res10[0x1c];
+	} pllcgsr[12];
+	u8	res21[0x280];
 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
 	u8	res16[0x1c];
 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c
index 36d02ad..23a71d5 100644
--- a/board/exmeritus/hww1u1a/ddr.c
+++ b/board/exmeritus/hww1u1a/ddr.c
@@ -30,5 +30,5 @@
 	popts->clk_adjust = 4;
 	popts->cpo_override = 4;
 	popts->write_data_delay = 2;
-	popts->twoT_en = 0;
+	popts->twot_en = 0;
 }
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
index 2fabbc7..272afc1 100644
--- a/board/freescale/b4860qds/b4860qds_qixis.h
+++ b/board/freescale/b4860qds/b4860qds_qixis.h
@@ -21,4 +21,9 @@
 
 #define QIXIS_SRDS1CLK_122		0x5a
 #define QIXIS_SRDS1CLK_125		0x5e
+
+/* SGMII */
+#define PHY_BASE_ADDR		0x18
+#define PORT_NUM		0x04
+#define REGNUM			0x00
 #endif
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
new file mode 100644
index 0000000..57b726e
--- /dev/null
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
new file mode 100644
index 0000000..577dabf
--- /dev/null
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x2A_0x98
+140e0018 0f001218 00000000 00000000
+54980000 9000a000 f8025000 a9000000
+01000000 00000000 00000000 0001b1f8
+00000000 14000020 00000000 00000011
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index b82b3d4..2d14923 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -31,20 +31,20 @@
 	.edc_config = 2,	/* ECC */
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1071,
-	.caslat_X = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
-	.tAA_ps = 13910,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13910,
-	.tRRD_ps = 6000,
-	.tRP_ps = 13910,
-	.tRAS_ps = 34000,
-	.tRC_ps = 48910,
-	.tRFC_ps = 260000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1071,
+	.caslat_x = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
+	.taa_ps = 13910,
+	.twr_ps = 15000,
+	.trcd_ps = 13910,
+	.trrd_ps = 6000,
+	.trp_ps = 13910,
+	.tras_ps = 34000,
+	.trc_ps = 48910,
+	.trfc_ps = 260000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 35000,
+	.tfaw_ps = 35000,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -71,7 +71,7 @@
 	u32 wrlvl_ctl_3;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -129,7 +129,7 @@
 				popts->wrlvl_start = pbsp->wrlvl_start;
 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -146,7 +146,7 @@
 		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index dc4ef80..a8fc845 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -150,6 +150,8 @@
 	struct memac_mdio_info tg_memac_mdio_info;
 	unsigned int i;
 	unsigned int  serdes1_prtcl, serdes2_prtcl;
+	int qsgmii;
+	struct mii_dev *bus;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -281,6 +283,22 @@
 		break;
 	}
 
+	/*set PHY address for QSGMII Riser Card on slot2*/
+	bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+	qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
+
+	if (qsgmii) {
+		switch (serdes2_prtcl) {
+		case 0xb2:
+		case 0x8d:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
+			break;
+		default:
+			break;
+		}
+	}
+
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1;
 
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
index c82fe0a..a9e92f2 100644
--- a/board/freescale/bsc9131rdb/ddr.c
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -114,20 +114,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index fdea193..b3130be 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -136,20 +136,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index b017cfd..804ea19 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -26,20 +26,20 @@
 	.edc_config = 2,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1650,
-	.caslat_X = 0x7e << 4,	/* 5,6,7,8,9,10 */
-	.tAA_ps = 14050,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13500,
-	.tRRD_ps = 75000,
-	.tRP_ps = 13500,
-	.tRAS_ps = 40000,
-	.tRC_ps = 49500,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 75000,
-	.tRTP_ps = 75000,
+	.tckmin_x_ps = 1650,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 14050,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 75000,
+	.trp_ps = 13500,
+	.tras_ps = 40000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 75000,
+	.trtp_ps = 75000,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 30000,
+	.tfaw_ps = 30000,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -62,7 +62,7 @@
 				unsigned int ctrl_num)
 {
 	int i;
-	popts->clk_adjust = 2;
+	popts->clk_adjust = 4;
 	popts->cpo_override = 0x1f;
 	popts->write_data_delay = 4;
 	popts->half_strength_driver_enable = 1;
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
index cd8fc21..80e5fff 100644
--- a/board/freescale/c29xpcie/law.c
+++ b/board/freescale/c29xpcie/law.c
@@ -10,8 +10,8 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
 					LAW_TRGT_IF_PLATFORM_SRAM),
 };
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index ddd1ef8..84844ee 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -46,11 +46,11 @@
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 4, BOOKE_PAGESZ_4K, 1),
+			0, 4, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_16K, 1),
+			0, 5, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
 			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 26e2eeb..d8fed14 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -79,7 +79,9 @@
 	u8 clk_freq[6];	/* Clock Measurement Registers */
 	u8 res_c6[8];
 	u8 clk_base[2];	/* Clock Frequency Base Reg */
-	u8 res_d0[16];
+	u8 res_d0[8];
+	u8 cms[2];	/* Core Management Space Address Register, 0xD8 */
+	u8 res_c0[6];
 	u8 aux2[4];	/* Auxiliary Registers,0xE0 */
 	u8 res14[10];
 	u8 aux_ad;
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index d789364..9c18dd8 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -18,7 +18,11 @@
 #endif
 
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* some boards with non-256-bytes EEPROM have special define */
+/* for MAX_NUM_PORTS in board-specific file */
+#ifndef MAX_NUM_PORTS
 #define MAX_NUM_PORTS	23
+#endif
 #define NXID_VERSION	1
 #endif
 
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 517e87f..18e2ff6 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -114,7 +114,7 @@
 	u32 wrlvl_start;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -217,7 +217,7 @@
 					pbsp->write_data_delay;
 				popts->clk_adjust = pbsp->clk_adjust;
 				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -234,7 +234,7 @@
 		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index a594efc..35825c4 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -76,6 +76,8 @@
 
 #define BRDCFG2_REG_GPIO_SEL	0x20
 
+#define PHY_BASE_ADDR		0x00
+
 /*
  * BRDCFG1 mask and value for each MAC
  *
@@ -365,6 +367,7 @@
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
 	int lane;
+	struct mii_dev *bus;
 
 	printf("Initializing Fman\n");
 
@@ -470,6 +473,9 @@
 		}
 	}
 
+	bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
+	set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
+
 	/*
 	 * For 10G, we only support one XAUI card per Fman.  If present, then we
 	 * force its routing and never touch those bits again, which removes the
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 597d0cb..e5beb55 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -37,6 +37,9 @@
 #define EMI1_MASK	0xc0000000
 #define EMI2_MASK	0x30000000
 
+#define PHY_BASE_ADDR	0x00
+#define PHY_BASE_ADDR_SLOT5	0x10
+
 static int mdio_mux[NUM_FM_PORTS];
 
 static char *mdio_names[16] = {
@@ -290,6 +293,7 @@
 	int i;
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	struct tgec_mdio_info tgec_mdio_info;
+	struct mii_dev *bus;
 
 	/* Initialize the mdio_mux array so we can recognize empty elements */
 	for (i = 0; i < NUM_FM_PORTS; i++)
@@ -370,6 +374,9 @@
 			break;
 		}
 	}
+	bus = mii_dev_for_muxval(EMI1_SLOT5);
+	set_sgmii_phy(bus, FM1_DTSEC1,
+		      CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
 
 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 		int idx = i - FM1_10GEC1, lane, slot;
@@ -435,6 +442,11 @@
 		}
 	}
 
+	bus = mii_dev_for_muxval(EMI1_SLOT3);
+	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+	bus = mii_dev_for_muxval(EMI1_SLOT4);
+	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+
 	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 		int idx = i - FM2_10GEC1, lane, slot;
 		switch (fm_info_get_enet_if(i)) {
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index fa07ff3..ad1bffd 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -77,6 +77,12 @@
 
 #define BRDCFG2_REG_GPIO_SEL	0x20
 
+/* SGMII */
+#define PHY_BASE_ADDR		0x00
+#define REGNUM			0x00
+#define PORT_NUM_FM1		0x04
+#define PORT_NUM_FM2		0x02
+
 /*
  * BRDCFG1 mask and value for each MAC
  *
@@ -415,6 +421,9 @@
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
 	int lane;
+	struct mii_dev *bus;
+	int qsgmii;
+	int phy_real_addr;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
@@ -449,6 +458,8 @@
 				"SUPER_HYDRA_FM1_SGMII_MDIO");
 	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
 				"SUPER_HYDRA_FM2_SGMII_MDIO");
+	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+			      "SUPER_HYDRA_FM3_SGMII_MDIO");
 	super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
 				"SUPER_HYDRA_FM1_TGEC_MDIO");
 	super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
@@ -573,6 +584,42 @@
 		}
 	}
 
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
+	qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
+
+	if (qsgmii) {
+		for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
+			if (fm_info_get_enet_if(i) ==
+					PHY_INTERFACE_MODE_SGMII) {
+				phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
+				fm_info_set_phy_address(i, phy_real_addr);
+			}
+		}
+		switch (srds_prtcl) {
+		case 0x00:
+		case 0x03:
+		case 0x04:
+		case 0x06:
+		case 0x11:
+		case 0x2a:
+		case 0x34:
+		case 0x36:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
+			break;
+		case 0x01:
+		case 0x02:
+		case 0x05:
+		case 0x07:
+		case 0x35:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
+			break;
+		default:
+			break;
+		}
+	}
+
 	/*
 	 * For 10G, we only support one XAUI card per Fman.  If present, then we
 	 * force its routing and never touch those bits again, which removes the
@@ -638,10 +685,22 @@
 				break;
 			};
 
-			super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO",
-					mdio_mux[i].mask, mdio_mux[i].val);
-			fm_info_set_mdio(i,
-			miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"));
+			if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
+				super_hydra_mdio_set_mux(
+						"SUPER_HYDRA_FM3_SGMII_MDIO",
+						mdio_mux[i].mask,
+						mdio_mux[i].val);
+				fm_info_set_mdio(i, miiphy_get_dev_by_name(
+						"SUPER_HYDRA_FM3_SGMII_MDIO"));
+			} else {
+				super_hydra_mdio_set_mux(
+						"SUPER_HYDRA_FM2_SGMII_MDIO",
+						mdio_mux[i].mask,
+						mdio_mux[i].val);
+				fm_info_set_mdio(i, miiphy_get_dev_by_name(
+						"SUPER_HYDRA_FM2_SGMII_MDIO"));
+			}
+
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
 			/*
@@ -672,6 +731,11 @@
 		}
 	}
 
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
+	set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
+	set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
+
 	/*
 	 * For 10G, we only support one XAUI card per Fman.  If present, then we
 	 * force its routing and never touch those bits again, which removes the
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
index c66750e..3d257d0 100644
--- a/board/freescale/mpc8349emds/ddr.c
+++ b/board/freescale/mpc8349emds/ddr.c
@@ -15,7 +15,7 @@
 	u32 clk_adjust;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -70,7 +70,7 @@
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -86,7 +86,7 @@
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->cpo_override = pbsp_highest->cpo;
 		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
@@ -97,5 +97,5 @@
 	 *	- number of DIMMs installed
 	 */
 	popts->half_strength_driver_enable = 0;
-	popts->DQS_config = 0;	/* only true DQS signal is used on board */
+	popts->dqs_config = 0;	/* only true DQS signal is used on board */
 }
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 5711374..9e79815 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -36,7 +36,7 @@
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index 94219b9..6cf9bc1 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -49,7 +49,7 @@
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 5711374..9e79815 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -36,7 +36,7 @@
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index a7ff668..52e4f42 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -17,7 +17,7 @@
 	u32 clk_adjust;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -139,7 +139,7 @@
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -155,7 +155,7 @@
 		popts->clk_adjust = pbsp->clk_adjust;
 		popts->cpo_override = pbsp->cpo;
 		popts->write_data_delay = pbsp->write_data_delay;
-		popts->twoT_en = pbsp->force_2T;
+		popts->twot_en = pbsp->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 94219b9..6cf9bc1 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -49,7 +49,7 @@
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 5d35757..651652a 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -106,5 +106,5 @@
 
 found:
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 }
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 681f052..ab1b41d 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -172,20 +172,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1875,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
index 0045127..ed41a05 100644
--- a/board/freescale/p1010rdb/law.c
+++ b/board/freescale/p1010rdb/law.c
@@ -9,11 +9,9 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SDCARD
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 06aa800..e940d22 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -21,10 +21,8 @@
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_ifc.h>
 #include <asm/fsl_pci.h>
-
-#ifndef CONFIG_SDCARD
 #include <hwconfig.h>
-#endif
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,10 +31,30 @@
 #define MUX_CPLD_TDM			0x01
 #define MUX_CPLD_SPICS0_FLASH		0x00
 #define MUX_CPLD_SPICS0_SLIC		0x02
+#define PMUXCR1_IFC_MASK       0x00ffff00
+#define PMUXCR1_SDHC_MASK      0x00fff000
+#define PMUXCR1_SDHC_ENABLE    0x00555000
+
+enum {
+	MUX_TYPE_IFC,
+	MUX_TYPE_SDHC,
+	MUX_TYPE_SPIFLASH,
+	MUX_TYPE_TDM,
+	MUX_TYPE_CAN,
+	MUX_TYPE_CS0_NOR,
+	MUX_TYPE_CS0_NAND,
+};
+
+enum {
+	I2C_READ_BANK,
+	I2C_READ_PCB_VER,
+};
+
+static uint sd_ifc_mux;
 
-#ifndef CONFIG_SDCARD
 struct cpld_data {
 	u8 cpld_ver; /* cpld revision */
+#if defined(CONFIG_P1010RDB_PA)
 	u8 pcba_ver; /* pcb revision number */
 	u8 twindie_ddr3;
 	u8 res1[6];
@@ -51,53 +69,18 @@
 	u8 por1; /* POR Options */
 	u8 por2; /* POR Options */
 	u8 por3; /* POR Options */
-};
-
-void cpld_show(void)
-{
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
-	printf("CPLD: V%x.%x PCBA: V%x.0\n",
-		in_8(&cpld_data->cpld_ver) & 0xF0,
-		in_8(&cpld_data->cpld_ver) & 0x0F,
-		in_8(&cpld_data->pcba_ver) & 0x0F);
-
-#ifdef CONFIG_DEBUG
-	printf("twindie_ddr =%x\n",
-		in_8(&cpld_data->twindie_ddr3));
-	printf("bank_sel =%x\n",
-		in_8(&cpld_data->bank_sel));
-	printf("usb2_sel =%x\n",
-		in_8(&cpld_data->usb2_sel));
-	printf("porsw_sel =%x\n",
-		in_8(&cpld_data->porsw_sel));
-	printf("tdm_can_sel =%x\n",
-		in_8(&cpld_data->tdm_can_sel));
-	printf("tdm_can_sel =%x\n",
-		in_8(&cpld_data->tdm_can_sel));
-	printf("spi_cs0_sel =%x\n",
-		in_8(&cpld_data->spi_cs0_sel));
-	printf("bcsr0 =%x\n",
-		in_8(&cpld_data->bcsr0));
-	printf("bcsr1 =%x\n",
-		in_8(&cpld_data->bcsr1));
-	printf("bcsr2 =%x\n",
-		in_8(&cpld_data->bcsr2));
-	printf("bcsr3 =%x\n",
-		in_8(&cpld_data->bcsr3));
-#endif
-}
+#elif defined(CONFIG_P1010RDB_PB)
+	u8 rom_loc;
 #endif
+};
 
 int board_early_init_f(void)
 {
 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-#ifndef CONFIG_SDCARD
 	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
 
 	/* Clock configuration to access CPLD using IFC(GPCM) */
 	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-#endif
 	/*
 	* Reset PCIe slots via GPIO4
 	*/
@@ -109,7 +92,6 @@
 
 int board_early_init_r(void)
 {
-#ifndef CONFIG_SDCARD
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 
@@ -133,7 +115,6 @@
 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
-#endif
 	return 0;
 }
 
@@ -144,13 +125,199 @@
 }
 #endif /* ifdef CONFIG_PCI */
 
+int config_board_mux(int ctrl_type)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 tmp;
+
+#if defined(CONFIG_P1010RDB_PA)
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x01;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x05;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		break;
+	case MUX_TYPE_TDM:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		break;
+	case MUX_TYPE_CAN:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		break;
+	default:
+		break;
+	}
+#elif defined(CONFIG_P1010RDB_PB)
+	uint orig_bus = i2c_get_bus_num();
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_TDM:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CAN:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NOR:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NAND:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	default:
+		break;
+	}
+	i2c_set_bus_num(orig_bus);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_P1010RDB_PB
+int i2c_pca9557_read(int type)
+{
+	u8 val;
+
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
+
+	switch (type) {
+	case I2C_READ_BANK:
+		val = (val & 0x10) >> 4;
+		break;
+	case I2C_READ_PCB_VER:
+		val = ((val & 0x60) >> 5) + 1;
+		break;
+	default:
+		break;
+	}
+
+	return val;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu;
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	u8 val;
 
 	cpu = gd->arch.cpu;
-	printf("Board: %sRDB\n", cpu->name);
+#if defined(CONFIG_P1010RDB_PA)
+	printf("Board: %sRDB-PA, ", cpu->name);
+#elif defined(CONFIG_P1010RDB_PB)
+	printf("Board: %sRDB-PB, ", cpu->name);
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+	val = 0x0;  /* no polarity inversion */
+	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
+#endif
 
+#ifdef CONFIG_SDCARD
+	/* switch to IFC to read info from CPLD */
+	config_board_mux(MUX_TYPE_IFC);
+#endif
+
+#if defined(CONFIG_P1010RDB_PA)
+	val = (in_8(&cpld_data->pcba_ver) & 0xf);
+	printf("PCB: v%x.0\n", val);
+#elif defined(CONFIG_P1010RDB_PB)
+	val = in_8(&cpld_data->cpld_ver);
+	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
+	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
+	val = in_8(&cpld_data->rom_loc) & 0xf;
+	puts("Boot from: ");
+	switch (val) {
+	case 0xf:
+		config_board_mux(MUX_TYPE_CS0_NOR);
+		printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
+		break;
+	case 0xe:
+		puts("SDHC\n");
+		val = 0x60; /* set pca9557 pin input/output */
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
+		break;
+	case 0x5:
+		config_board_mux(MUX_TYPE_IFC);
+		config_board_mux(MUX_TYPE_CS0_NAND);
+		puts("NAND\n");
+		break;
+	case 0x6:
+		config_board_mux(MUX_TYPE_IFC);
+		puts("SPI\n");
+		break;
+	default:
+		puts("unknown\n");
+		break;
+	}
+#endif
 	return 0;
 }
 
@@ -246,6 +413,16 @@
 	}
 }
 
+void fdt_del_ifc(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,ifc")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
 void fdt_disable_uart1(void *blob)
 {
 	int nodeoff;
@@ -289,9 +466,13 @@
 		fdt_del_flexcan(blob);
 		fdt_del_node_and_alias(blob, "ethernet2");
 	}
-#ifndef CONFIG_SDCARD
-	/* disable sdhc due to sdhc bug */
-	fdt_del_sdhc(blob);
+
+	/* Delete IFC node as IFC pins are multiplexing with SDHC */
+	if (sd_ifc_mux != MUX_TYPE_IFC)
+		fdt_del_ifc(blob);
+	else
+		fdt_del_sdhc(blob);
+
 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 		fdt_del_tdm(blob);
 		fdt_del_spi_slic(blob);
@@ -309,14 +490,27 @@
 		fdt_del_flexcan(blob);
 		fdt_disable_uart1(blob);
 	}
+}
 #endif
+
+#ifdef CONFIG_SDCARD
+int board_mmc_init(bd_t *bis)
+{
+	config_board_mux(MUX_TYPE_SDHC);
+		return -1;
+}
+#else
+void board_reset(void)
+{
+	/* mux to IFC to enable CPLD for reset */
+	if (sd_ifc_mux != MUX_TYPE_IFC)
+		config_board_mux(MUX_TYPE_IFC);
 }
 #endif
 
-#ifndef CONFIG_SDCARD
+
 int misc_init_r(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
@@ -324,7 +518,7 @@
 				MPC85xx_PMUXCR_CAN1_UART |
 				MPC85xx_PMUXCR_CAN2_TDM |
 				MPC85xx_PMUXCR_CAN2_UART);
-		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		config_board_mux(MUX_TYPE_CAN);
 	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 				MPC85xx_PMUXCR_CAN1_UART);
@@ -332,13 +526,39 @@
 				MPC85xx_PMUXCR_CAN1_TDM);
 		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
-		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
-		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		config_board_mux(MUX_TYPE_TDM);
 	} else {
 		/* defaultly spi_cs_sel to flash */
-		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		config_board_mux(MUX_TYPE_SPIFLASH);
 	}
 
+	if (hwconfig("esdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+	else if (hwconfig("ifc"))
+		config_board_mux(MUX_TYPE_IFC);
+
+#ifdef CONFIG_P1010RDB_PB
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
 	return 0;
 }
-#endif
+
+static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
+{
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (strcmp(argv[1], "ifc") == 0)
+		config_board_mux(MUX_TYPE_IFC);
+	else if (strcmp(argv[1], "sdhc") == 0)
+		config_board_mux(MUX_TYPE_SDHC);
+	else
+		return CMD_RET_USAGE;
+	return 0;
+}
+
+U_BOOT_CMD(
+	mux, 2, 0, pin_mux_cmd,
+	"configure multiplexing pin for IFC/SDHC bus in runtime",
+	"bus_type (e.g. mux sdhc)"
+);
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 77a8043..a7af0f6 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -42,7 +42,6 @@
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_SDCARD
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_16M, 1),
@@ -51,7 +50,6 @@
 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 3, BOOKE_PAGESZ_16M, 1),
-#endif
 
 #ifdef CONFIG_PCI
 	/* *I*G* - PCI */
@@ -66,7 +64,6 @@
 #endif
 #endif
 
-#ifndef CONFIG_SDCARD
 	/* *I*G - Board CPLD  */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -75,7 +72,6 @@
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
-#endif
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
index a639861..94d2c2b 100644
--- a/board/freescale/p1022ds/ddr.c
+++ b/board/freescale/p1022ds/ddr.c
@@ -17,7 +17,7 @@
 	u32 clk_adjust;		/* Range: 0-8 */
 	u32 cpo;		/* Range: 2-31 */
 	u32 write_data_delay;	/* Range: 0-6 */
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -72,7 +72,7 @@
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -88,7 +88,7 @@
 		popts->clk_adjust = pbsp->clk_adjust;
 		popts->cpo_override = pbsp->cpo;
 		popts->write_data_delay = pbsp->write_data_delay;
-		popts->twoT_en = pbsp->force_2T;
+		popts->twot_en = pbsp->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
index f027885..9fb61fd 100644
--- a/board/freescale/p1023rdb/ddr.c
+++ b/board/freescale/p1023rdb/ddr.c
@@ -33,20 +33,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1875,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 18000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 18000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index f8d0b35..202b4a5 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -21,6 +21,9 @@
 COBJS-y	+= spl_minimal.o tlb.o law.o
 
 else
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+endif
 
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index c0b72e0..81cc093 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -34,20 +34,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 #elif defined(CONFIG_P2020RDB)
 /* Micron MT41J128M16_15E */
@@ -65,20 +65,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1500,
-	.caslat_X = 0x7e << 4,	/* 5,6,7,8,9,10 */
-	.tAA_ps = 13500,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13500,
-	.tRRD_ps = 6000,
-	.tRP_ps = 13500,
-	.tRAS_ps = 36000,
-	.tRC_ps = 49500,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1500,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 13500,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 6000,
+	.trp_ps = 13500,
+	.tras_ps = 36000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 30000,
+	.tfaw_ps = 30000,
 };
 #elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 /* Micron MT41J512M8_187E */
@@ -96,20 +96,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 #elif defined(CONFIG_P1020RDB_PC)
 /*
@@ -133,20 +133,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1875,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 #elif	defined(CONFIG_P1024RDB) || \
 	defined(CONFIG_P1025RDB)
@@ -171,20 +171,20 @@
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1500,
-	.caslat_X = 0x3e << 4,	/* 5,6,7,8,9 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 6000,
-	.tRP_ps = 13125,
-	.tRAS_ps = 36000,
-	.tRC_ps = 49125,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1500,
+	.caslat_x = 0x3e << 4,	/* 5,6,7,8,9 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 6000,
+	.trp_ps = 13125,
+	.tras_ps = 36000,
+	.trc_ps = 49125,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 30000,
+	.tfaw_ps = 30000,
 };
 #else
 #error Missing raw timing data for this board
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
new file mode 100644
index 0000000..9bb0716
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+	66666000, 7499900, 83332500, 8999900,
+	99999000, 11111000, 12499800, 13333200
+};
+
+ulong get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#else
+	env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index ac07572..adfa7b1 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -15,59 +15,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_INIT_L2_ADDR
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-static void sdram_init(void)
-{
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
-	/* Set, but do not enable the memory */
-	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-#endif
-
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifndef CONFIG_QE
-	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-#elif defined(CONFIG_P1021RDB)
-	par_io_t *par_io = (par_io_t *)&(gur->qe_par_io);
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
@@ -80,35 +35,6 @@
 
 	puts("\nNAND boot... ");
 
-#ifndef CONFIG_QE
-	/* init DDR3 reset signal */
-	__raw_writel(0x02000000, &pgpio->gpdir);
-	__raw_writel(0x00200000, &pgpio->gpodr);
-	__raw_writel(0x00000000, &pgpio->gpdat);
-	udelay(1000);
-	__raw_writel(0x00200000, &pgpio->gpdat);
-	udelay(1000);
-	__raw_writel(0x00000000, &pgpio->gpdir);
-#elif defined(CONFIG_P1021RDB)
-	/* init DDR3 reset signal CE_PB8 */
-	out_be32(&par_io[1].cpdir1, 0x00004000);
-	out_be32(&par_io[1].cpodr, 0x00800000);
-	out_be32(&par_io[1].cppar1, 0x00000000);
-	/* reset DDR3 */
-	out_be32(&par_io[1].cpdat, 0x00800000);
-	udelay(1000);
-	out_be32(&par_io[1].cpdat, 0x00000000);
-	udelay(1000);
-	out_be32(&par_io[1].cpdat, 0x00800000);
-	/* disable the CE_PB8 */
-	out_be32(&par_io[1].cpdir1, 0x00000000);
-#endif
-
-#ifndef CONFIG_SYS_INIT_L2_ADDR
-	/* Initialize the DDR3 */
-	sdram_init();
-#endif
-
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
@@ -118,6 +44,7 @@
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
+	puts("\nSecond program loader running in sram...");
 	nand_boot();
 }
 
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index d4561c7..1c0008b 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -78,17 +78,8 @@
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
-#ifdef CONFIG_SYS_INIT_L2_ADDR
-	/* L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_256K, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_256K, 1),
-#else
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -101,8 +92,20 @@
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif /* P1020MBG */
-#endif /* not L2 SRAM */
 #endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index 59034f9..b12141f 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -17,7 +17,7 @@
 	u32 clk_adjust;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 
@@ -90,7 +90,7 @@
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -106,7 +106,7 @@
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->cpo_override = pbsp_highest->cpo;
 		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index 6d9a5de..cc1bfae 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -21,7 +21,7 @@
 	u32 wrlvl_start;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -76,7 +76,7 @@
 					pbsp->write_data_delay;
 				popts->clk_adjust = pbsp->clk_adjust;
 				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -93,7 +93,7 @@
 		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
new file mode 100644
index 0000000..8f0057b
--- /dev/null
+++ b/board/freescale/t1040qds/Makefile
@@ -0,0 +1,37 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-$(CONFIG_PCI)     += pci.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
new file mode 100644
index 0000000..f8b53b4
--- /dev/null
+++ b/board/freescale/t1040qds/README
@@ -0,0 +1,169 @@
+Overview
+--------
+The T1040QDS is a Freescale reference board that hosts the T1040 SoC
+(and variants).
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+    -  Packet parsing, classification, and distribution
+    -  Queue management for scheduling, packet sequencing, and congestion
+    	management
+    -  Cryptography Acceleration (SEC 5.0)
+    - RegEx Pattern Matching Acceleration (PME 2.2)
+    - IEEE Std 1588 support
+    - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+    - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+   - Four PCI Express 2.0 controllers running at up to 5 GHz
+   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+   - Upto two QSGMII interface
+   - Upto six SGMII interface supporting 1000 Mbps
+   - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+   - Two USB 2.0 controllers with integrated PHY
+   - SD/eSDHC/eMMC
+   -  eSPI controller
+   - Four I2C controllers
+   - Four UARTs
+   - Four GPIO controllers
+   - Integrated flash controller (IFC)
+   - LCD and HDMI interface (DIU) with 12 bit dual data rate
+   - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+ T1040QDS board Overview
+ -----------------------
+ - SERDES Connections, 8 lanes supporting:
+      — PCI Express: supporting Gen 1 and Gen 2;
+      — SGMII
+      — QSGMII
+      — SATA 2.0
+      — Aurora debug with dedicated connectors (T1040 only)
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ -IFC/Local Bus
+     - NAND flash: 8-bit, async, up to 2GB.
+     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+     - GASIC: Simple (minimal) target within Qixis FPGA
+     - PromJET rapid memory download support
+ - Ethernet
+     - Two on-board RGMII 10/100/1G ethernet ports.
+     - PHY #0 remains powered up during deep-sleep (T1040 only)
+ - QIXIS System Logic FPGA
+ - Clocks
+     - System and DDR clock (SYSCLK, “DDRCLK”)
+     - SERDES clocks
+ - Power Supplies
+ - Video
+     - DIU supports video at up to 1280x1024x32bpp
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     — Two type A ports with 5V@1.5A per port.
+     — Second port can be converted to OTG mini-AB
+ - SDHC
+     - SDHC port connects directly to an adapter card slot, featuring:
+     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
+     — Supporting eMMC memory devices
+ - SPI
+    -  On-board support of 3 different devices and sizes
+ - Other IO
+    - Two Serial ports
+    - ProfiBus port
+    - Four I2C ports
+
+Memory map on T1040QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+Start Address  End Address      Description                     Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - FPGA                      4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
+0xF_E000_0000  0xF_E7FF_FFFF    Promjet                         128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
+0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
+0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
+0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB
+
+
+NOR Flash memory Map on T1040QDS
+--------------------------------
+ Start          End             Definition                       Size
+0xEFF80000      0xEFFFFFFF      u-boot (current bank)            512KB
+0xEFF60000      0xEFF7FFFF      u-boot env (current bank)        128KB
+0xEFF40000      0xEFF5FFFF      FMAN Ucode (current bank)        128KB
+0xED300000      0xEFF3FFFF      rootfs (alt bank)                44MB + 256KB
+0xEC800000      0xEC8FFFF       Hardware device tree (alt bank)  1MB
+0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
+0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
+0xEBF80000      0xEBFFFFFF      u-boot (alt bank)                512KB
+0xEBF60000      0xEBF7FFFF      u-boot env (alt bank)            128KB
+0xEBF40000      0xEBF5FFFF      FMAN ucode (alt bank)            128KB
+0xE9300000      0xEBF3FFFF      rootfs (current bank)            44MB + 256KB
+0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
+0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
+0xE8000000      0xE801FFFF      RCW (current bank)               128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to T1040QDS
+
+1. U-boot environment variable hwconfig
+   The default hwconfig is:
+	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+					dr_mode=host,phy_type=utmi
+   Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+   fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+   Commands for switching to alternate bank.
+
+	1. To change from vbank0 to vbank4
+		=> qixis_reset altbank (it will boot using vbank4)
+
+	2.To change from vbank4 to vbank0
+		=> qixis reset (it will boot using vbank0)
+
+T1040 Personality
+--------------------
+
+T1022 Personality
+--------------------
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality
+--------------------
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
new file mode 100644
index 0000000..4fd17da
--- /dev/null
+++ b/board/freescale/t1040qds/ddr.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->twot_en = pbsp->force_2t;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found\n");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+		popts->twot_en = pbsp_highest->force_2t;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * rtt and rtt_wr override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
new file mode 100644
index 0000000..8ee206e
--- /dev/null
+++ b/board/freescale/t1040qds/ddr.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+#endif
diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c
new file mode 100644
index 0000000..a2dc027
--- /dev/null
+++ b/board/freescale/t1040qds/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c
new file mode 100644
index 0000000..c53e3b7
--- /dev/null
+++ b/board/freescale/t1040qds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
new file mode 100644
index 0000000..5abb18a
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *const freq[] = {"100", "125", "156.25", "161.13",
+						"122.88", "122.88", "122.88"};
+	int clock;
+
+	printf("Board: %sQDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0x15)
+		printf("IFCCard\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference: ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = (sw >> 6) & 3;
+	printf("Clock1=%sMHz ", freq[clock]);
+	clock = (sw >> 4) & 3;
+	printf("Clock2=%sMHz\n", freq[clock]);
+
+	return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_64:
+		return 64000000;
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	default:
+		return "Unknown frequency";
+	}
+}
+
+#define NUM_SRDS_BANKS	2
+int misc_init_r(void)
+{
+	u8 sw;
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS] = { 0 };
+	int i;
+
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
+		switch (clock) {
+		case 0:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+			break;
+		case 1:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		case 2:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		}
+	}
+
+	puts("SerDes1");
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 pllcr0 = srds_regs->bank[i].pllcr0;
+		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
+			       i + 1, serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+#endif
+}
+
+void qixis_dump_switch(void)
+{
+	int i, nr_of_cfgsw;
+
+	QIXIS_WRITE(cms[0], 0x00);
+	nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+	puts("DIP switch settings dump:\n");
+	for (i = 1; i <= nr_of_cfgsw; i++) {
+		QIXIS_WRITE(cms[0], i);
+		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+	}
+}
diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
new file mode 100644
index 0000000..79bdeda
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __T1040_QDS_H__
+#define __T1040_QDS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h
new file mode 100644
index 0000000..2ce8795
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds_qixis.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __T1040QDS_QIXIS_H__
+#define __T1040QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T1040QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+#endif
diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c
new file mode 100644
index 0000000..412c591
--- /dev/null
+++ b/board/freescale/t1040qds/tlb.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 26ac2a5..d70c310 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -56,7 +56,7 @@
 				popts->wrlvl_start = pbsp->wrlvl_start;
 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -75,7 +75,7 @@
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index d0a0951..8183af7 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -16,7 +16,7 @@
 	u32 wrlvl_ctl_3;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 6ac95ff..74df01a 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_28_6_12
-14180019 0c101916 00000000 00000000
-04383060 30548c00 6c020000 19000000
-00000000 ee0000ee 00000000 000187fc
-00000000 00000000 00000000 00000018
+120c0019 0c101915 00000000 00000000
+04383063 30548c00 6c020000 1d000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000020
diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c
index 5711374..9e79815 100644
--- a/board/stx/stxgp3/ddr.c
+++ b/board/stx/stxgp3/ddr.c
@@ -36,7 +36,7 @@
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c
index 56c87b2..71be3bf 100644
--- a/board/stx/stxssa/ddr.c
+++ b/board/stx/stxssa/ddr.c
@@ -37,7 +37,7 @@
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index a03a96b..9fc6f04 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -108,7 +108,7 @@
 		    ddr_freq <= pbsp->datarate_mhz_high) {
 			popts->clk_adjust = pbsp->clk_adjust;
 			popts->cpo_override = pbsp->cpo;
-			popts->twoT_en = 0;
+			popts->twot_en = 0;
 			break;
 		}
 		pbsp++;
diff --git a/boards.cfg b/boards.cfg
index aa2ee64..56af102 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -826,20 +826,34 @@
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS                            MPC8572DS                                                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS_36BIT                      MPC8572DS:36BIT                                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS_NAND                       MPC8572DS:NAND                                                                                                                    -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NAND                  P1010RDB:P1010RDB,36BIT,NAND                                                                                                      -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NAND_SECBOOT          P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                                  -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NOR                   P1010RDB:P1010RDB,36BIT                                                                                                           -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NOR_SECBOOT           P1010RDB:P1010RDB,36BIT,SECURE_BOOT                                                                                               -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_SDCARD                P1010RDB:P1010RDB,36BIT,SDCARD                                                                                                    -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_SPIFLASH              P1010RDB:P1010RDB,36BIT,SPIFLASH                                                                                                  -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_SPIFLASH_SECBOOT      P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT                                                                                      -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NAND                        P1010RDB:P1010RDB,NAND                                                                                                            -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NAND_SECBOOT                P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT                                                                                        -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NOR                         P1010RDB:P1010RDB                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NOR_SECBOOT                 P1010RDB:P1010RDB,SECURE_BOOT                                                                                                     -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_SDCARD                      P1010RDB:P1010RDB,SDCARD                                                                                                          -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_SPIFLASH                    P1010RDB:P1010RDB,SPIFLASH                                                                                                        -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_SPIFLASH_SECBOOT            P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT                                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NAND               P1010RDB:P1010RDB_PA,36BIT,NAND                                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NAND_SECBOOT       P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NOR                P1010RDB:P1010RDB_PA,36BIT                                                                                                        -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NOR_SECBOOT        P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT                                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SDCARD             P1010RDB:P1010RDB_PA,36BIT,SDCARD                                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SPIFLASH           P1010RDB:P1010RDB_PA,36BIT,SPIFLASH                                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SPIFLASH_SECBOOT   P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NAND                     P1010RDB:P1010RDB_PA,NAND                                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NAND_SECBOOT             P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NOR                      P1010RDB:P1010RDB_PA                                                                                                              -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NOR_SECBOOT              P1010RDB:P1010RDB_PA,SECURE_BOOT                                                                                                  -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SDCARD                   P1010RDB:P1010RDB_PA,SDCARD                                                                                                       -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SPIFLASH                 P1010RDB:P1010RDB_PA,SPIFLASH                                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SPIFLASH_SECBOOT         P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NAND               P1010RDB:P1010RDB_PB,36BIT,NAND                                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NAND_SECBOOT       P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NOR                P1010RDB:P1010RDB_PB,36BIT                                                                                                        -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NOR_SECBOOT        P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT                                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SDCARD             P1010RDB:P1010RDB_PB,36BIT,SDCARD                                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SPIFLASH           P1010RDB:P1010RDB_PB,36BIT,SPIFLASH                                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SPIFLASH_SECBOOT   P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NAND                     P1010RDB:P1010RDB_PB,NAND                                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NAND_SECBOOT             P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NOR                      P1010RDB:P1010RDB_PB                                                                                                              -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NOR_SECBOOT              P1010RDB:P1010RDB_PB,SECURE_BOOT                                                                                                  -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SDCARD                   P1010RDB:P1010RDB_PB,SDCARD                                                                                                       -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SPIFLASH                 P1010RDB:P1010RDB_PB,SPIFLASH                                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SPIFLASH_SECBOOT         P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS                              -                                                                                                                                 Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT                        P1022DS:36BIT                                                                                                                     Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT_NAND                   P1022DS:36BIT,NAND                                                                                                                Timur Tabi <timur@freescale.com>
@@ -947,6 +961,7 @@
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SDCARD                      T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                    -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SPIFLASH                    T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SRIO_PCIE_BOOT              T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t1040qds            T1040QDS                             T1040QDS:PPC_T1040                                                                                                                Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD          controlcenterd:36BIT,SDCARD                                                                                                       Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD_DEVELOP  controlcenterd:36BIT,SDCARD,DEVELOP                                                                                               Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_TRAILBLAZER           controlcenterd:TRAILBLAZER,SPIFLASH                                                                                               Dirk Eibach <eibach@gdsys.de>
diff --git a/doc/README.pblimage b/doc/README.pblimage
index 2b9bb5c..7fdd26b 100644
--- a/doc/README.pblimage
+++ b/doc/README.pblimage
@@ -14,20 +14,17 @@
 1. Building PBL Boot Image.
    The default Image is u-boot.pbl.
 
-   For eSPI boot(available on P3041/P4080/P5020):
+   For eSPI boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
 	To build the eSPI boot image:
-	make <board_name>_SPIFLASH_config
-	make u-boot.pbl
+	make <board_name>_SPIFLASH
 
-   For SD boot(available on P3041/P4080/P5020):
+   For SD boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
 	To build the SD boot image:
-	make <board_name>_SDCARD_config
-	make u-boot.pbl
+	make <board_name>_SDCARD
 
-   For Nand boot(available on P3041/P5020):
+   For Nand boot(available on P2041/P3041/P5020/P5040):
 	To build the NAND boot image:
-	make <board_name>_NAND_config
-	make u-boot.pbl
+	make <board_name>_NAND
 
 
 2. pblimage support available with mkimage utility will generate Freescale PBL
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 4edd849..dddde4f 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -29,6 +29,7 @@
 COBJS-$(CONFIG_PPC_P4080) += p4080.o
 COBJS-$(CONFIG_PPC_P5020) += p5020.o
 COBJS-$(CONFIG_PPC_P5040) += p5040.o
+COBJS-$(CONFIG_PPC_T1040) += t1040.o
 COBJS-$(CONFIG_PPC_T4240) += t4240.o
 COBJS-$(CONFIG_PPC_T4160) += t4240.o
 COBJS-$(CONFIG_PPC_B4420) += b4860.o
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 38fdbcd..5f197a9 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -21,6 +21,7 @@
 #define TX_PORT_1G_BASE		0x28
 #define MAX_NUM_TX_PORT_1G	CONFIG_SYS_NUM_FM1_DTSEC
 #define TX_PORT_10G_BASE	0x30
+#define MIIM_TIMEOUT    0xFFFF
 
 struct fm_muram {
 	u32 base;
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 14fa2ce..2d13145 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -274,3 +274,47 @@
 	}
 #endif
 }
+
+/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different.
+ *This function scans which Riser Card being used(QSGMII or SGMII Riser Card),
+ *then set the correct PHY address
+ */
+void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
+		unsigned int port_num, int phy_base_addr)
+{
+	unsigned int regnum = 0;
+	int qsgmii;
+	int i;
+	int phy_real_addr;
+
+	qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum);
+
+	if (!qsgmii)
+		return;
+
+	for (i = base_port; i < base_port + port_num; i++) {
+		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) {
+			phy_real_addr = phy_base_addr + i - base_port;
+			fm_info_set_phy_address(i, phy_real_addr);
+		}
+	}
+}
+
+/*to check whether qsgmii riser card is used*/
+int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
+		unsigned int port_num, unsigned regnum)
+{
+	int i;
+	int val;
+
+	if (!bus)
+		return 0;
+
+	for (i = phy_base_addr; i < phy_base_addr + port_num; i++) {
+		val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum);
+		if (val != MIIM_TIMEOUT)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
new file mode 100644
index 0000000..83cf081
--- /dev/null
+++ b/drivers/net/fm/t1040.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+	return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index d55db1a..2085cd6 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -295,6 +295,15 @@
 	int enabled, r, inbound = 0;
 	u16 ltssm;
 	u8 temp8, pcie_cap;
+	int pcie_cap_pos;
+	int pci_dcr;
+	int pci_dsr;
+	int pci_lsr;
+
+#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
+	int pci_lcr;
+#endif
+
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
 	struct pci_region *reg = hose->regions + hose->region_count;
 	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
@@ -367,7 +376,12 @@
 	hose->region_count++;
 
 	/* see if we are a PCIe or PCI controller */
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_dcr = pcie_cap_pos + 0x08;
+	pci_dsr = pcie_cap_pos + 0x0a;
+	pci_lsr = pcie_cap_pos + 0x12;
+
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	/* boot from PCIE --master */
@@ -406,15 +420,16 @@
 					 * - Master PERR (pci)
 					 * - ICCA (PCIe)
 					 */
-	pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
+	pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
 	temp32 |= 0xf000e;		/* set URR, FER, NFER (but not CER) */
-	pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
+	pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
 
 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
+	pci_lcr = pcie_cap_pos + 0x10;
 	temp32 = 0;
-	pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32);
+	pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
 	temp32 &= ~0x03;		/* Disable ASPM  */
-	pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
+	pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
 	udelay(1);
 #endif
 	if (pcie_cap == PCI_CAP_ID_EXP) {
@@ -494,7 +509,7 @@
 		out_be32(&pci->pme_msg_int_en, 0xffffffff);
 
 		/* Print the negotiated PCIe link width */
-		pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
+		pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
 		printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
 			pci_info->regs);
 
@@ -541,9 +556,9 @@
 		out_be32(&pci->pme_msg_det, 0xffffffff);
 	out_be32(&pci->pedr, 0xffffffff);
 
-	pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
+	pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
 	if (temp16) {
-		pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
+		pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
 	}
 
 	pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
@@ -554,10 +569,12 @@
 
 int fsl_is_pci_agent(struct pci_controller *hose)
 {
+	int pcie_cap_pos;
 	u8 pcie_cap;
 	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
 
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 	if (pcie_cap == PCI_CAP_ID_EXP) {
 		u8 header_type;
 
@@ -582,6 +599,7 @@
 	volatile ccsr_fsl_pci_t *pci;
 	struct pci_region *r;
 	pci_dev_t dev = PCI_BDF(busno,0,0);
+	int pcie_cap_pos;
 	u8 pcie_cap;
 
 	pci = (ccsr_fsl_pci_t *) pci_info->regs;
@@ -631,11 +649,11 @@
 #endif
 	}
 
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 	printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
 		"e" : "", pci_info->pci_num,
 		hose->first_busno, hose->last_busno);
-
 	return(hose->last_busno + 1);
 }
 
@@ -643,13 +661,15 @@
 void fsl_pci_config_unlock(struct pci_controller *hose)
 {
 	pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
+	int pcie_cap_pos;
 	u8 pcie_cap;
 	u16 pbfr;
 
 	if (!fsl_is_pci_agent(hose))
 		return;
 
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 	if (pcie_cap != 0x0) {
 		/* PCIe - set CFG_READY bit of Configuration Ready Register */
 		pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 2c07158..ed113bf 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -722,3 +722,68 @@
 	/* now call board specific pci_init()... */
 	pci_init_board();
 }
+
+/* Returns the address of the requested capability structure within the
+ * device's PCI configuration space or 0 in case the device does not
+ * support it.
+ * */
+int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
+			     int cap)
+{
+	int pos;
+	u8 hdr_type;
+
+	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
+
+	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
+
+	if (pos)
+		pos = pci_find_cap(hose, dev, pos, cap);
+
+	return pos;
+}
+
+/* Find the header pointer to the Capabilities*/
+int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
+			    u8 hdr_type)
+{
+	u16 status;
+
+	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
+
+	if (!(status & PCI_STATUS_CAP_LIST))
+		return 0;
+
+	switch (hdr_type) {
+	case PCI_HEADER_TYPE_NORMAL:
+	case PCI_HEADER_TYPE_BRIDGE:
+		return PCI_CAPABILITY_LIST;
+	case PCI_HEADER_TYPE_CARDBUS:
+		return PCI_CB_CAPABILITY_LIST;
+	default:
+		return 0;
+	}
+}
+
+int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
+{
+	int ttl = PCI_FIND_CAP_TTL;
+	u8 id;
+	u8 next_pos;
+
+	while (ttl--) {
+		pci_hose_read_config_byte(hose, dev, pos, &next_pos);
+		if (next_pos < CAP_START_POS)
+			break;
+		next_pos &= ~3;
+		pos = (int) next_pos;
+		pci_hose_read_config_byte(hose, dev,
+					  pos + PCI_CAP_LIST_ID, &id);
+		if (id == 0xff)
+			break;
+		if (id == cap)
+			return pos;
+		pos += PCI_CAP_LIST_NEXT;
+	}
+	return 0;
+}
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2f0bc6b..992aea7 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -16,6 +16,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -841,8 +843,6 @@
 
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 948394e..1d06c50 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -181,18 +181,18 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x08)  \
-					| FTIM0_NAND_TWP(0x06)   \
-					| FTIM0_NAND_TWCHT(0x03) \
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
+					| FTIM0_NAND_TWP(0x05)   \
+					| FTIM0_NAND_TWCHT(0x02) \
 					| FTIM0_NAND_TWH(0x04))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x18) \
-					| FTIM1_NAND_TWBE(0x23) \
-					| FTIM1_NAND_TRR(0x08)  \
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
+					| FTIM1_NAND_TWBE(0x1E) \
+					| FTIM1_NAND_TRR(0x07)  \
 					| FTIM1_NAND_TRP(0x05))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
 					| FTIM2_NAND_TREH(0x04) \
-					| FTIM2_NAND_TWHRE(0x3f))
-#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x22)
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 83779ef..cce2288 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -154,14 +154,16 @@
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
 #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1e) | \
-				FTIM1_NOR_TRAD_NOR(0x0f) | \
-				FTIM1_NOR_TSEQRAD_NOR(0x0f))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index ba3f7c2..c6b9aca 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -120,7 +120,11 @@
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#if defined(CONFIG_P1010RDB_PA)
 #define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
+#endif
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
@@ -152,10 +156,7 @@
 #define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1010 RDB */
 #define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for P1010 RDB */
 
-#ifndef CONFIG_SDCARD
 #define CONFIG_MISC_INIT_R
-#endif
-
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -203,25 +204,24 @@
 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
-
 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
 #define CONFIG_SYS_DDR_RCW_1		0x00000000
 #define CONFIG_SYS_DDR_RCW_2		0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0x470C0000	/* Type = DDR3  */
-#define CONFIG_SYS_DDR_CONTROL_2	0x04401010
+#define CONFIG_SYS_DDR_CONTROL		0xc70c0008      /* Type = DDR3  */
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
 #define CONFIG_SYS_DDR_TIMING_4		0x00000001
 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
 
-#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800	0x00330004
-#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6B4644
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b8644
 #define CONFIG_SYS_DDR_TIMING_2_800	0x0FA888CF
 #define CONFIG_SYS_DDR_CLK_CTRL_800	0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800	0x40461520
-#define CONFIG_SYS_DDR_MODE_2_800	0x8000c000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 
 /* settings for DDR3 at 667MT/s */
 #define CONFIG_SYS_DDR_TIMING_3_667		0x00010000
@@ -256,10 +256,6 @@
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 
-/* In case of SD card boot, IFC interface is not available because of muxing */
-#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_NO_FLASH
-#else
 /*
  * IFC Definitions
  */
@@ -322,6 +318,8 @@
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#if defined(CONFIG_P1010RDB_PA)
 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
@@ -329,13 +327,26 @@
 				| CSOR_NAND_PGS_512	/* Page Size = 512b */ \
 				| CSOR_NAND_SPRZ_16	/* Spare size = 16 */ \
 				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
+#endif
 
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
 
+#if defined(CONFIG_P1010RDB_PA)
 /* NAND Flash Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
 					FTIM0_NAND_TWP(0x0C)   | \
@@ -350,6 +361,23 @@
 					FTIM2_NAND_TWHRE(0x0f)
 #define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 
+#elif defined(CONFIG_P1010RDB_PB)
+/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a)  | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3	0x0
+#endif
+
 #define CONFIG_SYS_NAND_DDR_LAW		11
 
 /* Set up IFC registers for boot location NOR/NAND */
@@ -410,7 +438,6 @@
 					FTIM2_GPCM_TCH(0x0) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
-#endif	/* CONFIG_SDCARD */
 
 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
@@ -482,9 +509,21 @@
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define I2C_PCA9557_ADDR1		0x18
+#define I2C_PCA9557_ADDR2		0x19
+#define I2C_PCA9557_BUS_NUM		0
 
 /* I2C EEPROM */
-#undef CONFIG_ID_EEPROM
+#if defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define MAX_NUM_PORTS			9 /* for 128Bytes EEPROM */
+#endif
 /* enable read and write access to EEPROM */
 #define CONFIG_CMD_EEPROM
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -567,12 +606,7 @@
 #define CONFIG_LBA48
 #endif /* #ifdef CONFIG_FSL_SATA  */
 
-/*  SD interface will only be available in case of SD boot */
-#ifdef CONFIG_SDCARD
 #define CONFIG_MMC
-#define CONFIG_DEF_HWCONFIG		esdhc
-#endif
-
 #ifdef CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
@@ -613,9 +647,14 @@
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
+#if defined(CONFIG_P1010RDB_PA)
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_RANGE	(32 * CONFIG_ENV_SIZE) /* new block size 512K */
+#endif
 #define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
@@ -708,7 +747,6 @@
 #define CONFIG_HAS_ETH2
 #endif
 
-#define CONFIG_HOSTNAME		P1010RDB
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
@@ -747,7 +785,31 @@
 	"ext2load usb 0:4 $loadaddr $bootfile;"		\
 	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
 	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	CONFIG_BOOTMODE
+
+#if defined(CONFIG_P1010RDB_PA)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
+
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
+	"i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
+	"boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
+	"i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
+	"boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
+	"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
+#endif
 
 #define CONFIG_RAMBOOTCOMMAND		\
 	"setenv bootargs root=/dev/ram rw "	\
@@ -759,8 +821,6 @@
 
 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 862614b..2c4159b 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -746,8 +746,6 @@
 
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
new file mode 100644
index 0000000..2738242
--- /dev/null
+++ b/include/configs/T1040QDS.h
@@ -0,0 +1,761 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1040 QDS board configuration file
+ */
+#define CONFIG_T1040QDS
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE4			/* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1105)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE		0xffdf0000
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x10
+#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR	0x11
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t1040qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t1040qds/t1040qds.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 92a30ab..590799c 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -553,8 +553,6 @@
 
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c3fb80c..34b3aac 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -700,8 +700,8 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
 	"bank_intlv=cs0_cs1;"					\
-	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
-	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
@@ -745,8 +745,6 @@
 
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 5f0c4fb..a435f29 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -144,61 +144,106 @@
 #define CONFIG_SYS_L2_SIZE	(512 << 10)
 #endif
 
-#if CONFIG_SYS_L2_SIZE >= (512 << 10)
-/* must be 32-bit */
-#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#endif
-
 #ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x18000
+#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW         /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x18000
+#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_NAND
 #define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
-
-#define CONFIG_SPL_TEXT_BASE		0xfffff000
+#define CONFIG_SPL_TEXT_BASE		0xff800000
 #define CONFIG_SPL_MAX_SIZE		4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
 
-#ifdef CONFIG_SYS_INIT_L2_ADDR
-/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
-#define CONFIG_SYS_TEXT_BASE		0xf8f82000
-#define CONFIG_SPL_RELOC_TEXT_BASE	\
-	(CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
-#define CONFIG_SPL_RELOC_STACK		\
-	(CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START	\
-	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE)
-#else
-#define CONFIG_SYS_TEXT_BASE		0x00201000
-#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
-#define CONFIG_SPL_RELOC_STACK		0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
-#endif
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
-#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -526,6 +571,40 @@
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
 #endif
 
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
+#endif
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
@@ -536,7 +615,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
@@ -733,7 +812,7 @@
 /*
  * Environment
  */
-#ifdef CONFIG_RAMBOOT_SPIFLASH
+#ifdef CONFIG_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
@@ -742,15 +821,20 @@
 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#elif defined(CONFIG_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index f5809e5..15a3e8d 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -126,8 +126,8 @@
 	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
 	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
 	unsigned char pll_relock;  /* 46 PLL Relock time */
-	unsigned char Tcasemax;    /* 47 Tcasemax */
-	unsigned char psiTAdram;   /* 48 Thermal Resistance of DRAM Package from
+	unsigned char t_casemax;    /* 47 Tcasemax */
+	unsigned char psi_ta_dram;  /* 48 Thermal Resistance of DRAM Package from
 					 Top (Case) to Ambient (Psi T-A DRAM) */
 	unsigned char dt0_mode;    /* 49 DRAM Case Temperature Rise from Ambient
 					 due to Activate-Precharge/Mode Bits
@@ -153,9 +153,9 @@
 	unsigned char dt7;         /* 57 DRAM Case Temperature Rise from Ambient
 					 due to Bank Interleave Reads with
 					 Auto-Precharge (DT7) */
-	unsigned char psiTApll;    /* 58 Thermal Resistance of PLL Package form
+	unsigned char psi_ta_pll;  /* 58 Thermal Resistance of PLL Package form
 					 Top (Case) to Ambient (Psi T-A PLL) */
-	unsigned char psiTAreg;    /* 59 Thermal Reisitance of Register Package
+	unsigned char psi_ta_reg;    /* 59 Thermal Reisitance of Register Package
 					 from Top (Case) to Ambient
 					 (Psi T-A Register) */
 	unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
@@ -191,41 +191,41 @@
 					     Dividend / Divisor */
 	unsigned char mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
 	unsigned char mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
-	unsigned char tCK_min;         /* 12 SDRAM Minimum Cycle Time */
+	unsigned char tck_min;         /* 12 SDRAM Minimum Cycle Time */
 	unsigned char res_13;          /* 13 Reserved */
 	unsigned char caslat_lsb;      /* 14 CAS Latencies Supported,
 					     Least Significant Byte */
 	unsigned char caslat_msb;      /* 15 CAS Latencies Supported,
 					     Most Significant Byte */
-	unsigned char tAA_min;         /* 16 Min CAS Latency Time */
-	unsigned char tWR_min;         /* 17 Min Write REcovery Time */
-	unsigned char tRCD_min;        /* 18 Min RAS# to CAS# Delay Time */
-	unsigned char tRRD_min;        /* 19 Min Row Active to
+	unsigned char taa_min;         /* 16 Min CAS Latency Time */
+	unsigned char twr_min;         /* 17 Min Write REcovery Time */
+	unsigned char trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
+	unsigned char trrd_min;        /* 19 Min Row Active to
 					     Row Active Delay Time */
-	unsigned char tRP_min;         /* 20 Min Row Precharge Delay Time */
-	unsigned char tRAS_tRC_ext;    /* 21 Upper Nibbles for tRAS and tRC */
-	unsigned char tRAS_min_lsb;    /* 22 Min Active to Precharge
+	unsigned char trp_min;         /* 20 Min Row Precharge Delay Time */
+	unsigned char tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
+	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
 					     Delay Time */
-	unsigned char tRC_min_lsb;     /* 23 Min Active to Active/Refresh
+	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
 					     Delay Time, LSB */
-	unsigned char tRFC_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
-	unsigned char tRFC_min_msb;    /* 25 Min Refresh Recovery Delay Time */
-	unsigned char tWTR_min;        /* 26 Min Internal Write to
+	unsigned char trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
+	unsigned char trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
+	unsigned char twtr_min;        /* 26 Min Internal Write to
 					     Read Command Delay Time */
-	unsigned char tRTP_min;        /* 27 Min Internal Read to Precharge
+	unsigned char trtp_min;        /* 27 Min Internal Read to Precharge
 					     Command Delay Time */
-	unsigned char tFAW_msb;        /* 28 Upper Nibble for tFAW */
-	unsigned char tFAW_min;        /* 29 Min Four Activate Window
+	unsigned char tfaw_msb;        /* 28 Upper Nibble for tFAW */
+	unsigned char tfaw_min;        /* 29 Min Four Activate Window
 					     Delay Time*/
 	unsigned char opt_features;    /* 30 SDRAM Optional Features */
 	unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
 	unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
 	unsigned char device_type;     /* 33 SDRAM device type */
-	int8_t fine_tCK_min;	       /* 34 Fine offset for tCKmin */
-	int8_t fine_tAA_min;	       /* 35 Fine offset for tAAmin */
-	int8_t fine_tRCD_min;	       /* 36 Fine offset for tRCDmin */
-	int8_t fine_tRP_min;	       /* 37 Fine offset for tRPmin */
-	int8_t fine_tRC_min;	       /* 38 Fine offset for tRCmin */
+	int8_t fine_tck_min;	       /* 34 Fine offset for tCKmin */
+	int8_t fine_taa_min;	       /* 35 Fine offset for tAAmin */
+	int8_t fine_trcd_min;	       /* 36 Fine offset for tRCDmin */
+	int8_t fine_trp_min;	       /* 37 Fine offset for tRPmin */
+	int8_t fine_trc_min;	       /* 38 Fine offset for tRCmin */
 	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
 
 	/* Module-Specific Section: Bytes 60-116 */
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 90562dc..114bb8c 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -149,5 +149,9 @@
 int fm_info_get_phy_address(enum fm_port port);
 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
 void fm_disable_port(enum fm_port port);
+void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
+		unsigned int port_num, int phy_base_addr);
+int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
+		unsigned int port_num, unsigned regnum);
 
 #endif
diff --git a/include/pci.h b/include/pci.h
index 911ba89..d462479 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -410,6 +410,9 @@
 #define PCI_MAX_PCI_DEVICES	32
 #define PCI_MAX_PCI_FUNCTIONS	8
 
+#define PCI_FIND_CAP_TTL 0x48
+#define CAP_START_POS 0x40
+
 /* Include the ID list */
 
 #include <pci_ids.h>
@@ -647,6 +650,13 @@
 				  pci_addr_t mem,
 				  unsigned long command);
 
+extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
+				    int cap);
+extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
+				   u8 hdr_type);
+extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
+			int cap);
+
 const char * pci_class_str(u8 class);
 int pci_last_busno(void);