tree 06594f6ab1563c4990518d9fa8ce23b6a8a802e3
parent 8318e894663f8c897e3c1ab00e1e7fe3c8223317
author Lukas Auer <lukas.auer@aisec.fraunhofer.de> 1546562249 +0100
committer Andes <uboot@andestech.com> 1547516191 +0800

riscv: move the AX25-specific implementation of flush_dcache_all

The fence instruction is used to enforce device I/O and memory ordering
constraints in RISC-V. It can not be relied on to directly affect the
data cache on every CPU.
Andes' AX25 does not have a coherence agent. Its fence instruction
flushes the data cache and is used to keep data in the system coherent.
The implementation of flush_dcache_all in lib/cache.c is therefore
specific to the AX25. Move it into the AX25-specific cache.c in
cpu/ax25/.

This also adds a missing new line between flush_dcache_all and
flush_dcache_range in lib/cache.c.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>