rockchip: rk3036: clean mask definition for grf reg
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 8d42584..9215d6c 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -26,19 +26,19 @@
{
switch (pwm_id) {
case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT,
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
GPIO0D2_PWM0 << GPIO0D2_SHIFT);
break;
case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT,
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK,
GPIO0A0_PWM1 << GPIO0A0_SHIFT);
break;
case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT,
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK,
GPIO0A1_PWM2 << GPIO0A1_SHIFT);
break;
case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT,
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK,
GPIO0D3_PWM3 << GPIO0D3_SHIFT);
break;
default:
@@ -52,23 +52,20 @@
switch (i2c_id) {
case PERIPH_ID_I2C0:
rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A1_MASK << GPIO0A1_SHIFT |
- GPIO0A0_MASK << GPIO0A0_SHIFT,
+ GPIO0A1_MASK | GPIO0A0_MASK,
GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
break;
case PERIPH_ID_I2C1:
rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A3_MASK << GPIO0A3_SHIFT |
- GPIO0A2_MASK << GPIO0A2_SHIFT,
+ GPIO0A3_MASK | GPIO0A2_MASK,
GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
break;
case PERIPH_ID_I2C2:
rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C5_MASK << GPIO2C5_SHIFT |
- GPIO2C4_MASK << GPIO2C4_SHIFT,
+ GPIO2C5_MASK | GPIO2C4_MASK,
GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
@@ -80,24 +77,20 @@
{
switch (cs) {
case 0:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D6_MASK << GPIO1D6_SHIFT,
+ rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK,
GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
break;
case 1:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D7_MASK << GPIO1D7_SHIFT,
+ rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK,
GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
break;
}
rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D5_MASK << GPIO1D5_SHIFT |
- GPIO1D4_MASK << GPIO1D4_SHIFT,
+ GPIO1D5_MASK | GPIO1D4_MASK,
GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A0_MASK << GPIO2A0_SHIFT,
+ rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK,
GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
}
@@ -106,10 +99,8 @@
switch (uart_id) {
case PERIPH_ID_UART0:
rk_clrsetreg(&grf->gpio0c_iomux,
- GPIO0C3_MASK << GPIO0C3_SHIFT |
- GPIO0C2_MASK << GPIO0C2_SHIFT |
- GPIO0C1_MASK << GPIO0C1_SHIFT |
- GPIO0C0_MASK << GPIO0C0_SHIFT,
+ GPIO0C3_MASK | GPIO0C2_MASK |
+ GPIO0C1_MASK | GPIO0C0_MASK,
GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
@@ -117,15 +108,13 @@
break;
case PERIPH_ID_UART1:
rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C7_MASK << GPIO2C7_SHIFT |
- GPIO2C6_MASK << GPIO2C6_SHIFT,
+ GPIO2C7_MASK | GPIO2C6_MASK,
GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
break;
case PERIPH_ID_UART2:
rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C3_MASK << GPIO1C3_SHIFT |
- GPIO1C2_MASK << GPIO1C2_SHIFT,
+ GPIO1C3_MASK | GPIO1C2_MASK,
GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
break;
@@ -146,8 +135,7 @@
GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A4_MASK << GPIO2A4_SHIFT |
- GPIO2A1_MASK << GPIO2A1_SHIFT,
+ GPIO2A4_MASK | GPIO2A1_MASK,
GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
break;