tree e1819e3251f887c0e2724be99b82f75512706ece
parent c24db38fe859afc8b88ad40646c165c73b9bd0e6
author Siarhei Siamashka <siarhei.siamashka@gmail.com> 1421637815 +0200
committer Hans de Goede <hdegoede@redhat.com> 1421926496 +0100

video: ssd2828: Allow using 'pclk' as the PLL clock source

Instead of using the internal 'tx_clk' clock source, it is also
possible to use the pixel clock signal from the parallel LCD
interface ('pclk') as the reference clock for PLL.

The 'tx_clk' clock speed may be different on different boards/devices
(the allowed range is 8MHz - 30MHz). Which is not very convenient,
especially considering the need to know the exact 'tx_clk' clock
speed. This clock speed may be difficult to identify without having
device schematics and/or accurate documentation/sources every time.

Using 'pclk' is free from all these problems.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>