Tegra30: Add common CPU (shared) files
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index c4eb137..aebe29e 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -20,10 +20,14 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+
+/* Tegra AP (Application Processor) code */
+
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clock.h>
#include <asm/arch-tegra/fuse.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
@@ -58,6 +62,12 @@
return TEGRA_SOC_T25;
}
break;
+ case CHIPID_TEGRA30:
+ switch (tegra_sku_id) {
+ case SKU_ID_T30:
+ return TEGRA_SOC_T30;
+ }
+ break;
}
/* unknown sku id */
return TEGRA_SOC_UNKNOWN;
@@ -93,7 +103,7 @@
u32 bct_start, odmdata;
- bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+ bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
return odmdata;
@@ -127,5 +137,5 @@
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* FIXME: should have ap20's L2 disabled too? */
+ /* FIXME: should have SoC's L2 disabled too? */
}
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index b2e10c6..af1879c 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -54,16 +54,37 @@
reg = readl(&pmc->pmc_scratch20);
debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
- /* bits 31:28 in OdmData are used for RAM size */
+#if defined(CONFIG_TEGRA20)
+ /* bits 30:28 in OdmData are used for RAM size on T20 */
+ reg &= 0x70000000;
+
switch ((reg) >> 28) {
case 1:
return 0x10000000; /* 256 MB */
+ case 0:
case 2:
default:
return 0x20000000; /* 512 MB */
case 3:
return 0x40000000; /* 1GB */
}
+#else /* Tegra30 */
+ /* bits 31:28 in OdmData are used for RAM size on T30 */
+ switch ((reg) >> 28) {
+ case 0:
+ case 1:
+ default:
+ return 0x10000000; /* 256 MB */
+ case 2:
+ return 0x20000000; /* 512 MB */
+ case 3:
+ return 0x30000000; /* 768 MB */
+ case 4:
+ return 0x40000000; /* 1GB */
+ case 8:
+ return 0x7ff00000; /* 2GB - 1MB */
+ }
+#endif
}
int dram_init(void)
@@ -82,19 +103,27 @@
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int uart_configs[] = {
-#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA20)
+ #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA_UARTA_GPU)
+ #elif defined(CONFIG_TEGRA_UARTA_GPU)
FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
+ #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
-#else
+ #else
FUNCMUX_UART1_IRRX_IRTX,
-#endif
+ #endif
FUNCMUX_UART2_IRDA,
-1,
FUNCMUX_UART4_GMC,
-1,
+#else /* Tegra30 */
+ FUNCMUX_UART1_ULPI, /* UARTA */
+ -1,
+ -1,
+ -1,
+ -1,
+#endif
};
/**
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
index 1a0bb56..4632f15 100644
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ b/arch/arm/cpu/tegra-common/sys_info.c
@@ -22,12 +22,26 @@
*/
#include <common.h>
+#include <linux/ctype.h>
#ifdef CONFIG_DISPLAY_CPUINFO
+void upstring(char *s)
+{
+ while (*s) {
+ *s = toupper(*s);
+ s++;
+ }
+}
+
/* Print CPU information */
int print_cpuinfo(void)
{
- puts("TEGRA20\n");
+ char soc_name[10];
+
+ strncpy(soc_name, CONFIG_SYS_SOC, 10);
+ upstring(soc_name);
+ puts(soc_name);
+ puts("\n");
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;