riscv: Split SiFive CLINT support between SPL and U-Boot proper
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 198e36e..6f73bdd 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -8,7 +8,8 @@
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply SIFIVE_CLINT if RISCV_MMODE
+ imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI