diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index 7dcc949..380d7af 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -129,9 +129,9 @@
 	/* BCR - Bus Configuration Register (4-25) */
 #if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
 	if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
-		immr->im_siu_conf.sc_bcr = CFG_BCR_60x;
+		immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010);
 	} else {
-		immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE;
+		immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010);
 	}
 #else
 	immr->im_siu_conf.sc_bcr = CFG_BCR;
@@ -141,9 +141,9 @@
 #if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
 	cpu_clk = board_get_cpu_clk_f ();
 	if (cpu_clk >= 100000000) {
-		immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH;
+		immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000);
 	} else {
-		immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW;
+		immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000);
 	}
 #else
 	immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index 1edd6fb..75c6ab2 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -275,22 +275,7 @@
 				  | SIUMCR_BCTLC00
 				  | SIUMCR_MMR11;
 #elif defined(CONFIG_TQM8272)
-#if 0
-	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
-						~SIUMCR_LBPC11 &
-						~SIUMCR_CS10PC11 &
-						~SIUMCR_LBPC11) |
-					SIUMCR_LBPC01 |
-					SIUMCR_CS10PC01 |
-					SIUMCR_APPC10;
-#else
-#if 0
-	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
-					SIUMCR_APPC10);
-#else
-	immap->im_siu_conf.sc_siumcr = 0x88000000;
-#endif
-#endif
+/* nothing to do for this Board here */
 #else
 	/*
 	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -304,7 +289,6 @@
 					SIUMCR_CS10PC01 |
 					SIUMCR_APPC10;
 #endif
-printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
 
 	/* Make PCI lowest priority */
 	/* Each 4 bits is a device bus request	and the MS 4bits