arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
Add device trees describing possible uses of mezzanine cards depending
on the SERDES protocol employed.
This patch adds DPAA2 networking support for the following protocols on
each SERDES block:
* SD #1: 3, 7, 19, 20
* SD #2: 11
Each SERDES block has a different device tree file per protocol
supported, where the IO SLOTs used are enabled and PHYs located on the
mezzanine cards are described. Also, dpmac nodes are edited and their
associated phy-connection-type and phy-handle are added.
Top DTS files are also added for each combination of protocol on the 3
SERDES blocks.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
new file mode 100644
index 0000000..cf09f98
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11
+ *
+ * Some assumptions are made:
+ * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
+ * (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac12 {
+ status = "okay";
+ phy-handle = <&sgmii_phy7_2>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac17 {
+ status = "okay";
+ phy-handle = <&sgmii_phy7_3>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac18 {
+ status = "okay";
+ phy-handle = <&sgmii_phy7_4>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac16 {
+ status = "okay";
+ phy-handle = <&sgmii_phy8_2>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac13 {
+ status = "okay";
+ phy-handle = <&sgmii_phy8_3>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac14 {
+ status = "okay";
+ phy-handle = <&sgmii_phy8_4>;
+ phy-connection-type = "sgmii";
+};
+
+&emdio1_slot7 {
+ sgmii_phy7_2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy7_3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy7_4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+&emdio1_slot8 {
+ sgmii_phy8_2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy8_3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy8_4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};