License cleanup: Fix license header for some esd display configurations
These files were autogenerated by EPSON configuration tools.
This patch replaces the autogenerated file headers by the GPL
license notice.
This change is done with the explicit permission
of Epson Research & Development / IC Software Development.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h
index 60843ac..634889a 100644
--- a/board/esd/common/s1d13705_320_240_8bpp.h
+++ b/board/esd/common/s1d13705_320_240_8bpp.h
@@ -1,19 +1,26 @@
/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
*
- * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * See file CREDITS for list of people who contributed to this
+ * project.
*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- * All rights reserved.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
*
- * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*
- * This file defines the configuration environment and registers,
- * which can be used by any software, such as display drivers.
- *
- * PLEASE NOTE: If you FTP this file to a non-Windows platform, make
- * sure you transfer this file using ASCII, not BINARY
- * mode.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*
+ * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
*/
static S1D_REGS regs_13705_320_240_8bpp[] =