diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index ec27bda..7b4eefd 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -35,6 +35,7 @@
 #include <libfdt.h>
 #endif
 
+#include "../common/common.h"
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 #include <i2c.h>
 
@@ -421,7 +422,6 @@
 
 	return ((val & SCL_BIT) == SCL_BIT);
 }
-
 #endif
 
 #if !defined(CONFIG_KMETER1)
@@ -500,7 +500,7 @@
 	out_8 (&dev->cr, (I2C_CR_MEN));
 
 #else
-#if defined(CONFIG_HARD_I2C)
+#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3)
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 
@@ -578,10 +578,12 @@
 }
 #endif
 
+#if !defined(CONFIG_MACH_SUEN3)
 int ethernet_present (void)
 {
 	return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
 }
+#endif
 
 int board_eth_init (bd_t *bis)
 {
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
new file mode 100644
index 0000000..fffc6a3
--- /dev/null
+++ b/board/keymile/km_arm/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/keymile/km_arm/config.mk b/board/keymile/km_arm/config.mk
new file mode 100644
index 0000000..b9e81b2
--- /dev/null
+++ b/board/keymile/km_arm/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x004000000
+
+# Kirkwood Boot Image configuration file
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
new file mode 100644
index 0000000..53cf474
--- /dev/null
+++ b/board/keymile/km_arm/km_arm.c
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <nand.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int	io_dev;
+extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
+
+/* Multi-Purpose Pins Functionality configuration */
+u32 kwmpp_config[] = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP6_SYSRST_OUTn,
+	MPP7_PEX_RST_OUTn,
+#if defined(CONFIG_SOFT_I2C)
+	MPP8_GPIO,		/* SDA */
+	MPP9_GPIO,		/* SCL */
+#endif
+#if defined(CONFIG_HARD_I2C)
+	MPP8_TW_SDA,
+	MPP9_TW_SCK,
+#endif
+	MPP10_UART0_TXD,
+	MPP11_UART0_RXD,
+	MPP12_GPO,		/* Reserved */
+	MPP13_UART1_TXD,
+	MPP14_UART1_RXD,
+	MPP15_GPIO,		/* Not used */
+	MPP16_GPIO,		/* Not used */
+	MPP17_GPIO,		/* Reserved */
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+	MPP24_GPIO,
+	MPP25_GPIO,
+	MPP26_GPIO,
+	MPP27_GPIO,
+	MPP28_GPIO,
+	MPP29_GPIO,
+	MPP30_GPIO,
+	MPP31_GPIO,
+	MPP32_GPIO,
+	MPP33_GPIO,
+	MPP34_GPIO,		/* CDL1 (input) */
+	MPP35_GPIO,		/* CDL2 (input) */
+	MPP36_GPIO,		/* MAIN_IRQ (input) */
+	MPP37_GPIO,		/* BOARD_LED */
+	MPP38_GPIO,		/* Piggy3 LED[1] */
+	MPP39_GPIO,		/* Piggy3 LED[2] */
+	MPP40_GPIO,		/* Piggy3 LED[3] */
+	MPP41_GPIO,		/* Piggy3 LED[4] */
+	MPP42_GPIO,		/* Piggy3 LED[5] */
+	MPP43_GPIO,		/* Piggy3 LED[6] */
+	MPP44_GPIO,		/* Piggy3 LED[7] */
+	MPP45_GPIO,		/* Piggy3 LED[8] */
+	MPP46_GPIO,		/* Reserved */
+	MPP47_GPIO,		/* Reserved */
+	MPP48_GPIO,		/* Reserved */
+	MPP49_GPIO,		/* SW_INTOUTn */
+	0
+};
+
+int ethernet_present(void)
+{
+	uchar	buf;
+	int	ret = 0;
+
+	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
+		printf ("%s: Error reading Boco\n", __FUNCTION__);
+		return -1;
+	}
+	if ((buf & 0x40) == 0x40) {
+		ret = 1;
+	}
+	return ret;
+}
+
+int misc_init_r(void)
+{
+	I2C_MUX_DEVICE	*i2cdev;
+	char *str;
+	int mach_type;
+
+	/* add I2C Bus for I/O Expander */
+	i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
+	io_dev = i2cdev->busid;
+	puts("Piggy:");
+	if (ethernet_present() == 0)
+		puts (" not");
+	puts(" present\n");
+
+	str = getenv("mach_type");
+	if (str != NULL) {
+		mach_type = simple_strtoul(str, NULL, 10);
+		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
+		gd->bd->bi_arch_number = mach_type;
+	}
+	return 0;
+}
+
+int board_init(void)
+{
+	u32 tmp;
+
+	kirkwood_mpp_conf(kwmpp_config);
+
+	/*
+	 * The FLASH_GPIO_PIN switches between using a
+	 * NAND or a SPI FLASH. Set this pin on start
+	 * to NAND mode.
+	 */
+	tmp = readl(KW_GPIO0_BASE);
+	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+	tmp = readl(KW_GPIO0_BASE + 4);
+	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+	printf("KM: setting NAND mode\n");
+
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+#if defined(CONFIG_SOFT_I2C)
+	/* init the GPIO for I2C Bitbang driver */
+	kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
+	kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
+	kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
+	kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
+#endif
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	kw_gpio_set_valid(SUEN3_ENV_WP, 38);
+	kw_gpio_direction_output(SUEN3_ENV_WP, 1);
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_CMD_SF)
+int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 tmp;
+	if (argc < 2) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if ((strcmp(argv[1], "off") == 0)) {
+		printf("SPI FLASH disabled, NAND enabled\n");
+		/* Multi-Purpose Pins Functionality configuration */
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+
+		kirkwood_mpp_conf(kwmpp_config);
+		tmp = readl(KW_GPIO0_BASE);
+		writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+	} else if ((strcmp(argv[1], "on") == 0)) {
+		printf("SPI FLASH enabled, NAND disabled\n");
+		/* Multi-Purpose Pins Functionality configuration */
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;
+
+		kirkwood_mpp_conf(kwmpp_config);
+		tmp = readl(KW_GPIO0_BASE);
+		writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
+	} else {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	spitoggle,	2,	0,	do_spi_toggle,
+	"En-/disable SPI FLASH access",
+	"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
+	);
+#endif
+
+int dram_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
+						       kw_sdram_bs(i));
+	}
+	return 0;
+}
+
+/* Configure and enable MV88E1118 PHY */
+void reset_phy(void)
+{
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* reset the phy */
+	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store (ulong a)
+{
+	volatile ulong *save_addr;
+	volatile ulong size = 0;
+	int i;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		size += gd->bd->bi_dram[i].size;
+	}
+	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+	writel(a, save_addr);
+	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
+}
+
+ulong bootcount_load (void)
+{
+	volatile ulong *save_addr;
+	volatile ulong size = 0;
+	int i;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		size += gd->bd->bi_dram[i].size;
+	}
+	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+	if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
+		return 0;
+	else
+		return readl(save_addr);
+}
+#endif
+
+#if defined(CONFIG_SOFT_I2C)
+void set_sda (int state)
+{
+	I2C_ACTIVE;
+	I2C_SDA(state);
+}
+
+void set_scl (int state)
+{
+	I2C_SCL(state);
+}
+
+int get_sda (void)
+{
+	I2C_TRISTATE;
+	return I2C_READ;
+}
+
+int get_scl (void)
+{
+	return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	kw_gpio_set_value(SUEN3_ENV_WP, !state);
+
+	return !kw_gpio_get_value(SUEN3_ENV_WP);
+}
+#endif
diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
new file mode 100644
index 0000000..d6edd27
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -0,0 +1,176 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01111111	# MPP Control 0 Register
+# bit 3-0:   MPPSel0	1, NF_IO[2]
+# bit 7-4:   MPPSel1	1, NF_IO[3]
+# bit 12-8:  MPPSel2	1, NF_IO[4]
+# bit 15-12: MPPSel3	1, NF_IO[5]
+# bit 19-16: MPPSel4	1, NF_IO[6]
+# bit 23-20: MPPSel5	1, NF_IO[7]
+# bit 27-24: MPPSel6	1, SYSRST_O
+# bit 31-28: MPPSel7	0, GPO[7]
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   MPPSel16	0, GPIO[16]
+# bit 7-4:   MPPSel17	0, GPIO[17]
+# bit 12-8:  MPPSel18	1, NF_IO[0]
+# bit 15-12: MPPSel19	1, NF_IO[1]
+# bit 19-16: MPPSel20	0, GPIO[20]
+# bit 23-20: MPPSel21	0, GPIO[21]
+# bit 27-24: MPPSel22	0, GPIO[22]
+# bit 31-28: MPPSel23	0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+DATA 0xFFD20134 0xBBBBBBBB	# L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x00BBBBBB	# L2 RAM Timing 1 Register
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+#Dram initalization
+DATA 0xFFD01400 0x43000400	# SDRAM Configuration Register
+# bit13-0:  0x400 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x36343000	# DDR Controller Control Low
+		0x38543000
+# bit 3-0:  0 reserved
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302544B	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000032	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000642	#  DDR Mode
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    1,  DDR ODT control lsd disabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  0  , no sample stage
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00000000	#  DDR ODT Control (Low)
+# bit3-0:  0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E90F	# CPU ODT Control
+# bit3-0:  F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit9-8:  1, ODTEn, never active
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0