Origen: Select SCLKMPLL as FIMD0 parent clock
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index d949ad2..94cccca 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -56,6 +56,8 @@
#define CLK_SRC_PERIL0_OFFSET 0xC250
#define CLK_DIV_PERIL0_OFFSET 0xC550
+#define CLK_SRC_LCD0_OFFSET 0xC234
+
#define APLL_LOCK_OFFSET 0x14000
#define MPLL_LOCK_OFFSET 0x14008
#define APLL_CON0_OFFSET 0x14100
@@ -351,6 +353,16 @@
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
+/* CLK_SRC_LCD0 */
+#define FIMD_SEL_SCLKMPLL 6
+#define MDNIE0_SEL_XUSBXTI 1
+#define MDNIE_PWM0_SEL_XUSBXTI 1
+#define MIPI0_SEL_XUSBXTI 1
+#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
+ | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
+ | (MDNIE0_SEL_XUSBXTI << 4) \
+ | (FIMD_SEL_SCLKMPLL << 0))
+
/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x1C20