sunxi: move Cortex SMPEN setting into start.S
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.
This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR
very early in start.S, and moves sunxi boards over to use that instead
of the custom code we had in our board.c file (where it was called
technically too late).
In practice we got away with this so far, because at this point all the
other cores were still in reset, so any broadcasting would have been
ignored anyway. But it is architecturally cleaner to do it early, and
we move a core specific piece of code out of board.c.
This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few
years back, and moves the respective logic into the new Kconfig entry.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 60bb0a9..2eeef3c 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -76,4 +76,9 @@
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config SPL_ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
+
endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 698e15b..af87a54 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -173,6 +173,17 @@
*
*************************************************************************/
ENTRY(cpu_init_cp15)
+
+#if CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN)
+ /*
+ * The Arm Cortex-A7 TRM says this bit must be enabled before
+ * "any cache or TLB maintenance operations are performed".
+ */
+ mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
+ orr r0, r0, #1 << 6 @ set SMP bit to enable coherency
+ mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register
+#endif
+
/*
* Invalidate L1 I/D
*/