Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
powerpc/8xxx: Remove dependency on <usb.h>
powerpc/85xx: enable USB2 gadget mode for corenet ds board
powerpc/85xx: verify the device tree before booting Linux
MPC8xxx: drop redundant boot messages
powerpc/85xx: Fix build failure for P1023RDS
powerpc/p2041rdb: Enable SATA support
powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500
powerpc/85xx: Fix up clock_freq property in CAN node of dts
85xx: enable FDT support for STX SSA board
powerpc/85xx: provide 85xx flush_icache for cmd_cache
powerpc/p2041rdb: Enable backside L2 cache support
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
powerpc/85xx: Add support for P2041[e] XAUI in SERDES
powerpc/85xx: Rename P2040 id & SERDES to P2041
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access
powerpc/85xx: Fix setting of EPAPR_MAGIC value
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 8a0a8e9..7026bca 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -78,8 +78,8 @@
COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o
-COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
+COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
@@ -111,7 +111,7 @@
COBJS-$(CONFIG_P1025) += p1021_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ce59c25..22fa461 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -46,7 +46,6 @@
{
sys_info_t sysinfo;
uint pvr, svr;
- uint fam;
uint ver;
uint major, minor;
struct cpu_type *cpu;
@@ -94,30 +93,25 @@
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
- fam = PVR_FAM(pvr);
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
printf("Core: ");
- if (PVR_FAM(PVR_85xx)) {
- switch(PVR_MEM(pvr)) {
- case 0x1:
- case 0x2:
- puts("E500");
- break;
- case 0x3:
- puts("E500MC");
- break;
- case 0x4:
- puts("E5500");
- break;
- default:
- puts("Unknown");
- break;
- }
- } else {
+ switch(ver) {
+ case PVR_VER_E500_V1:
+ case PVR_VER_E500_V2:
+ puts("E500");
+ break;
+ case PVR_VER_E500MC:
+ puts("E500MC");
+ break;
+ case PVR_VER_E5500:
+ puts("E5500");
+ break;
+ default:
puts("Unknown");
+ break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
@@ -358,7 +352,7 @@
lbc_sdram_init();
#endif
- puts("DDR: ");
+ debug("DDR: ");
return dram_size;
}
#endif /* CONFIG_SYS_RAMBOOT */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b3da970..6aca166 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -222,6 +222,10 @@
void cpu_init_f (void)
{
extern void m8560_cpm_reset (void);
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
@@ -262,6 +266,13 @@
/* Invalidate the CPC before DDR gets enabled */
invalidate_cpc();
+
+ #ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* set DCSRCR so that DCSR space is 1G */
+ setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
+ in_be32(&gur->dcsrcr);
+#endif
+
}
/* Implement a dummy function for those platforms w/o SERDES */
@@ -381,6 +392,12 @@
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+ if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+ (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+ puts("N/A\n");
+ goto skip_l2;
+ }
+
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */
@@ -401,6 +418,8 @@
;
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
}
+
+skip_l2:
#else
puts("disabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 812bb3f..8f13cd8 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -228,6 +228,12 @@
u32 *ph;
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
u32 size, line_size, num_ways, num_sets;
+ int has_l2 = 1;
+
+ /* P2040/P2040E has no L2, so dont set any L2 props */
+ if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+ (SVR_SOC_VER(get_svr()) == SVR_P2040_E))
+ has_l2 = 0;
size = (l2cfg0 & 0x3fff) * 64 * 1024;
num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
@@ -250,21 +256,22 @@
goto next;
}
+ if (has_l2) {
#ifdef CONFIG_SYS_CACHE_STASHING
- {
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
if (reg)
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
- }
#endif
- fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
- fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
- fdt_setprop_cell(blob, l2_off, "cache-size", size);
- fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
- fdt_setprop_cell(blob, l2_off, "cache-level", 2);
- fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
+ fdt_setprop_cell(blob, l2_off, "cache-block-size",
+ line_size);
+ fdt_setprop_cell(blob, l2_off, "cache-size", size);
+ fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
+ fdt_setprop_cell(blob, l2_off, "cache-level", 2);
+ fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+ }
if (l3_off < 0) {
ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
@@ -628,4 +635,79 @@
*/
do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
"timer-frequency", gd->bus_clk/2, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
+ "clock_freq", gd->bus_clk, 1);
+}
+
+/*
+ * For some CCSR devices, we only have the virtual address, not the physical
+ * address. This is because we map CCSR as a whole, so we typically don't need
+ * a macro for the physical address of any device within CCSR. In this case,
+ * we calculate the physical address of that device using it's the difference
+ * between the virtual address of the device and the virtual address of the
+ * beginning of CCSR.
+ */
+#define CCSR_VIRT_TO_PHYS(x) \
+ (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+
+/*
+ * Verify the device tree
+ *
+ * This function compares several CONFIG_xxx macros that contain physical
+ * addresses with the corresponding nodes in the device tree, to see if
+ * the physical addresses are all correct. For example, if
+ * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
+ * of the first UART. We convert this to a physical address and compare
+ * that with the physical address of the first ns16550-compatible node
+ * in the device tree. If they don't match, then we display a warning.
+ *
+ * Returns 1 on success, 0 on failure
+ */
+int ft_verify_fdt(void *fdt)
+{
+ uint64_t ccsr = 0;
+ int aliases;
+ int off;
+
+ /* First check the CCSR base address */
+ off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
+ if (off > 0)
+ ccsr = fdt_get_base_address(fdt, off);
+
+ if (!ccsr) {
+ printf("Warning: could not determine base CCSR address in "
+ "device tree\n");
+ /* No point in checking anything else */
+ return 0;
+ }
+
+ if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) {
+ printf("Warning: U-Boot configured CCSR at address %llx,\n"
+ "but the device tree has it at %llx\n",
+ (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr);
+ /* No point in checking anything else */
+ return 0;
+ }
+
+ /*
+ * Get the 'aliases' node. If there isn't one, then there's nothing
+ * left to do.
+ */
+ aliases = fdt_path_offset(fdt, "/aliases");
+ if (aliases > 0) {
+#ifdef CONFIG_SYS_NS16550_COM1
+ if (!fdt_verify_alias_address(fdt, aliases, "serial0",
+ CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
+ return 0;
+#endif
+
+#ifdef CONFIG_SYS_NS16550_COM2
+ if (!fdt_verify_alias_address(fdt, aliases, "serial1",
+ CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
+ return 0;
+#endif
+ }
+
+ return 1;
}
diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
similarity index 100%
rename from arch/powerpc/cpu/mpc85xx/p2040_ids.c
rename to arch/powerpc/cpu/mpc85xx/p2041_ids.c
diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
similarity index 83%
rename from arch/powerpc/cpu/mpc85xx/p2040_serdes.c
rename to arch/powerpc/cpu/mpc85xx/p2041_serdes.c
index 83bc82f..f68f281 100644
--- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
@@ -37,8 +37,8 @@
PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
SATA2, NONE, NONE, NONE, NONE, },
[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
- PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
- NONE, NONE, NONE, NONE, NONE, NONE, },
+ PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
PCIE3, NONE, NONE, NONE, NONE, },
@@ -53,8 +53,8 @@
SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
NONE, NONE, NONE, },
[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
- NONE, NONE, NONE, NONE, NONE, },
+ SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, NONE, NONE, NONE, NONE, },
[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
@@ -68,19 +68,35 @@
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
{
+ enum srds_prtcl prtcl;
+ u32 svr = get_svr();
+ u32 ver = SVR_SOC_VER(svr);
+
if (!serdes_lane_enabled(lane))
return NONE;
+ prtcl = serdes_cfg_tbl[cfg][lane];
+
- return serdes_cfg_tbl[cfg][lane];
+ /* P2040[e] does not support XAUI */
+ if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+ prtcl = NONE;
+
+ return prtcl;
}
int is_serdes_prtcl_valid(u32 prtcl)
{
int i;
+ u32 svr = get_svr();
+ u32 ver = SVR_SOC_VER(svr);
if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
return 0;
+ /* P2040[e] does not support XAUI */
+ if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+ return 0;
+
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 56a853e..6678ed4 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@@ -144,6 +144,18 @@
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
+ /* skip L2 setup on P2040/P2040E as they have no L2 */
+ mfspr r2,SPRN_SVR
+ lis r3,SVR_P2040@h
+ ori r3,r3,SVR_P2040@l
+ cmpw r2,r3
+ beq 3f
+
+ lis r3,SVR_P2040_E@h
+ ori r3,r3,SVR_P2040_E@l
+ cmpw r2,r3
+ beq 3f
+
/* Enable/invalidate the L2 cache */
msync
lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
@@ -169,6 +181,7 @@
andis. r1,r3,L2CSR0_L2E@h
beq 2b
#endif
+3:
#define EPAPR_MAGIC (0x45504150)
#define ENTRY_ADDR_UPPER 0
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 626ccce..878a3d6 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -676,6 +676,8 @@
/* Cache functions.
*/
+.globl flush_icache
+flush_icache:
.globl invalidate_icache
invalidate_icache:
mfspr r0,L1CSR1
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index d9e3e7e..285051d 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -30,9 +30,8 @@
#include <asm/fsl_serdes.h>
#include <phy.h>
#include <hwconfig.h>
-#ifdef CONFIG_HAS_FSL_DR_USB
-#include <usb.h>
-#endif
+
+#define FSL_MAX_NUM_USB_CTRLS 2
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -135,7 +134,7 @@
char str[5];
int i, j;
- for (i = 1; i <= USB_MAX_DEVICE; i++) {
+ for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) {
int mode_idx = -1, phy_idx = -1;
sprintf(str, "%s%d", "usb", i);
if (hwconfig(str)) {
@@ -163,8 +162,6 @@
usb1_defined = 1;
if (mode_idx < 0 && phy_idx < 0)
printf("WARNING: invalid phy or mode\n");
- } else {
- break;
}
}
if (!usb1_defined) {
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 267a940..6aaade0 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1759,7 +1759,8 @@
u32 cgencrl; /* Core general control */
u8 res31[184];
u32 sriopstecr; /* SRIO prescaler timer enable control */
- u8 res32[1788];
+ u32 dcsrcr; /* DCSR Control register */
+ u8 res32[1784];
u32 pmuxcr; /* Pin multiplexing control */
u8 res33[60];
u32 iovselsr; /* I/O voltage selection status */
@@ -1772,6 +1773,10 @@
u8 res37[380];
} ccsr_gur_t;
+#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
+#define FSL_CORENET_DCSR_SZ_4M 0x0
+#define FSL_CORENET_DCSR_SZ_1G 0x3
+
/*
* On p4080 we have an LIODN for msg unit (rmu) but not maintenance
* everything after has RMan thus msg unit LIODN is used for maintenance
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 9c4651a..0c4cc25 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -938,6 +938,10 @@
#define PVR_85xx 0x80200000
#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
+#define PVR_VER_E500_V1 0x8020
+#define PVR_VER_E500_V2 0x8021
+#define PVR_VER_E500MC 0x8023
+#define PVR_VER_E5500 0x8024
#define PVR_86xx 0x80040000
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 4e0cb8f..1375474 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -87,7 +87,7 @@
* r8: 0
* r9: 0
*/
-#if defined(CONFIG_85xx) || defined(CONFIG_440)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
#define EPAPR_MAGIC (0x45504150)
#else
#define EPAPR_MAGIC (0x65504150)
@@ -226,6 +226,24 @@
return ret;
}
+/*
+ * Verify the device tree.
+ *
+ * This function is called after all device tree fix-ups have been enacted,
+ * so that the final device tree can be verified. The definition of "verified"
+ * is up to the specific implementation. However, it generally means that the
+ * addresses of some of the devices in the device tree are compared with the
+ * actual addresses at which U-Boot has placed them.
+ *
+ * Returns 1 on success, 0 on failure. If 0 is returned, U-boot will halt the
+ * boot process.
+ */
+static int __ft_verify_fdt(void *fdt)
+{
+ return 1;
+}
+__attribute__((weak, alias("__ft_verify_fdt"))) int ft_verify_fdt(void *fdt);
+
static int boot_body_linux(bootm_headers_t *images)
{
ulong rd_len;
@@ -298,6 +316,9 @@
/* fixup the initrd now that we know where it should be */
if (*initrd_start && *initrd_end)
fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+ if (!ft_verify_fdt(*of_flat_tree))
+ return -1;
}
#endif /* CONFIG_OF_LIBFDT */
return 0;
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index cf9b7b8..b1e7823 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -236,6 +236,7 @@
#endif
fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
}
int board_eth_init(bd_t *bis)
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index a184592..b937015 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -256,6 +256,6 @@
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c
index dd6f6f7..58f23c5 100644
--- a/board/freescale/corenet_ds/law.c
+++ b/board/freescale/corenet_ds/law.c
@@ -37,7 +37,8 @@
#endif
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 4e4b7c0..8aceddb 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -145,7 +145,7 @@
setup_ddr_bat(dram_size);
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index e3916fc..455569e 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -69,7 +69,7 @@
setup_ddr_bat(dram_size);
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index 46de910..e9c699c 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -110,6 +110,6 @@
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+ debug(" DDR: ");
return dram_size;
}
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index dd58541..bed8f53 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -63,7 +63,7 @@
dram_size = fixed_sdram ();
#endif
- puts (" DDR: ");
+ debug (" DDR: ");
return dram_size;
}
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index 83ffcd2..3077eb3 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -34,6 +34,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
@@ -247,6 +248,13 @@
#endif
}
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup (blob, bd);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
int
board_early_init_f(void)
{
diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h
index 4f14a02..95f3a2c 100644
--- a/include/configs/P1023RDS.h
+++ b/include/configs/P1023RDS.h
@@ -536,16 +536,16 @@
#define CONFIG_FMAN_ENET
#endif
+#define CONFIG_SYS_FMAN_FW
#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
-#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
#else
#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
-#define CONFIG_SYS_FMAN_FW_ADDR 0x10000000
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
#endif
+#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 2beb357..638dbe7 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -108,6 +108,8 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS
@@ -452,6 +454,26 @@
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 0b7becb..adf9906 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -595,6 +595,7 @@
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_MMC
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index d5dd94f..141da26 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -43,7 +43,7 @@
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#define CONFIG_MPC8560 1
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
@@ -194,6 +194,11 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
/*
* I2C
*/