tree d3d2c0f2060c1a04e1ad9020c0bcd8be49c29958
parent 111bc5949e3bccaf81cc92cd47902b16b99c7c19
author Chen-Yu Tsai <wens@csie.org> 1480496074 +0800
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1492687801 +0200

sunxi: Set PLL lock enable bits for R40

According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.

This patch enables it for all the PLLs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>