tree c0ecd11723228a17348918bc330e0ec1b8063d11
parent 213b9ba4493891619482a75ccaca93133ea35225
author Jagan Teki <jagan@amarulasolutions.com> 1563278232 +0530
committer Kever Yang <kever.yang@rock-chips.com> 1563638384 +0800

ram: rk3399: Don't wait for PLL lock in lpddr4

lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.

So no need to wait explicitly during pctl config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>