commit 5e8341c264c042a828922212891c55d73114923c
author Fabio Estevam <fabio.estevam@freescale.com> Thu Nov 15 11:23:24 2012 +0000
committer Stefano Babic <sbabic@denx.de> Mon Nov 19 08:49:00 2012 +0100
tree 8bd13629d47da2981d0ff603fdd3b2812c8a94c4
parent 17cd2a851f3dc6c3acbb449de81ffa5ec1e60381

spi: mxc_spi: Fix spi clock glitch durant reset

Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.

Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

drivers/spi/mxc_spi.c

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index b6bad98..859c43f 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -140,8 +140,8 @@
 	reg_ctrl = reg_read(&regs->ctrl);
 
 	/* Reset spi */
-	reg_write(&regs->ctrl, 0);
-	reg_write(&regs->ctrl, (reg_ctrl | 0x1));
+	reg_write(&regs->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
+	reg_write(&regs->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
 
 	/*
 	 * The following computation is taken directly from Freescale's code.