cache: add sifive private L2 cache driver
This driver is currently responsible for enabling the clock gating
feature of SiFive pre core's private L2 cache.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 6cb8c3e..26c2d80 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -45,4 +45,11 @@
This driver is for SiFive Composable L2/L3 cache. It enables cache
ways of composable cache.
+config SIFIVE_PL2
+ bool "SiFive private L2 cache"
+ select CACHE
+ help
+ This driver is for SiFive Private L2 cache. It configures registers
+ to enable the clock gating feature.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index ad76577..78e673d 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
+obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o
diff --git a/drivers/cache/cache-sifive-pl2.c b/drivers/cache/cache-sifive-pl2.c
new file mode 100644
index 0000000..ae689e1
--- /dev/null
+++ b/drivers/cache/cache-sifive-pl2.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 SiFive
+ */
+
+#include <cache.h>
+#include <dm.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+
+#define SIFIVE_PL2CHICKENBIT_OFFSET 0x1000
+#define SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK BIT(3)
+
+static int sifive_pl2_probe(struct udevice *dev)
+{
+ fdt_addr_t base;
+ u32 val;
+
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Enable regionClockDisable bit */
+ val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
+ writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK,
+ (void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
+
+ return 0;
+}
+
+static const struct udevice_id sifive_pl2_ids[] = {
+ { .compatible = "sifive,pl2cache0" },
+ { .compatible = "sifive,pl2cache1" },
+ {}
+};
+
+U_BOOT_DRIVER(sifive_pl2) = {
+ .name = "sifive_pl2",
+ .id = UCLASS_CACHE,
+ .of_match = sifive_pl2_ids,
+ .probe = sifive_pl2_probe,
+};