tree 87ea425ec314d57771e74a0200c5ad0684329541
parent bc7cb5ff109d41511d18cee7babfc00b82cf78d8
author Zhichun Hua <zhichun.hua@freescale.com> 1435564177 +0800
committer York Sun <yorksun@freescale.com> 1437417880 -0700

armv8: Fix TCR macros for shareability attribute

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>