Merge patch series "include: env: phytec: k3_net: Remove net_apply_extensions"
This series from Daniel Schultz <d.schultz@phytec.de> cleans up the
environment further on the phytec am62ax platforms.
Link: https://lore.kernel.org/r/20250428144904.1058574-1-d.schultz@phytec.de
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 01ab0c1..5e1938b 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@
windows_vm: windows-2022
ubuntu_vm: ubuntu-24.04
macos_vm: macOS-14
- ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250404-10Apr2025
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -90,7 +90,7 @@
steps:
- script: |
set -e
- virtualenv -p /usr/bin/python3 /tmp/venvhtml
+ python3 -m venv /tmp/venvhtml
. /tmp/venvhtml/bin/activate
pip install -r doc/sphinx/requirements.txt
make htmldocs KDOC_WERROR=1
@@ -132,7 +132,7 @@
git config --global user.email bmeng.cn@gmail.com
git config --global --add safe.directory $(work_dir)
export USER=azure
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
@@ -170,7 +170,7 @@
- script: |
git config --global --add safe.directory $(work_dir)
export USER=azure
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
@@ -277,7 +277,7 @@
if [ -n "\${BUILD_ENV}" ]; then
export \${BUILD_ENV};
fi
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
@@ -307,6 +307,13 @@
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
+ # If we have TF-A binaries, we need to use them.
+ if [[ -d /opt/tf-a/"\${TEST_PY_BD}" ]]; then
+ cp /opt/tf-a/"\${TEST_PY_BD}"/fip.bin /opt/tf-a/"\${TEST_PY_BD}"/bl1.bin /tmp;
+ export fip=/tmp/fip.bin;
+ export bl1=/tmp/bl1.bin;
+ export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:\${PATH};
+ fi
export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
# "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
@@ -430,6 +437,12 @@
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
+ vexpress_fvp:
+ TEST_PY_BD: "vexpress_fvp"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
+ vexpress_fvp_bloblist:
+ TEST_PY_BD: "vexpress_fvp_bloblist"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
integratorcp_cm926ejs:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id qemu"
@@ -594,7 +607,7 @@
# make environment variables available as tests are running inside a container
export BUILDMAN="${BUILDMAN}"
git config --global --add safe.directory ${WORK_DIR}
- virtualenv -p /usr/bin/python3 /tmp/venv
+ python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 145bdad..6f11331 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -20,7 +20,7 @@
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250404-10Apr2025
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -57,7 +57,7 @@
export BINMAN_INDIRS=/tmp;
fi
# Prepare python environment
- - virtualenv -p /usr/bin/python3 /tmp/venv;
+ - python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
@@ -96,6 +96,13 @@
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
+ # If we have TF-A binaries, we need to use them.
+ - if [[ -d /opt/tf-a/"${TEST_PY_BD}" ]]; then
+ cp /opt/tf-a/"${TEST_PY_BD}"/fip.bin /opt/tf-a/"${TEST_PY_BD}"/bl1.bin /tmp/;
+ export fip=/tmp/fip.bin;
+ export bl1=/tmp/bl1.bin;
+ export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:${PATH};
+ fi
# "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
@@ -124,7 +131,7 @@
- ${HOST}
script:
# Prepare python environment
- - virtualenv -p /usr/bin/python3 /tmp/venv;
+ - python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt
@@ -155,7 +162,7 @@
docs:
extends: .testsuites
script:
- - virtualenv -p /usr/bin/python3 /tmp/venvhtml
+ - python3 -m venv /tmp/venvhtml
- . /tmp/venvhtml/bin/activate
- pip install -r doc/sphinx/requirements.txt
- make htmldocs KDOC_WERROR=1
@@ -184,7 +191,7 @@
git config --global user.email trini@konsulko.com;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
export USER=gitlab;
- virtualenv -p /usr/bin/python3 /tmp/venv;
+ python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
@@ -210,7 +217,7 @@
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- - virtualenv -p /usr/bin/python3 /tmp/venv
+ - python3 -m venv /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
@@ -515,6 +522,22 @@
TEST_PY_ID: "--id spi-nor_qemu"
<<: *buildman_and_testpy_dfn
+vexpress_fvp test.py:
+ variables:
+ TEST_PY_BD: "vexpress_fvp"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
+ tags:
+ - ${DEFAULT_AMD64_TAG}
+ <<: *buildman_and_testpy_dfn
+
+vexpress_fvp_bloblist test.py:
+ variables:
+ TEST_PY_BD: "vexpress_fvp_bloblist"
+ TEST_PY_TEST_SPEC: "not sleep and not hostfs"
+ tags:
+ - ${DEFAULT_AMD64_TAG}
+ <<: *buildman_and_testpy_dfn
+
xilinx_zynq_virt test.py:
variables:
TEST_PY_BD: "xilinx_zynq_virt"
diff --git a/Makefile b/Makefile
index 7393974..15c7e63 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2025
-PATCHLEVEL = 04
+PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@@ -30,7 +30,7 @@
export HOST_ARCH=$(HOST_ARCH_X86)
else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
export HOST_ARCH=$(HOST_ARCH_AARCH64)
-else ifneq (,$(findstring $(MK_ARCH), "arm" "armv7" "armv7a" "armv7l"))
+else ifneq (,$(findstring $(MK_ARCH), "arm" "armv5tel" "armv6l" "armv7" "armv7a" "armv7l"))
export HOST_ARCH=$(HOST_ARCH_ARM)
else ifeq ("riscv32", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_RISCV32)
@@ -2231,7 +2231,8 @@
itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \
mkimage.rom.mkimage mkimage-in-simple-bin* rom.map simple-bin* \
idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb \
- Test* capsule*.*.efi-capsule capsule*.map
+ Test* capsule*.*.efi-capsule capsule*.map mkimage.imx-boot.spl \
+ mkimage.imx-boot.u-boot mkimage-out.imx-boot.spl mkimage-out.imx-boot.u-boot
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl vpl \
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index df373d3..fedfdb2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1190,6 +1190,7 @@
select DM_SPI_FLASH if SPI && MTD
select DM_KEYBOARD
select DM_SERIAL
+ select MMU_PGPROT if ARM64
select OF_BOARD_SETUP
select OF_CONTROL
select PINCTRL
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index f7707ac..044a7c1 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -74,10 +74,19 @@
.word 0xf57ff06f // isb
.word 0xe590d000 // ldr sp, [r0]
.word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901014 // ldr r1, [r0, #20]
+ .word 0xe121f301 // msr SP_irq, r1
.word 0xe5901010 // ldr r1, [r0, #16]
.word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
.word 0xe590100c // ldr r1, [r0, #12]
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
+#ifdef CONFIG_MACH_SUN55I_A523
+ .word 0xe5901018 // ldr r1, [r0, #24]
+ .word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR
+ .word 0xe590101c // ldr r1, [r0, #28]
+ .word 0xee0c1ffc // mcr 15, 0, r1, cr12, cr12, {7}; ICC_IGRPEN1
+#endif
+
.word 0xe12fff1e // bx lr ; return to FEL
ENDPROC(return_to_fel)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bcf3f4b..c197e3b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -419,6 +419,7 @@
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-bonegreen.dtb \
+ am335x-bonegreen-eco.dtb \
am335x-bonegreen-wireless.dtb \
am335x-icev2.dtb \
am335x-pocketbeagle.dtb \
@@ -530,17 +531,6 @@
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
-dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
- stm32429i-eval.dtb \
- stm32f469-disco.dtb
-
-dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
- stm32f769-disco.dtb \
- stm32746g-eval.dtb
-dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
- stm32h743i-eval.dtb \
- stm32h750i-art-pi.dtb
-
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-inet-3f.dtb \
sun4i-a10-inet-3w.dtb
@@ -1087,29 +1077,9 @@
ast2600-sbp1.dtb \
ast2600-x4tf.dtb
-dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
-
-dtb-$(CONFIG_STM32MP13X) += \
- stm32mp135f-dk.dtb
-
dtb-$(CONFIG_STM32MP15X) += \
- stm32mp157a-dk1.dtb \
- stm32mp157a-dk1-scmi.dtb \
- stm32mp157a-icore-stm32mp1-ctouch2.dtb \
- stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
- stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
- stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
- stm32mp157c-dk2.dtb \
- stm32mp157c-dk2-scmi.dtb \
- stm32mp157c-ed1.dtb \
- stm32mp157c-ed1-scmi.dtb \
- stm32mp157c-ev1.dtb \
- stm32mp157c-ev1-scmi.dtb \
stm32mp157c-odyssey.dtb
-dtb-$(CONFIG_STM32MP25X) += \
- stm32mp257f-ev1.dtb
-
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-r5-base-board.dtb
diff --git a/arch/arm/dts/am335x-bonegreen-eco.dts b/arch/arm/dts/am335x-bonegreen-eco.dts
new file mode 100644
index 0000000..f3363d1
--- /dev/null
+++ b/arch/arm/dts/am335x-bonegreen-eco.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Bootlin
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+#include "am335x-bonegreen-common.dtsi"
+
+/ {
+ model = "TI AM335x BeagleBone Green Eco";
+ compatible = "ti,am335x-bone-green-eco", "ti,am335x-bone-green",
+ "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+
+ cpus {
+ cpu@0 {
+ /delete-property/ cpu0-supply;
+ };
+ };
+};
+
+&usb0 {
+ interrupts-extended = <&intc 18>;
+ interrupt-names = "mc";
+};
+
+&baseboard_eeprom {
+ /delete-property/ vcc-supply;
+};
+
+&i2c0 {
+ /delete-node/ tps@24;
+};
diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
new file mode 100644
index 0000000..2d1f02b
--- /dev/null
+++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "imx95-u-boot.dtsi"
+
+&lpuart1 {
+ bootph-pre-ram;
+};
+
+®_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+};
+
+&wdog3 {
+ status = "disabled";
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi
new file mode 100644
index 0000000..5ec3b1c
--- /dev/null
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+/ {
+ binman {
+ multiple-images;
+
+ m33-oei-ddrfw {
+ pad-byte = <0x00>;
+ align-size = <0x8>;
+ filename = "m33-oei-ddrfw.bin";
+
+ oei-m33-ddr {
+ align-size = <0x4>;
+ filename = "oei-m33-ddr.bin";
+ type = "blob-ext";
+ };
+
+ imx-lpddr {
+ type = "nxp-header-ddrfw";
+
+ imx-lpddr-imem {
+ filename = "lpddr5_imem_v202311.bin";
+ type = "blob-ext";
+ };
+
+ imx-lpddr-dmem {
+ filename = "lpddr5_dmem_v202311.bin";
+ type = "blob-ext";
+ };
+ };
+
+ imx-lpddr-qb {
+ type = "nxp-header-ddrfw";
+
+ imx-lpddr-imem-qb {
+ filename = "lpddr5_imem_qb_v202311.bin";
+ type = "blob-ext";
+ };
+
+ imx-lpddr-dmem-qb {
+ filename = "lpddr5_dmem_qb_v202311.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl {
+ align = <0x400>;
+ align-size = <0x400>;
+ type = "mkimage";
+ args = "-n spl/u-boot-spl.cfgout -T imx8image";
+ };
+
+ u-boot {
+ type = "mkimage";
+ args = "-n u-boot-container.cfgout -T imx8image";
+ };
+ };
+ };
+};
+
+&A55_0 {
+ clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_1 {
+ clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_2 {
+ clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_3 {
+ clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_4 {
+ clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&A55_5 {
+ clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
+ /delete-property/ power-domains;
+};
+
+&aips1 {
+ bootph-all;
+};
+
+&aips2 {
+ bootph-all;
+};
+
+&aips3 {
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+};
+
+&elemu1 {
+ bootph-all;
+ status = "okay";
+};
+
+&elemu3 {
+ bootph-all;
+ status = "okay";
+};
+
+&{/firmware} {
+ bootph-all;
+};
+
+&{/firmware/scmi} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@11} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@13} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@14} {
+ bootph-all;
+};
+
+&{/firmware/scmi/protocol@19} {
+ bootph-all;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+};
+
+&gpio5 {
+ bootph-pre-ram;
+};
+
+&mu2 {
+ bootph-all;
+};
+
+&osc_24m {
+ bootph-all;
+};
+
+&{/soc} {
+ bootph-all;
+};
+
+&sram0 {
+ bootph-all;
+};
+
+&scmi_buf0 {
+ reg = <0x0 0x400>;
+ bootph-all;
+};
+
+&scmi_buf1 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index a067b0b..01b6a8e 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -71,13 +71,6 @@
#define AM625_BEAGLEPLAY_DTB "dts/upstream/src/arm64/ti/k3-am625-beagleplay.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- };
- };
-
tifsstub-gp {
filename = "tifsstub.bin_gp";
ti-secure-rom {
@@ -153,8 +146,8 @@
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
- blob-ext {
- filename = "ti-dm.bin";
+ ti-dm {
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
index 4a65427..9b536d6 100644
--- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
@@ -158,13 +158,6 @@
#define AM625_PHYBOARD_LYRA_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- };
- };
-
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
@@ -270,8 +263,8 @@
content = <&dm>;
keyfile = "custMpk.pem";
};
- dm: blob-ext {
- filename = "ti-dm.bin";
+ dm: ti-dm {
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
@@ -418,8 +411,8 @@
fit {
images {
dm {
- blob-ext {
- filename = "ti-dm.bin";
+ ti-dm {
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi
index 534eb14..cc619f5 100644
--- a/arch/arm/dts/k3-am625-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -156,14 +156,6 @@
#define AM625_SK_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
@@ -270,7 +262,8 @@
keyfile = "custMpk.pem";
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -397,7 +390,8 @@
dm {
ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
index 0e61889..5a8788b 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
@@ -144,13 +144,6 @@
#define VERDIN_AM62_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- };
- };
-
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
@@ -257,7 +250,7 @@
keyfile = "custMpk.pem";
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
@@ -380,7 +373,7 @@
dm {
ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
index 325702e..1871926 100644
--- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
@@ -164,14 +164,6 @@
#define AM62A7_PHYBOARD_LYRA_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
@@ -276,7 +268,8 @@
keyfile = "custMpk.pem";
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -462,7 +455,8 @@
};
dm {
ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi
index 2a8c260..ed97354 100644
--- a/arch/arm/dts/k3-am62a-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi
@@ -148,14 +148,6 @@
#define AM62A7_SK_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
@@ -260,7 +252,8 @@
keyfile = "custMpk.pem";
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -385,7 +378,8 @@
};
dm {
ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi
index 797644a..8216add 100644
--- a/arch/arm/dts/k3-am62p-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi
@@ -127,14 +127,6 @@
#define AM62PX_SK_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
-
- blob-ext {
- filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
@@ -210,7 +202,8 @@
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi
index 6c52038..ba05d41 100644
--- a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi
+++ b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi
@@ -53,6 +53,10 @@
status = "disabled";
};
+&main_gpio1 {
+ bootph-all;
+};
+
#if IS_ENABLED(CONFIG_TARGET_J722S_R5_BEAGLEY_AI)
&binman {
@@ -164,15 +168,6 @@
#define BEAGLEY_AI_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
-
- blob-ext {
- filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
ti-spl {
insert-template = <&ti_spl_template>;
@@ -185,7 +180,8 @@
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
index 9c6e324..e836264 100644
--- a/arch/arm/dts/k3-am69-r5-sk.dts
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -10,3 +10,10 @@
#include "k3-j784s4-ddr.dtsi"
#include "k3-am69-sk-u-boot.dtsi"
#include "k3-j784s4-r5.dtsi"
+
+&tps659413 {
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
+};
diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
index 2f11950..fc68608 100644
--- a/arch/arm/dts/k3-am69-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
@@ -58,17 +58,18 @@
#else // CONFIG_ARM64
&binman {
- ti-dm {
- filename = "ti-dm.bin";
-
- blob-ext {
- filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
tispl {
insert-template = <&ti_spl>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
};
u-boot {
@@ -77,6 +78,16 @@
tispl-unsigned {
insert-template = <&ti_spl_unsigned>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
};
u-boot-unsigned {
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi
index 423badd..47a4cde 100644
--- a/arch/arm/dts/k3-j7200-binman.dtsi
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -237,13 +237,6 @@
#define J7200_EVM_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
ti-spl {
insert-template = <&ti_spl_template>;
@@ -345,7 +338,8 @@
keyfile = "custMpk.pem";
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -430,7 +424,8 @@
images {
dm {
ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
index 8cefa39..6a773c1 100644
--- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
@@ -212,13 +212,6 @@
#define J721E_BBAI64_DTB "dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- };
- };
-
ti-spl_unsigned {
filename = "tispl.bin_unsigned";
pad-byte = <0xff>;
@@ -263,8 +256,8 @@
os = "DM";
load = <0x89000000>;
entry = <0x89000000>;
- blob-ext {
- filename = "ti-dm.bin";
+ ti-dm {
+ filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
index 0d60729..6adfab1 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -333,13 +333,6 @@
#define J721E_EVM_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
ti-spl {
insert-template = <&ti_spl_template>;
@@ -467,7 +460,8 @@
keyfile = "custMpk.pem";
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -551,7 +545,8 @@
images {
dm {
ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi
index d121d8c..73af184 100644
--- a/arch/arm/dts/k3-j721s2-binman.dtsi
+++ b/arch/arm/dts/k3-j721s2-binman.dtsi
@@ -145,13 +145,6 @@
#define J721S2_EVM_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
- blob-ext {
- filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
ti-spl {
insert-template = <&ti_spl_template>;
@@ -286,7 +279,8 @@
keyfile = "custMpk.pem";
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
@@ -371,7 +365,8 @@
images {
dm {
ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi
index 6b52116..8f14713 100644
--- a/arch/arm/dts/k3-j722s-binman.dtsi
+++ b/arch/arm/dts/k3-j722s-binman.dtsi
@@ -116,15 +116,6 @@
#define J722S_EVM_DTB "u-boot.dtb"
&binman {
- ti-dm {
- filename = "ti-dm.bin";
-
- blob-ext {
- filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
ti-spl {
insert-template = <&ti_spl_template>;
@@ -137,7 +128,8 @@
};
dm: ti-dm {
- filename = "ti-dm.bin";
+ filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
};
};
diff --git a/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
index ede5d6e5..b1d79a3 100644
--- a/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
@@ -43,17 +43,18 @@
#else // CONFIG_ARM64
&binman {
- ti-dm {
- filename = "ti-dm.bin";
-
- blob-ext {
- filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
tispl {
insert-template = <&ti_spl>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
};
u-boot {
@@ -62,6 +63,16 @@
tispl-unsigned {
insert-template = <&ti_spl_unsigned>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
};
u-boot-unsigned {
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi
index 0553825..cb1fbc6 100644
--- a/arch/arm/dts/k3-j784s4-binman.dtsi
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -165,8 +165,8 @@
keyfile = "custMpk.pem";
};
- dm: blob-ext {
- filename = "ti-dm.bin";
+ dm: ti-dm {
+ optional;
};
};
@@ -254,8 +254,8 @@
fit {
images {
dm {
- blob-ext {
- filename = "ti-dm.bin";
+ ti-dm {
+ optional;
};
};
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 8a60d7c..cc0b562 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -52,17 +52,18 @@
#else // CONFIG_ARM64
&binman {
- ti-dm {
- filename = "ti-dm.bin";
-
- blob-ext {
- filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
- optional;
- };
- };
-
tispl {
insert-template = <&ti_spl>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
};
u-boot {
@@ -71,6 +72,16 @@
tispl-unsigned {
insert-template = <&ti_spl_unsigned>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
};
u-boot-unsigned {
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index 0eeffa7..fc20438 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -10,3 +10,10 @@
#include "k3-j784s4-ddr.dtsi"
#include "k3-j784s4-evm-u-boot.dtsi"
#include "k3-j784s4-r5.dtsi"
+
+&tps659413 {
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
+};
diff --git a/arch/arm/dts/qrb4210-rb2-u-boot.dtsi b/arch/arm/dts/qrb4210-rb2-u-boot.dtsi
deleted file mode 100644
index 7d1375f..0000000
--- a/arch/arm/dts/qrb4210-rb2-u-boot.dtsi
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-/* This is usually OTG but U-Boot doesn't support that properly */
-&usb_dwc3 {
- dr_mode = "host";
-};
diff --git a/arch/arm/dts/st-pincfg.h b/arch/arm/dts/st-pincfg.h
deleted file mode 100644
index d805512..0000000
--- a/arch/arm/dts/st-pincfg.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ST_PINCFG_H_
-#define _ST_PINCFG_H_
-
-/* Alternate functions */
-#define ALT1 1
-#define ALT2 2
-#define ALT3 3
-#define ALT4 4
-#define ALT5 5
-#define ALT6 6
-#define ALT7 7
-
-/* Output enable */
-#define OE (1 << 27)
-/* Pull Up */
-#define PU (1 << 26)
-/* Open Drain */
-#define OD (1 << 25)
-#define RT (1 << 23)
-#define INVERTCLK (1 << 22)
-#define CLKNOTDATA (1 << 21)
-#define DOUBLE_EDGE (1 << 20)
-#define CLK_A (0 << 18)
-#define CLK_B (1 << 18)
-#define CLK_C (2 << 18)
-#define CLK_D (3 << 18)
-
-/* User-frendly defines for Pin Direction */
- /* oe = 0, pu = 0, od = 0 */
-#define IN (0)
- /* oe = 0, pu = 1, od = 0 */
-#define IN_PU (PU)
- /* oe = 1, pu = 0, od = 0 */
-#define OUT (OE)
- /* oe = 1, pu = 0, od = 1 */
-#define BIDIR (OE | OD)
- /* oe = 1, pu = 1, od = 1 */
-#define BIDIR_PU (OE | PU | OD)
-
-/* RETIME_TYPE */
-/*
- * B Mode
- * Bypass retime with optional delay parameter
- */
-#define BYPASS (0)
-/*
- * R0, R1, R0D, R1D modes
- * single-edge data non inverted clock, retime data with clk
- */
-#define SE_NICLK_IO (RT)
-/*
- * RIV0, RIV1, RIV0D, RIV1D modes
- * single-edge data inverted clock, retime data with clk
- */
-#define SE_ICLK_IO (RT | INVERTCLK)
-/*
- * R0E, R1E, R0ED, R1ED modes
- * double-edge data, retime data with clk
- */
-#define DE_IO (RT | DOUBLE_EDGE)
-/*
- * CIV0, CIV1 modes with inverted clock
- * Retiming the clk pins will park clock & reduce the noise within the core.
- */
-#define ICLK (RT | CLKNOTDATA | INVERTCLK)
-/*
- * CLK0, CLK1 modes with non-inverted clock
- * Retiming the clk pins will park clock & reduce the noise within the core.
- */
-#define NICLK (RT | CLKNOTDATA)
-#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/dts/stih407-clock.dtsi b/arch/arm/dts/stih407-clock.dtsi
deleted file mode 100644
index 1ab40db..0000000
--- a/arch/arm/dts/stih407-clock.dtsi
+++ /dev/null
@@ -1,323 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics R&D Limited
- */
-#include <dt-bindings/clock/stih407-clks.h>
-/ {
- /*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- };
-
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /*
- * A9 PLL.
- */
- clockgen-a9@92b0000 {
- compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
-
- clockgen_a9_pll: clockgen-a9-pll {
- #clock-cells = <1>;
- compatible = "st,stih407-clkgen-plla9";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
- };
- };
-
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@92b0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
-
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
-
- clockgen-a@90ff000 {
- compatible = "st,clkgen-c32";
- reg = <0x90ff000 0x1000>;
-
- clk_s_a0_pll: clk-s-a0-pll {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
- };
-
- clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
-
- #clock-cells = <1>;
-
- clocks = <&clk_s_a0_pll 0>,
- <&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0";
- clock-critical = <CLK_IC_LMI0>;
- };
- };
-
- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
- "clk-s-c0-fs0-ch1",
- "clk-s-c0-fs0-ch2",
- "clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
- };
-
- clk_s_c0: clockgen-c@9103000 {
- compatible = "st,clkgen-c32";
- reg = <0x9103000 0x1000>;
-
- clk_s_c0_pll0: clk-s-c0-pll0 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
- };
-
- clk_s_c0_pll1: clk-s-c0-pll1 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll1";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
- };
-
- clk_s_c0_flexgen: clk-s-c0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_c0_pll0 0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_quadfs 0>,
- <&clk_s_c0_quadfs 1>,
- <&clk_s_c0_quadfs 2>,
- <&clk_s_c0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-icn-gpu",
- "clk-fdma",
- "clk-nand",
- "clk-hva",
- "clk-proc-stfe",
- "clk-proc-tp",
- "clk-rx-icn-dmu",
- "clk-rx-icn-hva",
- "clk-icn-cpu",
- "clk-tx-icn-dmu",
- "clk-mmc-0",
- "clk-mmc-1",
- "clk-jpegdec",
- "clk-ext2fa9",
- "clk-ic-bdisp-0",
- "clk-ic-bdisp-1",
- "clk-pp-dmu",
- "clk-vid-dmu",
- "clk-dss-lpc",
- "clk-st231-aud-0",
- "clk-st231-gp-1",
- "clk-st231-dmu",
- "clk-icn-lmi",
- "clk-tx-icn-disp-1",
- "clk-icn-sbc",
- "clk-stfe-frc2",
- "clk-eth-phy",
- "clk-eth-ref-phyclk",
- "clk-flash-promip",
- "clk-main-disp",
- "clk-aux-disp",
- "clk-compo-dvp";
- clock-critical = <CLK_PROC_STFE>,
- <CLK_ICN_CPU>,
- <CLK_TX_ICN_DMU>,
- <CLK_EXT2F_A9>,
- <CLK_ICN_LMI>,
- <CLK_ICN_SBC>;
-
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
- };
-
- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
- "clk-s-d0-fs0-ch1",
- "clk-s-d0-fs0-ch2",
- "clk-s-d0-fs0-ch3";
- };
-
- clockgen-d0@9104000 {
- compatible = "st,clkgen-c32";
- reg = <0x9104000 0x1000>;
-
- clk_s_d0_flexgen: clk-s-d0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-audio", "st,flexgen";
-
- clocks = <&clk_s_d0_quadfs 0>,
- <&clk_s_d0_quadfs 1>,
- <&clk_s_d0_quadfs 2>,
- <&clk_s_d0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-pcm-0",
- "clk-pcm-1",
- "clk-pcm-2",
- "clk-spdiff";
- };
- };
-
- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
- "clk-s-d2-fs0-ch1",
- "clk-s-d2-fs0-ch2",
- "clk-s-d2-fs0-ch3";
- };
-
- clockgen-d2@9106000 {
- compatible = "st,clkgen-c32";
- reg = <0x9106000 0x1000>;
-
- clk_s_d2_flexgen: clk-s-d2-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-video", "st,flexgen";
-
- clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_d2_quadfs 2>,
- <&clk_s_d2_quadfs 3>,
- <&clk_sysin>,
- <&clk_sysin>,
- <&clk_tmdsout_hdmi>;
-
- clock-output-names = "clk-pix-main-disp",
- "clk-pix-pip",
- "clk-pix-gdp1",
- "clk-pix-gdp2",
- "clk-pix-gdp3",
- "clk-pix-gdp4",
- "clk-pix-aux-disp",
- "clk-denc",
- "clk-pix-hddac",
- "clk-hddac",
- "clk-sddac",
- "clk-pix-dvo",
- "clk-dvo",
- "clk-pix-hdmi",
- "clk-tmds-hdmi",
- "clk-ref-hdmiphy";
- };
- };
-
- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
- "clk-s-d3-fs0-ch1",
- "clk-s-d3-fs0-ch2",
- "clk-s-d3-fs0-ch3";
- };
-
- clockgen-d3@9107000 {
- compatible = "st,clkgen-c32";
- reg = <0x9107000 0x1000>;
-
- clk_s_d3_flexgen: clk-s-d3-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_d3_quadfs 0>,
- <&clk_s_d3_quadfs 1>,
- <&clk_s_d3_quadfs 2>,
- <&clk_s_d3_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-stfe-frc1",
- "clk-tsout-0",
- "clk-tsout-1",
- "clk-mchi",
- "clk-vsens-compo",
- "clk-frc1-remote",
- "clk-lpc-0",
- "clk-lpc-1";
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih407-family.dtsi b/arch/arm/dts/stih407-family.dtsi
deleted file mode 100644
index 7c36c37..0000000
--- a/arch/arm/dts/stih407-family.dtsi
+++ /dev/null
@@ -1,1000 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
- */
-#include "stih407-pinctrl.dtsi"
-#include <dt-bindings/mfd/st-lpc.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/reset/stih407-resets.h>
-#include <dt-bindings/interrupt-controller/irq-st.h>
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gp0_reserved: rproc@45000000 {
- compatible = "shared-dma-pool";
- reg = <0x45000000 0x00400000>;
- no-map;
- };
-
- delta_reserved: rproc@44000000 {
- compatible = "shared-dma-pool";
- reg = <0x44000000 0x01000000>;
- no-map;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
-
- /* u-boot puts hpen in SBC dmem at 0xa4 offset */
- cpu-release-addr = <0x94100A4>;
-
- /* kHz uV */
- operating-points = <1500000 0
- 1200000 0
- 800000 0
- 500000 0>;
-
- clocks = <&clk_m_a9>;
- clock-names = "cpu";
- clock-latency = <100000>;
- cpu0-supply = <&pwm_regulator>;
- st,syscfg = <&syscfg_core 0x8e0>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
-
- /* u-boot puts hpen in SBC dmem at 0xa4 offset */
- cpu-release-addr = <0x94100A4>;
-
- /* kHz uV */
- operating-points = <1500000 0
- 1200000 0
- 800000 0
- 500000 0>;
- };
- };
-
- intc: interrupt-controller@8761000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x08761000 0x1000>, <0x08760100 0x100>;
- };
-
- scu@8760000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0x08760000 0x1000>;
- };
-
- timer@8760200 {
- interrupt-parent = <&intc>;
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x08760200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&arm_periph_clk>;
- };
-
- l2: cache-controller@8762000 {
- compatible = "arm,pl310-cache";
- reg = <0x08762000 0x1000>;
- arm,data-latency = <3 3 3>;
- arm,tag-latency = <2 2 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- arm-pmu {
- interrupt-parent = <&intc>;
- compatible = "arm,cortex-a9-pmu";
- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pwm_regulator: pwm-regulator {
- compatible = "pwm-regulator";
- pwms = <&pwm1 3 8448>;
- regulator-name = "CPU_1V0_AVS";
- regulator-min-microvolt = <784000>;
- regulator-max-microvolt = <1299000>;
- regulator-always-on;
- max-duty-cycle = <255>;
- status = "okay";
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
- compatible = "simple-bus";
-
- restart: restart-controller@0 {
- compatible = "st,stih407-restart";
- reg = <0 0>;
- st,syscfg = <&syscfg_sbc_reg>;
- status = "okay";
- };
-
- powerdown: powerdown-controller@0 {
- compatible = "st,stih407-powerdown";
- reg = <0 0>;
- #reset-cells = <1>;
- };
-
- softreset: softreset-controller@0 {
- compatible = "st,stih407-softreset";
- reg = <0 0>;
- #reset-cells = <1>;
- };
-
- picophyreset: picophyreset-controller@0 {
- compatible = "st,stih407-picophyreset";
- reg = <0 0>;
- #reset-cells = <1>;
- };
-
- syscfg_sbc: sbc-syscfg@9620000 {
- compatible = "st,stih407-sbc-syscfg", "syscon";
- reg = <0x9620000 0x1000>;
- };
-
- syscfg_front: front-syscfg@9280000 {
- compatible = "st,stih407-front-syscfg", "syscon";
- reg = <0x9280000 0x1000>;
- };
-
- syscfg_rear: rear-syscfg@9290000 {
- compatible = "st,stih407-rear-syscfg", "syscon";
- reg = <0x9290000 0x1000>;
- };
-
- syscfg_flash: flash-syscfg@92a0000 {
- compatible = "st,stih407-flash-syscfg", "syscon";
- reg = <0x92a0000 0x1000>;
- };
-
- syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
- compatible = "st,stih407-sbc-reg-syscfg", "syscon";
- reg = <0x9600000 0x1000>;
- };
-
- syscfg_core: core-syscfg@92b0000 {
- compatible = "st,stih407-core-syscfg", "syscon";
- reg = <0x92b0000 0x1000>;
-
- sti_sasg_codec: sti-sasg-codec {
- compatible = "st,stih407-sas-codec";
- #sound-dai-cells = <1>;
- status = "disabled";
- st,syscfg = <&syscfg_core>;
- };
- };
-
- syscfg_lpm: lpm-syscfg@94b5100 {
- compatible = "st,stih407-lpm-syscfg", "syscon";
- reg = <0x94b5100 0x1000>;
- };
-
- irq-syscfg@0 {
- compatible = "st,stih407-irq-syscfg";
- reg = <0 0>;
- st,syscfg = <&syscfg_core>;
- st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
- <ST_IRQ_SYSCFG_PMU_1>;
- st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
- <ST_IRQ_SYSCFG_DISABLED>;
- };
-
- /* Display */
- vtg_main: sti-vtg-main@8d02800 {
- compatible = "st,vtg";
- reg = <0x8d02800 0x200>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- vtg_aux: sti-vtg-aux@8d00200 {
- compatible = "st,vtg";
- reg = <0x8d00200 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- serial@9830000 {
- compatible = "st,asc";
- reg = <0x9830000 0x2c>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- /* Pinctrl moved out to a per-board configuration */
-
- status = "disabled";
- };
-
- serial@9831000 {
- compatible = "st,asc";
- reg = <0x9831000 0x2c>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial1>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- serial@9832000 {
- compatible = "st,asc";
- reg = <0x9832000 0x2c>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial2>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- /* SBC_ASC0 - UART10 */
- sbc_serial0: serial@9530000 {
- compatible = "st,asc";
- reg = <0x9530000 0x2c>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial0>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- serial@9531000 {
- compatible = "st,asc";
- reg = <0x9531000 0x2c>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial1>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- i2c@9840000 {
- compatible = "st,comms-ssc4-i2c";
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x9840000 0x110>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9841000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9841000 0x110>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9842000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9842000 0x110>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9843000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9843000 0x110>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9844000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9844000 0x110>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9845000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9845000 0x110>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c5_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
-
- /* SSCs on SBC */
- i2c@9540000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9540000 0x110>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c10_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c@9541000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9541000 0x110>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c11_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- usb2_picophy0: phy1@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0x100 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY2_RESET>;
- reset-names = "global", "port";
- };
-
- miphy28lp_phy: miphy28lp@0 {
- compatible = "st,miphy28lp-phy";
- st,syscfg = <&syscfg_core>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- reg = <0 0>;
-
- phy_port0: port@9b22000 {
- reg = <0x9b22000 0xff>,
- <0x9b09000 0xff>,
- <0x9b04000 0xff>;
- reg-names = "sata-up",
- "pcie-up",
- "pipew";
-
- st,syscfg = <0x114 0x818 0xe0 0xec>;
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
- };
-
- phy_port1: port@9b2a000 {
- reg = <0x9b2a000 0xff>,
- <0x9b19000 0xff>,
- <0x9b14000 0xff>;
- reg-names = "sata-up",
- "pcie-up",
- "pipew";
-
- st,syscfg = <0x118 0x81c 0xe4 0xf0>;
-
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
- };
-
- phy_port2: port@8f95000 {
- reg = <0x8f95000 0xff>,
- <0x8f90000 0xff>;
- reg-names = "pipew",
- "usb3-up";
-
- st,syscfg = <0x11c 0x820>;
-
- #phy-cells = <1>;
-
- reset-names = "miphy-sw-rst";
- resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
- };
- };
-
- spi@9840000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9840000 0x110>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-0 = <&pinctrl_spi0_default>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9841000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9841000 0x110>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9842000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9842000 0x110>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9843000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9843000 0x110>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi3_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9844000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9844000 0x110>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi4_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- /* SBC SSC */
- spi@9540000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9540000 0x110>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi10_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9541000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9541000 0x110>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi11_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- spi@9542000 {
- compatible = "st,comms-ssc4-spi";
- reg = <0x9542000 0x110>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi12_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- mmc0: sdhci@9060000 {
- compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
- reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
- reg-names = "mmc", "top-mmc-delay";
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc0>;
- clock-names = "mmc", "icn";
- clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
- bus-width = <8>;
- };
-
- mmc1: sdhci@9080000 {
- compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
- reg = <0x09080000 0x7ff>;
- reg-names = "mmc";
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mmcirq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sd1>;
- clock-names = "mmc", "icn";
- clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
- <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
- resets = <&softreset STIH407_MMC1_SOFTRESET>;
- bus-width = <4>;
- };
-
- /* Watchdog and Real-Time Clock */
- lpc@8787000 {
- compatible = "st,stih407-lpc";
- reg = <0x8787000 0x1000>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
- timeout-sec = <120>;
- st,syscfg = <&syscfg_core>;
- st,lpc-mode = <ST_LPC_MODE_WDT>;
- };
-
- lpc@8788000 {
- compatible = "st,stih407-lpc";
- reg = <0x8788000 0x1000>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
- st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
- };
-
- sata0: sata@9b20000 {
- compatible = "st,ahci";
- reg = <0x9b20000 0x1000>;
-
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
-
- phys = <&phy_port0 PHY_TYPE_SATA>;
- phy-names = "ahci_phy";
-
- resets = <&powerdown STIH407_SATA0_POWERDOWN>,
- <&softreset STIH407_SATA0_SOFTRESET>,
- <&softreset STIH407_SATA0_PWR_SOFTRESET>;
- reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
-
- clock-names = "ahci_clk";
- clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
-
- ports-implemented = <0x1>;
-
- status = "disabled";
- };
-
- sata1: sata@9b28000 {
- compatible = "st,ahci";
- reg = <0x9b28000 0x1000>;
-
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
-
- phys = <&phy_port1 PHY_TYPE_SATA>;
- phy-names = "ahci_phy";
-
- resets = <&powerdown STIH407_SATA1_POWERDOWN>,
- <&softreset STIH407_SATA1_SOFTRESET>,
- <&softreset STIH407_SATA1_PWR_SOFTRESET>;
- reset-names = "pwr-dwn",
- "sw-rst",
- "pwr-rst";
-
- clock-names = "ahci_clk";
- clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
-
- ports-implemented = <0x1>;
-
- status = "disabled";
- };
-
-
- st_dwc3: dwc3@8f94000 {
- compatible = "st,stih407-dwc3";
- reg = <0x08f94000 0x1000>, <0x110 0x4>;
- reg-names = "reg-glue", "syscfg-reg";
- st,syscfg = <&syscfg_core>;
- resets = <&powerdown STIH407_USB3_POWERDOWN>,
- <&softreset STIH407_MIPHY2_SOFTRESET>;
- reset-names = "powerdown", "softreset";
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- ranges;
-
- status = "disabled";
-
- dwc3: dwc3@9900000 {
- compatible = "snps,dwc3";
- reg = <0x09900000 0x100000>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- phy-names = "usb2-phy", "usb3-phy";
- phys = <&usb2_picophy0>,
- <&phy_port2 PHY_TYPE_USB3>;
- snps,dis_u3_susphy_quirk;
- };
- };
-
- /* COMMS PWM Module */
- pwm0: pwm@9810000 {
- compatible = "st,sti-pwm";
- #pwm-cells = <2>;
- reg = <0x9810000 0x68>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
- clock-names = "pwm";
- clocks = <&clk_sysin>;
- st,pwm-num-chan = <1>;
-
- status = "disabled";
- };
-
- /* SBC PWM Module */
- pwm1: pwm@9510000 {
- compatible = "st,sti-pwm";
- #pwm-cells = <2>;
- reg = <0x9510000 0x68>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1_chan0_default
- &pinctrl_pwm1_chan1_default
- &pinctrl_pwm1_chan2_default
- &pinctrl_pwm1_chan3_default>;
- clock-names = "pwm";
- clocks = <&clk_sysin>;
- st,pwm-num-chan = <4>;
-
- status = "disabled";
- };
-
- rng10: rng@8a89000 {
- compatible = "st,rng";
- reg = <0x08a89000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- rng11: rng@8a8a000 {
- compatible = "st,rng";
- reg = <0x08a8a000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- ethernet0: dwmac@9630000 {
- device_type = "network";
- status = "disabled";
- compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
- reg = <0x9630000 0x8000>, <0x80 0x4>;
- reg-names = "stmmaceth", "sti-ethconf";
-
- st,syscon = <&syscfg_sbc_reg 0x80>;
- st,gmac_en;
- resets = <&softreset STIH407_ETH1_SOFTRESET>;
- reset-names = "stmmaceth";
-
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
-
- /* DMA Bus Mode */
- snps,pbl = <8>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii1>;
-
- clock-names = "stmmaceth", "sti-ethclk";
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_ETH_PHY>;
- };
-
- rng10: rng@8a89000 {
- compatible = "st,rng";
- reg = <0x08a89000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- rng11: rng@8a8a000 {
- compatible = "st,rng";
- reg = <0x08a8a000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- mailbox0: mailbox@8f00000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f00000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- mbox-name = "a9";
- status = "okay";
- };
-
- mailbox1: mailbox@8f01000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f01000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_gp_1";
- status = "okay";
- };
-
- mailbox2: mailbox@8f02000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f02000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_gp_0";
- status = "okay";
- };
-
- mailbox3: mailbox@8f03000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f03000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_audio_video";
- status = "okay";
- };
-
- st231_gp0: st231-gp0@0 {
- compatible = "st,st231-rproc";
- reg = <0 0>;
- memory-region = <&gp0_reserved>;
- resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x22c>;
- #mbox-cells = <1>;
- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
- mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
- };
-
- st231_delta: st231-delta@0 {
- compatible = "st,st231-rproc";
- reg = <0 0>;
- memory-region = <&delta_reserved>;
- resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x224>;
- #mbox-cells = <1>;
- mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
- mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
- };
-
- /* fdma audio */
- fdma0: dma-controller@8e20000 {
- compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
- reg = <0x8e20000 0x8000>,
- <0x8e30000 0x3000>,
- <0x8e37000 0x1000>,
- <0x8e38000 0x8000>;
- reg-names = "slimcore", "dmem", "peripherals", "imem";
- clocks = <&clk_s_c0_flexgen CLK_FDMA>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <16>;
- #dma-cells = <3>;
- };
-
- /* fdma app */
- fdma1: dma-controller@8e40000 {
- compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
- reg = <0x8e40000 0x8000>,
- <0x8e50000 0x3000>,
- <0x8e57000 0x1000>,
- <0x8e58000 0x8000>;
- reg-names = "slimcore", "dmem", "peripherals", "imem";
- clocks = <&clk_s_c0_flexgen CLK_FDMA>,
- <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
- <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <16>;
- #dma-cells = <3>;
-
- status = "disabled";
- };
-
- /* fdma free running */
- fdma2: dma-controller@8e60000 {
- compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
- reg = <0x8e60000 0x8000>,
- <0x8e70000 0x3000>,
- <0x8e77000 0x1000>,
- <0x8e78000 0x8000>;
- reg-names = "slimcore", "dmem", "peripherals", "imem";
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <16>;
- #dma-cells = <3>;
- clocks = <&clk_s_c0_flexgen CLK_FDMA>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>,
- <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- sti_uni_player0: sti-uni-player@8d80000 {
- compatible = "st,stih407-uni-player-hdmi";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
- assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d80000 0x158>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 2 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_player1: sti-uni-player@8d81000 {
- compatible = "st,stih407-uni-player-pcm-out";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
- assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d81000 0x158>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 3 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_player2: sti-uni-player@8d82000 {
- compatible = "st,stih407-uni-player-dac";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
- assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d82000 0x158>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 4 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_player3: sti-uni-player@8d85000 {
- compatible = "st,stih407-uni-player-spdif";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
- assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
- assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
- assigned-clock-rates = <50000000>;
- reg = <0x8d85000 0x158>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 7 0 1>;
- dma-names = "tx";
-
- status = "disabled";
- };
-
- sti_uni_reader0: sti-uni-reader@8d83000 {
- compatible = "st,stih407-uni-reader-pcm_in";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- reg = <0x8d83000 0x158>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 5 0 1>;
- dma-names = "rx";
-
- status = "disabled";
- };
-
- sti_uni_reader1: sti-uni-reader@8d84000 {
- compatible = "st,stih407-uni-reader-hdmi";
- #sound-dai-cells = <0>;
- st,syscfg = <&syscfg_core>;
- reg = <0x8d84000 0x158>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&fdma0 6 0 1>;
- dma-names = "rx";
-
- status = "disabled";
- };
-
- delta0@0 {
- compatible = "st,st-delta";
- reg = <0 0>;
- clock-names = "delta",
- "delta-st231",
- "delta-flash-promip";
- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
- <&clk_s_c0_flexgen CLK_ST231_DMU>,
- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
- };
- };
-};
diff --git a/arch/arm/dts/stih407-pinctrl.dtsi b/arch/arm/dts/stih407-pinctrl.dtsi
deleted file mode 100644
index 2cf3357..0000000
--- a/arch/arm/dts/stih407-pinctrl.dtsi
+++ /dev/null
@@ -1,1262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
- */
-#include "st-pincfg.h"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-/ {
-
- aliases {
- /* 0-5: PIO_SBC */
- gpio0 = &pio0;
- gpio1 = &pio1;
- gpio2 = &pio2;
- gpio3 = &pio3;
- gpio4 = &pio4;
- gpio5 = &pio5;
- /* 10-19: PIO_FRONT0 */
- gpio6 = &pio10;
- gpio7 = &pio11;
- gpio8 = &pio12;
- gpio9 = &pio13;
- gpio10 = &pio14;
- gpio11 = &pio15;
- gpio12 = &pio16;
- gpio13 = &pio17;
- gpio14 = &pio18;
- gpio15 = &pio19;
- /* 20: PIO_FRONT1 */
- gpio16 = &pio20;
- /* 30-35: PIO_REAR */
- gpio17 = &pio30;
- gpio18 = &pio31;
- gpio19 = &pio32;
- gpio20 = &pio33;
- gpio21 = &pio34;
- gpio22 = &pio35;
- /* 40-42: PIO_FLASH */
- gpio23 = &pio40;
- gpio24 = &pio41;
- gpio25 = &pio42;
- };
-
- soc {
- pin-controller-sbc@961f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-sbc-pinctrl";
- st,syscfg = <&syscfg_sbc>;
- reg = <0x0961f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09610000 0x6000>;
-
- pio0: gpio@9610000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO0";
- };
- pio1: gpio@9611000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO1";
- };
- pio2: gpio@9612000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO2";
- };
- pio3: gpio@9613000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO3";
- };
- pio4: gpio@9614000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO4";
- };
-
- pio5: gpio@9615000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO5";
- st,retime-pin-mask = <0x3f>;
- };
-
- cec0 {
- pinctrl_cec0_default: cec0-default {
- st,pins {
- hdmi_cec = <&pio2 4 ALT1 BIDIR>;
- };
- };
- };
-
- rc {
- pinctrl_ir: ir0 {
- st,pins {
- ir = <&pio4 0 ALT2 IN>;
- };
- };
-
- pinctrl_uhf: uhf0 {
- st,pins {
- ir = <&pio4 1 ALT2 IN>;
- };
- };
-
- pinctrl_tx: tx0 {
- st,pins {
- tx = <&pio4 2 ALT2 OUT>;
- };
- };
-
- pinctrl_tx_od: tx_od0 {
- st,pins {
- tx_od = <&pio4 3 ALT2 OUT>;
- };
- };
- };
-
- /* SBC_ASC0 - UART10 */
- sbc_serial0 {
- pinctrl_sbc_serial0: sbc_serial0-0 {
- st,pins {
- tx = <&pio3 4 ALT1 OUT>;
- rx = <&pio3 5 ALT1 IN>;
- };
- };
- };
- /* SBC_ASC1 - UART11 */
- sbc_serial1 {
- pinctrl_sbc_serial1: sbc_serial1-0 {
- st,pins {
- tx = <&pio2 6 ALT3 OUT>;
- rx = <&pio2 7 ALT3 IN>;
- };
- };
- };
-
- i2c10 {
- pinctrl_i2c10_default: i2c10-default {
- st,pins {
- sda = <&pio4 6 ALT1 BIDIR>;
- scl = <&pio4 5 ALT1 BIDIR>;
- };
- };
- };
-
- i2c11 {
- pinctrl_i2c11_default: i2c11-default {
- st,pins {
- sda = <&pio5 1 ALT1 BIDIR>;
- scl = <&pio5 0 ALT1 BIDIR>;
- };
- };
- };
-
- keyscan {
- pinctrl_keyscan: keyscan {
- st,pins {
- keyin0 = <&pio4 0 ALT6 IN>;
- keyin1 = <&pio4 5 ALT4 IN>;
- keyin2 = <&pio0 4 ALT2 IN>;
- keyin3 = <&pio2 6 ALT2 IN>;
-
- keyout0 = <&pio4 6 ALT4 OUT>;
- keyout1 = <&pio1 7 ALT2 OUT>;
- keyout2 = <&pio0 6 ALT2 OUT>;
- keyout3 = <&pio2 7 ALT2 OUT>;
- };
- };
- };
-
- gmac1 {
- /*
- * Almost all the boards based on STiH407 SoC have an embedded
- * switch where the mdio/mdc have been used for managing the SMI
- * iface via I2C. For this reason these lines can be allocated
- * by using dedicated configuration (in case of there will be a
- * standard PHY transceiver on-board).
- */
- pinctrl_rgmii1: rgmii1-0 {
- st,pins {
-
- txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
- rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
- rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
- };
- };
-
- pinctrl_rgmii1_mdio: rgmii1-mdio {
- st,pins {
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- };
- };
-
- pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 {
- st,pins {
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- };
- };
-
- pinctrl_mii1: mii1 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
- col = <&pio0 7 ALT1 IN BYPASS 1000>;
-
- mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- crs = <&pio1 2 ALT1 IN BYPASS 1000>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-
- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
- phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
- };
- };
-
- pinctrl_rmii1: rmii1-0 {
- st,pins {
- txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
- mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
- mdint = <&pio1 3 ALT1 IN BYPASS 0>;
- rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
- rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
- rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
- rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
-
- pinctrl_rmii1_phyclk: rmii1_phyclk {
- st,pins {
- phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
- };
- };
-
- pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
- st,pins {
- phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
- };
- };
- };
-
- pwm1 {
- pinctrl_pwm1_chan0_default: pwm1-0-default {
- st,pins {
- pwm-out = <&pio3 0 ALT1 OUT>;
- pwm-capturein = <&pio3 2 ALT1 IN>;
- };
- };
- pinctrl_pwm1_chan1_default: pwm1-1-default {
- st,pins {
- pwm-capturein = <&pio4 3 ALT1 IN>;
- pwm-out = <&pio4 4 ALT1 OUT>;
- };
- };
- pinctrl_pwm1_chan2_default: pwm1-2-default {
- st,pins {
- pwm-out = <&pio4 6 ALT3 OUT>;
- };
- };
- pinctrl_pwm1_chan3_default: pwm1-3-default {
- st,pins {
- pwm-out = <&pio4 7 ALT3 OUT>;
- };
- };
- };
-
- spi10 {
- pinctrl_spi10_default: spi10-4w-alt1-0 {
- st,pins {
- mtsr = <&pio4 6 ALT1 OUT>;
- mrst = <&pio4 7 ALT1 IN>;
- scl = <&pio4 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
- st,pins {
- mtsr = <&pio4 6 ALT1 BIDIR_PU>;
- scl = <&pio4 5 ALT1 OUT>;
- };
- };
- };
-
- spi11 {
- pinctrl_spi11_default: spi11-4w-alt2-0 {
- st,pins {
- mtsr = <&pio3 1 ALT2 OUT>;
- mrst = <&pio3 0 ALT2 IN>;
- scl = <&pio3 2 ALT2 OUT>;
- };
- };
-
- pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
- st,pins {
- mtsr = <&pio3 1 ALT2 BIDIR_PU>;
- scl = <&pio3 2 ALT2 OUT>;
- };
- };
- };
-
- spi12 {
- pinctrl_spi12_default: spi12-4w-alt2-0 {
- st,pins {
- mtsr = <&pio3 6 ALT2 OUT>;
- mrst = <&pio3 4 ALT2 IN>;
- scl = <&pio3 7 ALT2 OUT>;
- };
- };
-
- pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
- st,pins {
- mtsr = <&pio3 6 ALT2 BIDIR_PU>;
- scl = <&pio3 7 ALT2 OUT>;
- };
- };
- };
- };
-
- pin-controller-front0@920f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-front-pinctrl";
- st,syscfg = <&syscfg_front>;
- reg = <0x0920f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09200000 0x10000>;
-
- pio10: pio@9200000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO10";
- };
- pio11: pio@9201000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO11";
- };
- pio12: pio@9202000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO12";
- };
- pio13: pio@9203000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO13";
- };
- pio14: pio@9204000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO14";
- };
- pio15: pio@9205000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO15";
- };
- pio16: pio@9206000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x100>;
- st,bank-name = "PIO16";
- };
- pio17: pio@9207000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x100>;
- st,bank-name = "PIO17";
- };
- pio18: pio@9208000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x100>;
- st,bank-name = "PIO18";
- };
- pio19: pio@9209000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x9000 0x100>;
- st,bank-name = "PIO19";
- };
-
- /* Comms */
- serial0 {
- pinctrl_serial0: serial0-0 {
- st,pins {
- tx = <&pio17 0 ALT1 OUT>;
- rx = <&pio17 1 ALT1 IN>;
- };
- };
- pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
- st,pins {
- tx = <&pio17 0 ALT1 OUT>;
- rx = <&pio17 1 ALT1 IN>;
- cts = <&pio17 2 ALT1 IN>;
- rts = <&pio17 3 ALT1 OUT>;
- };
- };
- };
-
- serial1 {
- pinctrl_serial1: serial1-0 {
- st,pins {
- tx = <&pio16 0 ALT1 OUT>;
- rx = <&pio16 1 ALT1 IN>;
- };
- };
- };
-
- serial2 {
- pinctrl_serial2: serial2-0 {
- st,pins {
- tx = <&pio15 0 ALT1 OUT>;
- rx = <&pio15 1 ALT1 IN>;
- };
- };
- };
-
- mmc1 {
- pinctrl_sd1: sd1-0 {
- st,pins {
- sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
- sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
- sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
- sd_led = <&pio16 6 ALT6 OUT>;
- sd_pwren = <&pio16 7 ALT6 OUT>;
- sd_cd = <&pio19 0 ALT6 IN>;
- sd_wp = <&pio19 1 ALT6 IN>;
- };
- };
- };
-
-
- i2c0 {
- pinctrl_i2c0_default: i2c0-default {
- st,pins {
- sda = <&pio10 6 ALT2 BIDIR>;
- scl = <&pio10 5 ALT2 BIDIR>;
- };
- };
- };
-
- i2c1 {
- pinctrl_i2c1_default: i2c1-default {
- st,pins {
- sda = <&pio11 1 ALT2 BIDIR>;
- scl = <&pio11 0 ALT2 BIDIR>;
- };
- };
- };
-
- i2c2 {
- pinctrl_i2c2_default: i2c2-default {
- st,pins {
- sda = <&pio15 6 ALT2 BIDIR>;
- scl = <&pio15 5 ALT2 BIDIR>;
- };
- };
-
- pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
- st,pins {
- sda = <&pio12 6 ALT2 BIDIR>;
- scl = <&pio12 5 ALT2 BIDIR>;
- };
- };
- };
-
- i2c3 {
- pinctrl_i2c3_default: i2c3-alt1-0 {
- st,pins {
- sda = <&pio18 6 ALT1 BIDIR>;
- scl = <&pio18 5 ALT1 BIDIR>;
- };
- };
- pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
- st,pins {
- sda = <&pio17 7 ALT1 BIDIR>;
- scl = <&pio17 6 ALT1 BIDIR>;
- };
- };
- pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
- st,pins {
- sda = <&pio13 6 ALT3 BIDIR>;
- scl = <&pio13 5 ALT3 BIDIR>;
- };
- };
- };
-
- spi0 {
- pinctrl_spi0_default: spi0-4w-alt2-0 {
- st,pins {
- mtsr = <&pio10 6 ALT2 OUT>;
- mrst = <&pio10 7 ALT2 IN>;
- scl = <&pio10 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
- st,pins {
- mtsr = <&pio10 6 ALT2 BIDIR_PU>;
- scl = <&pio10 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
- st,pins {
- mtsr = <&pio19 7 ALT1 OUT>;
- mrst = <&pio19 5 ALT1 IN>;
- scl = <&pio19 6 ALT1 OUT>;
- };
- };
-
- pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
- st,pins {
- mtsr = <&pio19 7 ALT1 BIDIR_PU>;
- scl = <&pio19 6 ALT1 OUT>;
- };
- };
- };
-
- spi1 {
- pinctrl_spi1_default: spi1-4w-alt2-0 {
- st,pins {
- mtsr = <&pio11 1 ALT2 OUT>;
- mrst = <&pio11 2 ALT2 IN>;
- scl = <&pio11 0 ALT2 OUT>;
- };
- };
-
- pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
- st,pins {
- mtsr = <&pio11 1 ALT2 BIDIR_PU>;
- scl = <&pio11 0 ALT2 OUT>;
- };
- };
-
- pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
- st,pins {
- mtsr = <&pio14 3 ALT1 OUT>;
- mrst = <&pio14 4 ALT1 IN>;
- scl = <&pio14 2 ALT1 OUT>;
- };
- };
-
- pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
- st,pins {
- mtsr = <&pio14 3 ALT1 BIDIR_PU>;
- scl = <&pio14 2 ALT1 OUT>;
- };
- };
- };
-
- spi2 {
- pinctrl_spi2_default: spi2-4w-alt2-0 {
- st,pins {
- mtsr = <&pio12 6 ALT2 OUT>;
- mrst = <&pio12 7 ALT2 IN>;
- scl = <&pio12 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
- st,pins {
- mtsr = <&pio12 6 ALT2 BIDIR_PU>;
- scl = <&pio12 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
- st,pins {
- mtsr = <&pio14 6 ALT1 OUT>;
- mrst = <&pio14 7 ALT1 IN>;
- scl = <&pio14 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
- st,pins {
- mtsr = <&pio14 6 ALT1 BIDIR_PU>;
- scl = <&pio14 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
- st,pins {
- mtsr = <&pio15 6 ALT2 OUT>;
- mrst = <&pio15 7 ALT2 IN>;
- scl = <&pio15 5 ALT2 OUT>;
- };
- };
-
- pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
- st,pins {
- mtsr = <&pio15 6 ALT2 BIDIR_PU>;
- scl = <&pio15 5 ALT2 OUT>;
- };
- };
- };
-
- spi3 {
- pinctrl_spi3_default: spi3-4w-alt3-0 {
- st,pins {
- mtsr = <&pio13 6 ALT3 OUT>;
- mrst = <&pio13 7 ALT3 IN>;
- scl = <&pio13 5 ALT3 OUT>;
- };
- };
-
- pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
- st,pins {
- mtsr = <&pio13 6 ALT3 BIDIR_PU>;
- scl = <&pio13 5 ALT3 OUT>;
- };
- };
-
- pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
- st,pins {
- mtsr = <&pio17 7 ALT1 OUT>;
- mrst = <&pio17 5 ALT1 IN>;
- scl = <&pio17 6 ALT1 OUT>;
- };
- };
-
- pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
- st,pins {
- mtsr = <&pio17 7 ALT1 BIDIR_PU>;
- scl = <&pio17 6 ALT1 OUT>;
- };
- };
-
- pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
- st,pins {
- mtsr = <&pio18 6 ALT1 OUT>;
- mrst = <&pio18 7 ALT1 IN>;
- scl = <&pio18 5 ALT1 OUT>;
- };
- };
-
- pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
- st,pins {
- mtsr = <&pio18 6 ALT1 BIDIR_PU>;
- scl = <&pio18 5 ALT1 OUT>;
- };
- };
- };
-
- tsin0 {
- pinctrl_tsin0_parallel: tsin0_parallel {
- st,pins {
- DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin0_serial: tsin0_serial {
- st,pins {
- DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin1 {
- pinctrl_tsin1_parallel: tsin1_parallel {
- st,pins {
- DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin1_serial: tsin1_serial {
- st,pins {
- DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin2 {
- pinctrl_tsin2_parallel: tsin2_parallel {
- st,pins {
- DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
- DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin2_serial: tsin2_serial {
- st,pins {
- DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin3 {
- pinctrl_tsin3_serial: tsin3_serial {
- st,pins {
- DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin4 {
- pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
- st,pins {
- DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
- ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
- PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsin5 {
- pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
- st,pins {
- DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
- st,pins {
- DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsout0 {
- pinctrl_tsout0_parallel: tsout0_parallel {
- st,pins {
- DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
- VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- };
- };
- pinctrl_tsout0_serial: tsout0_serial {
- st,pins {
- DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
- VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- tsout1 {
- pinctrl_tsout1_serial: tsout1_serial {
- st,pins {
- DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
- VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- mtsin0 {
- pinctrl_mtsin0_parallel: mtsin0_parallel {
- st,pins {
- DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
- systrace {
- pinctrl_systrace_default: systrace-default {
- st,pins {
- trc_data0 = <&pio11 3 ALT5 OUT>;
- trc_data1 = <&pio11 4 ALT5 OUT>;
- trc_data2 = <&pio11 5 ALT5 OUT>;
- trc_data3 = <&pio11 6 ALT5 OUT>;
- trc_clk = <&pio11 7 ALT5 OUT>;
- };
- };
- };
- };
-
- pin-controller-front1@921f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-front-pinctrl";
- st,syscfg = <&syscfg_front>;
- reg = <0x0921f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09210000 0x10000>;
-
- pio20: pio@9210000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO20";
- };
-
- tsin4 {
- pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
- st,pins {
- DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
- VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
- };
-
- pin-controller-rear@922f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-rear-pinctrl";
- st,syscfg = <&syscfg_rear>;
- reg = <0x0922f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09220000 0x6000>;
-
- pio30: gpio@9220000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x100>;
- st,bank-name = "PIO30";
- };
- pio31: gpio@9221000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO31";
- };
- pio32: gpio@9222000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO32";
- };
- pio33: gpio@9223000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x100>;
- st,bank-name = "PIO33";
- };
- pio34: gpio@9224000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x100>;
- st,bank-name = "PIO34";
- };
- pio35: gpio@9225000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x100>;
- st,bank-name = "PIO35";
- st,retime-pin-mask = <0x7f>;
- };
-
- i2c4 {
- pinctrl_i2c4_default: i2c4-default {
- st,pins {
- sda = <&pio30 1 ALT1 BIDIR>;
- scl = <&pio30 0 ALT1 BIDIR>;
- };
- };
- };
-
- i2c5 {
- pinctrl_i2c5_default: i2c5-default {
- st,pins {
- sda = <&pio34 4 ALT1 BIDIR>;
- scl = <&pio34 3 ALT1 BIDIR>;
- };
- };
- };
-
- usb3 {
- pinctrl_usb3: usb3-2 {
- st,pins {
- usb-oc-detect = <&pio35 4 ALT1 IN>;
- usb-pwr-enable = <&pio35 5 ALT1 OUT>;
- usb-vbus-valid = <&pio35 6 ALT1 IN>;
- };
- };
- };
-
- pwm0 {
- pinctrl_pwm0_chan0_default: pwm0-0-default {
- st,pins {
- pwm-capturein = <&pio31 0 ALT1 IN>;
- pwm-out = <&pio31 1 ALT1 OUT>;
- };
- };
- };
-
- spi4 {
- pinctrl_spi4_default: spi4-4w-alt1-0 {
- st,pins {
- mtsr = <&pio30 1 ALT1 OUT>;
- mrst = <&pio30 2 ALT1 IN>;
- scl = <&pio30 0 ALT1 OUT>;
- };
- };
-
- pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
- st,pins {
- mtsr = <&pio30 1 ALT1 BIDIR_PU>;
- scl = <&pio30 0 ALT1 OUT>;
- };
- };
-
- pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
- st,pins {
- mtsr = <&pio34 1 ALT3 OUT>;
- mrst = <&pio34 2 ALT3 IN>;
- scl = <&pio34 0 ALT3 OUT>;
- };
- };
-
- pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
- st,pins {
- mtsr = <&pio34 1 ALT3 BIDIR_PU>;
- scl = <&pio34 0 ALT3 OUT>;
- };
- };
- };
-
- i2s_out {
- pinctrl_i2s_8ch_out: i2s_8ch_out{
- st,pins {
- mclk = <&pio33 5 ALT1 OUT>;
- lrclk = <&pio33 7 ALT1 OUT>;
- sclk = <&pio33 6 ALT1 OUT>;
- data0 = <&pio33 4 ALT1 OUT>;
- data1 = <&pio34 0 ALT1 OUT>;
- data2 = <&pio34 1 ALT1 OUT>;
- data3 = <&pio34 2 ALT1 OUT>;
- };
- };
-
- pinctrl_i2s_2ch_out: i2s_2ch_out{
- st,pins {
- mclk = <&pio33 5 ALT1 OUT>;
- lrclk = <&pio33 7 ALT1 OUT>;
- sclk = <&pio33 6 ALT1 OUT>;
- data0 = <&pio33 4 ALT1 OUT>;
- };
- };
- };
-
- i2s_in {
- pinctrl_i2s_8ch_in: i2s_8ch_in{
- st,pins {
- mclk = <&pio32 5 ALT1 IN>;
- lrclk = <&pio32 7 ALT1 IN>;
- sclk = <&pio32 6 ALT1 IN>;
- data0 = <&pio32 4 ALT1 IN>;
- data1 = <&pio33 0 ALT1 IN>;
- data2 = <&pio33 1 ALT1 IN>;
- data3 = <&pio33 2 ALT1 IN>;
- data4 = <&pio33 3 ALT1 IN>;
- };
- };
-
- pinctrl_i2s_2ch_in: i2s_2ch_in{
- st,pins {
- mclk = <&pio32 5 ALT1 IN>;
- lrclk = <&pio32 7 ALT1 IN>;
- sclk = <&pio32 6 ALT1 IN>;
- data0 = <&pio32 4 ALT1 IN>;
- };
- };
- };
-
- spdif_out {
- pinctrl_spdif_out: spdif_out{
- st,pins {
- spdif_out = <&pio34 7 ALT1 OUT>;
- };
- };
- };
-
- serial3 {
- pinctrl_serial3: serial3-0 {
- st,pins {
- tx = <&pio31 3 ALT1 OUT>;
- rx = <&pio31 4 ALT1 IN>;
- };
- };
- };
- };
-
- pin-controller-flash@923f080 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih407-flash-pinctrl";
- st,syscfg = <&syscfg_flash>;
- reg = <0x0923f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0x09230000 0x3000>;
-
- pio40: gpio@9230000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO40";
- };
- pio41: gpio@9231000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x100>;
- st,bank-name = "PIO41";
- };
- pio42: gpio@9232000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x100>;
- st,bank-name = "PIO42";
- };
-
- mmc0 {
- pinctrl_mmc0: mmc0-0 {
- st,pins {
- emmc_clk = <&pio40 6 ALT1 BIDIR>;
- emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
- emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
- emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
- emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
- emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
- emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
- emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
- emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
- emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
- };
- };
- pinctrl_sd0: sd0-0 {
- st,pins {
- sd_clk = <&pio40 6 ALT1 BIDIR>;
- sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
- sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
- sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
- sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
- sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
- sd_led = <&pio42 0 ALT2 OUT>;
- sd_pwren = <&pio42 2 ALT2 OUT>;
- sd_vsel = <&pio42 3 ALT2 OUT>;
- sd_cd = <&pio42 4 ALT2 IN>;
- sd_wp = <&pio42 5 ALT2 IN>;
- };
- };
- };
-
- fsm {
- pinctrl_fsm: fsm {
- st,pins {
- spi-fsm-clk = <&pio40 1 ALT1 OUT>;
- spi-fsm-cs = <&pio40 0 ALT1 OUT>;
- spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
- spi-fsm-miso = <&pio40 3 ALT1 IN>;
- spi-fsm-hol = <&pio40 5 ALT1 OUT>;
- spi-fsm-wp = <&pio40 4 ALT1 OUT>;
- };
- };
- };
-
- nand {
- pinctrl_nand: nand {
- st,pins {
- nand_cs1 = <&pio40 6 ALT3 OUT>;
- nand_cs0 = <&pio40 7 ALT3 OUT>;
- nand_d0 = <&pio41 0 ALT3 BIDIR>;
- nand_d1 = <&pio41 1 ALT3 BIDIR>;
- nand_d2 = <&pio41 2 ALT3 BIDIR>;
- nand_d3 = <&pio41 3 ALT3 BIDIR>;
- nand_d4 = <&pio41 4 ALT3 BIDIR>;
- nand_d5 = <&pio41 5 ALT3 BIDIR>;
- nand_d6 = <&pio41 6 ALT3 BIDIR>;
- nand_d7 = <&pio41 7 ALT3 BIDIR>;
- nand_we = <&pio42 0 ALT3 OUT>;
- nand_dqs = <&pio42 1 ALT3 OUT>;
- nand_ale = <&pio42 2 ALT3 OUT>;
- nand_cle = <&pio42 3 ALT3 OUT>;
- nand_rnb = <&pio42 4 ALT3 IN>;
- nand_oe = <&pio42 5 ALT3 OUT>;
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi
index e9d7ec9..1aa0a58 100644
--- a/arch/arm/dts/stih410-b2260-u-boot.dtsi
+++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi
@@ -7,37 +7,35 @@
/{
soc {
- st_dwc3: dwc3@8f94000 {
- dwc3: dwc3@9900000 {
- dr_mode = "peripheral";
- phys = <&usb2_picophy0>;
- };
- };
-
clk_usb: clk-usb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
+ };
+};
- ohci0: usb@9a03c00 {
- compatible = "generic-ohci";
- clocks = <&clk_usb>;
- };
+&dwc3 {
+ dr_mode = "peripheral";
+ phys = <&usb2_picophy0>;
+};
- ehci0: usb@9a03e00 {
- compatible = "generic-ehci";
- clocks = <&clk_usb>;
- };
+&ehci0 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
+};
- ohci1: usb@9a83c00 {
- compatible = "generic-ohci";
- clocks = <&clk_usb>;
- };
+&ehci1 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
+};
- ehci1: usb@9a83e00 {
- compatible = "generic-ehci";
- clocks = <&clk_usb>;
- };
- };
+&ohci0 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
+};
+
+&ohci1 {
+ compatible = "st,st-ehci-300x", "generic-ehci";
+ clocks = <&clk_usb>;
};
diff --git a/arch/arm/dts/stih410-b2260.dts b/arch/arm/dts/stih410-b2260.dts
deleted file mode 100644
index 8c4155b..0000000
--- a/arch/arm/dts/stih410-b2260.dts
+++ /dev/null
@@ -1,214 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016 STMicroelectronics (R&D) Limited.
- * Author: Patrice Chotard <patrice.chotard@foss.st.com>
- */
-/dts-v1/;
-#include "stih410.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STiH410 B2260";
- compatible = "st,stih410-b2260", "st,stih410";
-
- chosen {
- bootargs = "clk_ignore_unused";
- stdout-path = &uart1;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x40000000>;
- };
-
- aliases {
- serial1 = &uart1;
- ethernet0 = ðernet0;
- };
-
- leds {
- compatible = "gpio-leds";
- user_green_1 {
- label = "User_green_1";
- gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- user_green_2 {
- label = "User_green_2";
- gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- user_green_3 {
- label = "User_green_3";
- gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- user_green_4 {
- label = "User_green_4";
- gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- sound: sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "STI-B2260";
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- simple-audio-card,dai-link@0 {
- reg = <0>;
- /* DAC */
- format = "i2s";
- mclk-fs = <128>;
- cpu {
- sound-dai = <&sti_uni_player0>;
- };
-
- codec {
- sound-dai = <&sti_hdmi>;
- };
- };
- };
-
- soc {
- /* Low speed expansion connector */
- uart0: serial@9830000 {
- label = "LS-UART0";
- pinctrl-names = "default", "no-hw-flowctrl";
- pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>;
- pinctrl-1 = <&pinctrl_serial0>;
- rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
- };
-
- /* Low speed expansion connector */
- uart1: serial@9831000 {
- label = "LS-UART1";
- status = "okay";
- };
-
- /* Low speed expansion connector */
- spi0: spi@9844000 {
- label = "LS-SPI0";
- cs-gpios = <&pio30 3 0>;
- status = "okay";
- };
-
- /* Low speed expansion connector */
- i2c0: i2c@9840000 {
- label = "LS-I2C0";
- status = "okay";
- };
-
- /* Low speed expansion connector */
- i2c1: i2c@9841000 {
- label = "LS-I2C1";
- status = "okay";
- };
-
- /* high speed expansion connector */
- i2c2: i2c@9842000 {
- label = "HS-I2C2";
- pinctrl-0 = <&pinctrl_i2c2_alt2_1>;
- status = "okay";
- };
-
- /* high speed expansion connector */
- i2c3: i2c@9843000 {
- label = "HS-I2C3";
- pinctrl-0 = <&pinctrl_i2c3_alt3_0>;
- status = "okay";
- };
-
- mmc0: sdhci@9060000 {
- pinctrl-0 = <&pinctrl_sd0>;
- bus-width = <4>;
- status = "okay";
- };
-
- /* high speed expansion connector */
- mmc1: sdhci@9080000 {
- status = "okay";
- };
-
- pwm0: pwm@9810000 {
- status = "okay";
- };
-
- pwm1: pwm@9510000 {
- status = "okay";
- };
-
- usb2_picophy1: phy2@0 {
- status = "okay";
- };
-
- usb2_picophy2: phy3@0 {
- status = "okay";
- };
-
- ohci0: usb@9a03c00 {
- status = "okay";
- };
-
- ehci0: usb@9a03e00 {
- status = "okay";
- };
-
- ohci1: usb@9a83c00 {
- status = "okay";
- };
-
- ehci1: usb@9a83e00 {
- status = "okay";
- };
-
- st_dwc3: dwc3@8f94000 {
- status = "okay";
- };
-
- ethernet0: dwmac@9630000 {
- phy-mode = "rgmii";
- pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
-
- snps,phy-bus-name = "stmmac";
- snps,phy-bus-id = <0>;
- snps,phy-addr = <0>;
- snps,reset-gpio = <&pio0 7 0>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 1000000>;
-
- status = "okay";
- };
-
- sti_uni_player0: sti-uni-player@8d80000 {
- status = "okay";
- };
- /* SSC11 to HDMI */
- hdmiddc: i2c@9541000 {
- /* HDMI V1.3a supports Standard mode only */
- clock-frequency = <100000>;
- st,i2c-min-scl-pulse-width-us = <0>;
- st,i2c-min-sda-pulse-width-us = <5>;
- status = "okay";
- };
-
- miphy28lp_phy: miphy28lp@0 {
-
- phy_port1: port@9b2a000 {
- st,osc-force-ext;
- };
- };
-
- sata1: sata@9b28000 {
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/stih410-clock.dtsi b/arch/arm/dts/stih410-clock.dtsi
deleted file mode 100644
index 81a8c25..0000000
--- a/arch/arm/dts/stih410-clock.dtsi
+++ /dev/null
@@ -1,333 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics R&D Limited
- */
-#include <dt-bindings/clock/stih410-clks.h>
-/ {
- /*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- clock-output-names = "CLK_SYSIN";
- };
-
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- compatible = "st,stih410-clk", "simple-bus";
-
- /*
- * A9 PLL.
- */
- clockgen-a9@92b0000 {
- compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
-
- clockgen_a9_pll: clockgen-a9-pll {
- #clock-cells = <1>;
- compatible = "st,stih407-clkgen-plla9";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
- };
- };
-
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@92b0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
-
- clockgen-a@90ff000 {
- compatible = "st,clkgen-c32";
- reg = <0x90ff000 0x1000>;
-
- clk_s_a0_pll: clk-s-a0-pll {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
- };
-
- clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
-
- #clock-cells = <1>;
-
- clocks = <&clk_s_a0_pll 0>,
- <&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
- "clk-ic-lmi1";
- clock-critical = <CLK_IC_LMI0>;
- };
- };
-
- clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
- "clk-s-c0-fs0-ch1",
- "clk-s-c0-fs0-ch2",
- "clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
- };
-
- clk_s_c0: clockgen-c@9103000 {
- compatible = "st,clkgen-c32";
- reg = <0x9103000 0x1000>;
-
- clk_s_c0_pll0: clk-s-c0-pll0 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll0";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
- };
-
- clk_s_c0_pll1: clk-s-c0-pll1 {
- #clock-cells = <1>;
- compatible = "st,clkgen-pll1";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
- };
-
- clk_s_c0_flexgen: clk-s-c0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_c0_pll0 0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_quadfs 0>,
- <&clk_s_c0_quadfs 1>,
- <&clk_s_c0_quadfs 2>,
- <&clk_s_c0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-icn-gpu",
- "clk-fdma",
- "clk-nand",
- "clk-hva",
- "clk-proc-stfe",
- "clk-proc-tp",
- "clk-rx-icn-dmu",
- "clk-rx-icn-hva",
- "clk-icn-cpu",
- "clk-tx-icn-dmu",
- "clk-mmc-0",
- "clk-mmc-1",
- "clk-jpegdec",
- "clk-ext2fa9",
- "clk-ic-bdisp-0",
- "clk-ic-bdisp-1",
- "clk-pp-dmu",
- "clk-vid-dmu",
- "clk-dss-lpc",
- "clk-st231-aud-0",
- "clk-st231-gp-1",
- "clk-st231-dmu",
- "clk-icn-lmi",
- "clk-tx-icn-disp-1",
- "clk-icn-sbc",
- "clk-stfe-frc2",
- "clk-eth-phy",
- "clk-eth-ref-phyclk",
- "clk-flash-promip",
- "clk-main-disp",
- "clk-aux-disp",
- "clk-compo-dvp",
- "clk-tx-icn-hades",
- "clk-rx-icn-hades",
- "clk-icn-reg-16",
- "clk-pp-hades",
- "clk-clust-hades",
- "clk-hwpe-hades",
- "clk-fc-hades";
- clock-critical = <CLK_PROC_STFE>,
- <CLK_ICN_CPU>,
- <CLK_TX_ICN_DMU>,
- <CLK_EXT2F_A9>,
- <CLK_ICN_LMI>,
- <CLK_ICN_SBC>;
-
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
- };
- };
-
- clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
- "clk-s-d0-fs0-ch1",
- "clk-s-d0-fs0-ch2",
- "clk-s-d0-fs0-ch3";
- };
-
- clockgen-d0@9104000 {
- compatible = "st,clkgen-c32";
- reg = <0x9104000 0x1000>;
-
- clk_s_d0_flexgen: clk-s-d0-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-audio", "st,flexgen";
-
- clocks = <&clk_s_d0_quadfs 0>,
- <&clk_s_d0_quadfs 1>,
- <&clk_s_d0_quadfs 2>,
- <&clk_s_d0_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-pcm-0",
- "clk-pcm-1",
- "clk-pcm-2",
- "clk-spdiff",
- "clk-pcmr10-master",
- "clk-usb2-phy";
- };
- };
-
- clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
- "clk-s-d2-fs0-ch1",
- "clk-s-d2-fs0-ch2",
- "clk-s-d2-fs0-ch3";
- };
-
- clockgen-d2@9106000 {
- compatible = "st,clkgen-c32";
- reg = <0x9106000 0x1000>;
-
- clk_s_d2_flexgen: clk-s-d2-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen-video", "st,flexgen";
-
- clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_d2_quadfs 2>,
- <&clk_s_d2_quadfs 3>,
- <&clk_sysin>,
- <&clk_sysin>,
- <&clk_tmdsout_hdmi>;
-
- clock-output-names = "clk-pix-main-disp",
- "clk-pix-pip",
- "clk-pix-gdp1",
- "clk-pix-gdp2",
- "clk-pix-gdp3",
- "clk-pix-gdp4",
- "clk-pix-aux-disp",
- "clk-denc",
- "clk-pix-hddac",
- "clk-hddac",
- "clk-sddac",
- "clk-pix-dvo",
- "clk-dvo",
- "clk-pix-hdmi",
- "clk-tmds-hdmi",
- "clk-ref-hdmiphy";
- };
- };
-
- clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
- #clock-cells = <1>;
- compatible = "st,quadfs";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
- "clk-s-d3-fs0-ch1",
- "clk-s-d3-fs0-ch2",
- "clk-s-d3-fs0-ch3";
- };
-
- clockgen-d3@9107000 {
- compatible = "st,clkgen-c32";
- reg = <0x9107000 0x1000>;
-
- clk_s_d3_flexgen: clk-s-d3-flexgen {
- #clock-cells = <1>;
- compatible = "st,flexgen";
-
- clocks = <&clk_s_d3_quadfs 0>,
- <&clk_s_d3_quadfs 1>,
- <&clk_s_d3_quadfs 2>,
- <&clk_s_d3_quadfs 3>,
- <&clk_sysin>;
-
- clock-output-names = "clk-stfe-frc1",
- "clk-tsout-0",
- "clk-tsout-1",
- "clk-mchi",
- "clk-vsens-compo",
- "clk-frc1-remote",
- "clk-lpc-0",
- "clk-lpc-1";
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih410-pinctrl.dtsi b/arch/arm/dts/stih410-pinctrl.dtsi
deleted file mode 100644
index e6eadd1..0000000
--- a/arch/arm/dts/stih410-pinctrl.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Peter Griffin <peter.griffin@linaro.org>
- */
-#include "st-pincfg.h"
-/ {
-
- soc {
- pin-controller-rear@922f080 {
-
- usb0 {
- pinctrl_usb0: usb2-0 {
- st,pins {
- usb-oc-detect = <&pio35 0 ALT1 IN>;
- usb-pwr-enable = <&pio35 1 ALT1 OUT>;
- };
- };
- };
-
- usb1 {
- pinctrl_usb1: usb2-1 {
- st,pins {
- usb-oc-detect = <&pio35 2 ALT1 IN>;
- usb-pwr-enable = <&pio35 3 ALT1 OUT>;
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stih410.dtsi b/arch/arm/dts/stih410.dtsi
deleted file mode 100644
index 6d84701..0000000
--- a/arch/arm/dts/stih410.dtsi
+++ /dev/null
@@ -1,300 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Peter Griffin <peter.griffin@linaro.org>
- */
-#include "stih410-clock.dtsi"
-#include "stih407-family.dtsi"
-#include "stih410-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-/ {
- aliases {
- bdisp0 = &bdisp0;
- };
-
- soc {
- usb2_picophy1: phy2@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xf8 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY0_RESET>;
- reset-names = "global", "port";
-
- status = "disabled";
- };
-
- usb2_picophy2: phy3@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0 0>;
- #phy-cells = <0>;
- st,syscfg = <&syscfg_core 0xfc 0xf4>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY1_RESET>;
- reset-names = "global", "port";
-
- status = "disabled";
- };
-
- ohci0: usb@9a03c00 {
- compatible = "st,st-ohci-300x";
- reg = <0x9a03c00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
- <&softreset STIH407_USB2_PORT0_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy1>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- ehci0: usb@9a03e00 {
- compatible = "st,st-ehci-300x";
- reg = <0x9a03e00 0x100>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
- <&softreset STIH407_USB2_PORT0_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy1>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- ohci1: usb@9a83c00 {
- compatible = "st,st-ohci-300x";
- reg = <0x9a83c00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
- <&softreset STIH407_USB2_PORT1_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy2>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- ehci1: usb@9a83e00 {
- compatible = "st,st-ehci-300x";
- reg = <0x9a83e00 0x100>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
- <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
- <&softreset STIH407_USB2_PORT1_SOFTRESET>;
- reset-names = "power", "softreset";
- phys = <&usb2_picophy2>;
- phy-names = "usb";
-
- status = "disabled";
- };
-
- sti-display-subsystem@0 {
- compatible = "st,sti-display-subsystem";
- #address-cells = <1>;
- #size-cells = <1>;
-
- reg = <0 0>;
- assigned-clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_c0_flexgen CLK_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_GDP1>,
- <&clk_s_d2_flexgen CLK_PIX_GDP2>,
- <&clk_s_d2_flexgen CLK_PIX_GDP3>,
- <&clk_s_d2_flexgen CLK_PIX_GDP4>;
-
- assigned-clock-parents = <0>,
- <0>,
- <0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>;
-
- assigned-clock-rates = <297000000>,
- <297000000>,
- <0>,
- <400000000>,
- <400000000>;
-
- ranges;
-
- sti-compositor@9d11000 {
- compatible = "st,stih407-compositor";
- reg = <0x9d11000 0x1000>;
-
- clock-names = "compo_main",
- "compo_aux",
- "pix_main",
- "pix_aux",
- "pix_gdp1",
- "pix_gdp2",
- "pix_gdp3",
- "pix_gdp4",
- "main_parent",
- "aux_parent";
-
- clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_GDP1>,
- <&clk_s_d2_flexgen CLK_PIX_GDP2>,
- <&clk_s_d2_flexgen CLK_PIX_GDP3>,
- <&clk_s_d2_flexgen CLK_PIX_GDP4>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
-
- reset-names = "compo-main", "compo-aux";
- resets = <&softreset STIH407_COMPO_SOFTRESET>,
- <&softreset STIH407_COMPO_SOFTRESET>;
- st,vtg = <&vtg_main>, <&vtg_aux>;
- };
-
- sti-tvout@8d08000 {
- compatible = "st,stih407-tvout";
- reg = <0x8d08000 0x1000>;
- reg-names = "tvout-reg";
- reset-names = "tvout";
- resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
- #address-cells = <1>;
- #size-cells = <1>;
- assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
- <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
- <&clk_s_d0_flexgen CLK_PCM_0>,
- <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
- <&clk_s_d2_flexgen CLK_HDDAC>;
-
- assigned-clock-parents = <&clk_s_d2_quadfs 0>,
- <&clk_tmdsout_hdmi>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d0_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>;
- };
-
- sti_hdmi: sti-hdmi@8d04000 {
- compatible = "st,stih407-hdmi";
- reg = <0x8d04000 0x1000>;
- reg-names = "hdmi-reg";
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq";
- clock-names = "pix",
- "tmds",
- "phy",
- "audio",
- "main_parent",
- "aux_parent";
-
- clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
- <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
- <&clk_s_d0_flexgen CLK_PCM_0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
-
- hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
- reset-names = "hdmi";
- resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
- ddc = <&hdmiddc>;
- };
-
- sti-hda@8d02000 {
- compatible = "st,stih407-hda";
- status = "disabled";
- reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
- reg-names = "hda-reg", "video-dacs-ctrl";
- clock-names = "pix",
- "hddac",
- "main_parent",
- "aux_parent";
- clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
- <&clk_s_d2_flexgen CLK_HDDAC>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
- };
-
- sti-hqvdp@9c00000 {
- compatible = "st,stih407-hqvdp";
- reg = <0x9C00000 0x100000>;
- clock-names = "hqvdp", "pix_main";
- clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
- reset-names = "hqvdp";
- resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
- st,vtg = <&vtg_main>;
- };
- };
-
- bdisp0:bdisp@9f10000 {
- compatible = "st,stih407-bdisp";
- reg = <0x9f10000 0x1000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "bdisp";
- clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
- };
-
- hva@8c85000 {
- compatible = "st,st-hva";
- reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
- reg-names = "hva_registers", "hva_esram";
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "clk_hva";
- clocks = <&clk_s_c0_flexgen CLK_HVA>;
- };
-
- thermal@91a0000 {
- compatible = "st,stih407-thermal";
- reg = <0x91a0000 0x28>;
- clock-names = "thermal";
- clocks = <&clk_sysin>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
- };
-
- delta0@0 {
- compatible = "st,st-delta";
- clock-names = "delta",
- "delta-st231",
- "delta-flash-promip";
- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
- <&clk_s_c0_flexgen CLK_ST231_DMU>,
- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
- };
-
- sti-cec@94a087c {
- compatible = "st,stih-cec";
- reg = <0x94a087c 0x64>;
- clocks = <&clk_sysin>;
- clock-names = "cec-clk";
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cec-irq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_cec0_default>;
- resets = <&softreset STIH407_LPM_SOFTRESET>;
- hdmi-phandle = <&sti_hdmi>;
- };
- };
-};
diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts
deleted file mode 100644
index 592b182..0000000
--- a/arch/arm/dts/stm32429i-eval.dts
+++ /dev/null
@@ -1,284 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
- * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STMicroelectronics STM32429i-EVAL board";
- compatible = "st,stm32429i-eval", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@00000000 {
- device_type = "memory";
- reg = <0x00000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vref: regulator-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_panel: vdd-panel {
- compatible = "regulator-fixed";
- regulator-name = "vdd_panel";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpiog 6 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- gpios = <&gpiog 7 1>;
- };
- led-red {
- gpios = <&gpiog 10 1>;
- };
- led-blue {
- gpios = <&gpiog 12 1>;
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- autorepeat;
- button@0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 0>;
- };
- button@1 {
- label = "Tamper";
- linux,code = <KEY_RESTART>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- usbotg_hs_phy: usbphy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- panel_rgb: panel-rgb {
- compatible = "ampire,am-480272h3tmqw-t01h";
- power-supply = <&vdd_panel>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc3_in8_pin>;
- vdda-supply = <&vdda>;
- vref-supply = <&vref>;
- status = "okay";
- adc3: adc@200 {
- st,adc-channels = <8>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov2640_0>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ov2640: camera@30 {
- compatible = "ovti,ov2640";
- reg = <0x30>;
- resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
- pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
- clocks = <&clk_ext_camera>;
- clock-names = "xvclk";
- status = "okay";
-
- port {
- ov2640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- };
- };
- };
-
- stmpe1600: stmpe1600@42 {
- compatible = "st,stmpe1600";
- reg = <0x42>;
- interrupts = <8 3>;
- interrupt-parent = <&gpioi>;
- interrupt-controller;
- wakeup-source;
-
- stmpegpio: stmpe_gpio {
- compatible = "st,stmpe-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-};
-
-&iwdg {
- status = "okay";
- timeout-sec = <32>;
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&mac {
- status = "okay";
- pinctrl-0 = <ðernet_mii>;
- pinctrl-names = "default";
- phy-mode = "mii";
- phy-handle = <&phy1>;
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
- max-frequency = <12500000>;
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts
deleted file mode 100644
index 0e6445a..0000000
--- a/arch/arm/dts/stm32746g-eval.dts
+++ /dev/null
@@ -1,186 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "STMicroelectronics STM32746g-EVAL board";
- compatible = "st,stm32746g-eval", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpiof 10 1>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- gpios = <&stmfx_pinctrl 17 1>;
- };
- led-red {
- gpios = <&gpiob 7 1>;
- };
- led-blue {
- gpios = <&stmfx_pinctrl 19 1>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "Wake up";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioc 13 0>;
- };
- };
-
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
- bias-pull-up;
- };
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi
deleted file mode 100644
index 0adc41b..0000000
--- a/arch/arm/dts/stm32f4-pinctrl.dtsi
+++ /dev/null
@@ -1,447 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_b: usbotg-fs-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
- <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
- <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- ethernet_mii: mii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
- <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
- <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
- <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
- <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
- slew-rate = <2>;
- };
- };
-
- adc3_in8_pin: adc-200 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
- };
- };
-
- pwm1_pins: pwm1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
- <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
- <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
- };
- };
-
- pwm3_pins: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
- <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
- };
- };
-
- i2c1_pins: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
- <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- ltdc_pins_b: ltdc-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, AF14)>,
- /* LCD_HSYNC */
- <STM32_PINMUX('A', 4, AF14)>,
- /* LCD_VSYNC */
- <STM32_PINMUX('G', 7, AF14)>,
- /* LCD_CLK */
- <STM32_PINMUX('C', 10, AF14)>,
- /* LCD_R2 */
- <STM32_PINMUX('B', 0, AF9)>,
- /* LCD_R3 */
- <STM32_PINMUX('A', 11, AF14)>,
- /* LCD_R4 */
- <STM32_PINMUX('A', 12, AF14)>,
- /* LCD_R5 */
- <STM32_PINMUX('B', 1, AF9)>,
- /* LCD_R6*/
- <STM32_PINMUX('G', 6, AF14)>,
- /* LCD_R7 */
- <STM32_PINMUX('A', 6, AF14)>,
- /* LCD_G2 */
- <STM32_PINMUX('G', 10, AF9)>,
- /* LCD_G3 */
- <STM32_PINMUX('B', 10, AF14)>,
- /* LCD_G4 */
- <STM32_PINMUX('D', 6, AF14)>,
- /* LCD_B2 */
- <STM32_PINMUX('G', 11, AF14)>,
- /* LCD_B3*/
- <STM32_PINMUX('B', 11, AF14)>,
- /* LCD_G5 */
- <STM32_PINMUX('C', 7, AF14)>,
- /* LCD_G6 */
- <STM32_PINMUX('D', 3, AF14)>,
- /* LCD_G7 */
- <STM32_PINMUX('G', 12, AF9)>,
- /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>,
- /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>,
- /* LCD_B6 */
- <STM32_PINMUX('B', 9, AF14)>,
- /* LCD_B7 */
- <STM32_PINMUX('F', 10, AF14)>;
- /* LCD_DE */
- slew-rate = <2>;
- };
- };
-
- spi5_pins: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF5)>,
- /* SPI5_CLK */
- <STM32_PINMUX('F', 9, AF5)>;
- /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 8, AF5)>;
- /* SPI5_MISO */
- bias-disable;
- };
- };
-
- i2c3_pins: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 9, AF4)>,
- /* I2C3_SDA */
- <STM32_PINMUX('A', 8, AF4)>;
- /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <3>;
- };
- };
-
- dcmi_pins: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
- <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
- <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
- <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
- <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
- <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
- <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
- <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
- <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
- <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- sdio_pins: sdio-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od: sdio-pins-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts
deleted file mode 100644
index 30daabd..0000000
--- a/arch/arm/dts/stm32f429-disco.dts
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- */
-
-/dts-v1/;
-#include "stm32f429.dtsi"
-#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STMicroelectronics STM32F429i-DISCO board";
- compatible = "st,stm32f429i-disco", "st,stm32f429";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@90000000 {
- device_type = "memory";
- reg = <0x90000000 0x800000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- gpios = <&gpiog 14 0>;
- };
- led-green {
- gpios = <&gpiog 13 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 0>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpioc 4 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&crc {
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <100000>;
- status = "okay";
-
- stmpe811@41 {
- compatible = "st,stmpe811";
- reg = <0x41>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpioa>;
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
-
- stmpe_touchscreen {
- compatible = "st,stmpe-ts";
- /* 8 sample average control */
- st,ave-ctrl = <3>;
- /* 7 length fractional part in z */
- st,fraction-z = <7>;
- /*
- * 50 mA typical 80 mA max touchscreen drivers
- * current limit value
- */
- st,i-drive = <1>;
- /* 1 ms panel driver settling time */
- st,settling = <3>;
- /* 5 ms touch detect interrupt delay */
- st,touch-det-delay = <5>;
- };
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- /* forbid to use ADC channels 3-0 (touch) */
- st,norequest-mask = <0x0F>;
- };
- };
-};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins_b>;
- pinctrl-names = "default";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&rtc {
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSI>;
- status = "okay";
-};
-
-&spi5 {
- status = "okay";
- pinctrl-0 = <&spi5_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
-
- l3gd20: l3gd20@0 {
- compatible = "st,l3gd20-gyro";
- spi-max-frequency = <10000000>;
- st,drdy-int-pin = <2>;
- interrupt-parent = <&gpioa>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>,
- <2 IRQ_TYPE_EDGE_RISING>;
- reg = <0>;
- status = "okay";
- };
-
- display: display@1{
- /* Connect panel-ilitek-9341 to ltdc */
- compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
- reg = <1>;
- spi-3wire;
- spi-max-frequency = <10000000>;
- dc-gpios = <&gpiod 13 0>;
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- compatible = "st,stm32f4x9-fsotg";
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi
deleted file mode 100644
index 5be171e..0000000
--- a/arch/arm/dts/stm32f429-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f429-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi
deleted file mode 100644
index 8133ea1..0000000
--- a/arch/arm/dts/stm32f429.dtsi
+++ /dev/null
@@ -1,758 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f4-rcc.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- romem: efuse@1fff7800 {
- compatible = "st,stm32f4-otp";
- reg = <0x1fff7800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- ts_cal1: calib@22c {
- reg = <0x22c 0x2>;
- };
- ts_cal2: calib@22e {
- reg = <0x22e 0x2>;
- };
- };
-
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- iwdg: watchdog@40003000 {
- compatible = "st,stm32-iwdg";
- reg = <0x40003000 0x400>;
- clocks = <&clk_lsi>;
- clock-names = "lsi";
- status = "disabled";
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
- status = "disabled";
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
- status = "disabled";
- dmas = <&dma1 1 4 0x400 0x0>,
- <&dma1 3 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f4-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- gcan: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32f4-dac-core";
- reg = <0x40007400 0x400>;
- resets = <&rcc STM32F4_APB1_RESET(DAC)>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
- status = "disabled";
- dmas = <&dma2 2 4 0x400 0x0>,
- <&dma2 7 4 0x400 0x0>;
- dma-names = "rx", "tx";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
- status = "disabled";
- };
-
- adc: adc@40012000 {
- compatible = "st,stm32f4-adc-core";
- reg = <0x40012000 0x400>;
- interrupts = <18>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- clock-names = "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
- interrupt-parent = <&adc>;
- interrupts = <0>;
- dmas = <&dma2 0 0 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
- interrupt-parent = <&adc>;
- interrupts = <1>;
- dmas = <&dma2 3 1 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc3: adc@200 {
- compatible = "st,stm32f4-adc";
- #io-channel-cells = <1>;
- reg = <0x200>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
- interrupt-parent = <&adc>;
- interrupts = <2>;
- dmas = <&dma2 1 2 0x400 0x0>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- sdio: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
- dmas = <&dma2 3 2 0x400 0x0>,
- <&dma2 4 2 0x400 0x0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi6: spi@40015400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32f4-spi";
- reg = <0x40015400 0x400>;
- interrupts = <86>;
- clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f4-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
- <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- snps,mixed-burst;
- status = "disabled";
- };
-
- dma2d: dma2d@4002b000 {
- compatible = "st,stm32-dma2d";
- reg = <0x4002b000 0xc00>;
- interrupts = <90>;
- resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
- clock-names = "dma2d";
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "snps,dwc2";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 39>;
- clock-names = "otg";
- status = "disabled";
- };
-
- dcmi: dcmi@50050000 {
- compatible = "st,stm32-dcmi";
- reg = <0x50050000 0x400>;
- interrupts = <78>;
- resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
- clock-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&dcmi_pins>;
- dmas = <&dma2 1 1 0x414 0x3>;
- dma-names = "tx";
- status = "disabled";
- };
-
- rng: rng@50060800 {
- compatible = "st,stm32-rng";
- reg = <0x50060800 0x400>;
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
-
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 SYSTICK>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts
deleted file mode 100644
index c9acabf..0000000
--- a/arch/arm/dts/stm32f469-disco.dts
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
- *
- */
-
-/dts-v1/;
-#include "stm32f469.dtsi"
-#include "stm32f469-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "STMicroelectronics STM32F469i-DISCO board";
- compatible = "st,stm32f469i-disco", "st,stm32f469";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x1000000>;
- };
-
- aliases {
- serial0 = &usart3;
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_dsi: vdd-dsi {
- compatible = "regulator-fixed";
- regulator-name = "vdd_dsi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- soc {
- dma-ranges = <0xc0000000 0x0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- led-orange {
- gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
- };
- led-red {
- gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
- };
- led-blue {
- gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- /* This turns on vbus for otg for host mode (dwc2) */
- vcc5v_otg: vcc5v-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-};
-
-&rcc {
- compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
-};
-
-&clk_hse {
- clock-frequency = <8000000>;
-};
-
-&dma2d {
- status = "okay";
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_out_dsi>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&dsi_panel_in>;
- };
- };
- };
-
- panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>; /* dsi virtual channel (0..3) */
- reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
- power-supply = <&vdd_dsi>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_out_dsi: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&timers1 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- status = "okay";
-
- pwm {
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- timer@2 {
- status = "okay";
- };
-};
-
-&sdio {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_pins_od>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart3 {
- pinctrl-0 = <&usart3_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi
deleted file mode 100644
index 0610407..0000000
--- a/arch/arm/dts/stm32f469-pinctrl.dtsi
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32f4-pinctrl.dtsi"
-
-&pinctrl {
- compatible = "st,stm32f469-pinctrl";
-
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 6>,
- <&pinctrl 12 156 4>;
- };
-
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 3 163 5>;
- };
-};
diff --git a/arch/arm/dts/stm32f469.dtsi b/arch/arm/dts/stm32f469.dtsi
deleted file mode 100644
index 5f6a797..0000000
--- a/arch/arm/dts/stm32f469.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
-
-#include "stm32f429.dtsi"
-
-/ {
- soc {
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- resets = <&rcc STM32F4_APB2_RESET(DSI)>;
- reset-names = "apb";
- clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
- clock-names = "pclk", "ref";
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi
deleted file mode 100644
index d3706ee..0000000
--- a/arch/arm/dts/stm32f7-pinctrl.dtsi
+++ /dev/null
@@ -1,415 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/ {
- soc {
- pinctrl: pinctrl@40020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
- slew-rate = <0>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- i2c1_pins_b: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
- <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c3_pins_a: i2c3-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
- <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_b: usbotg-hs-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_a: sdio-pins-a-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_a: sdio-pins-od-a-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_b: sdio-pins-b-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- sdio_pins_od_b: sdio-pins-od-b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
- <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
- drive-open-drain;
- slew-rate = <2>;
- };
- };
-
- can1_pins_a: can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_b: can1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
- bias-pull-up;
- };
- };
-
- can1_pins_c: can1-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can1_pins_d: can1-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
- bias-pull-up;
-
- };
- };
-
- can2_pins_a: can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can2_pins_b: can2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_a: can3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- can3_pins_b: can3-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
- bias-pull-up;
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
- <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
- slew-rate = <2>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 38d797e..8ea4ea6 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -24,11 +24,6 @@
};
};
-<dc {
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
- bootph-all;
-};
-
&fmc {
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
@@ -53,8 +48,14 @@
};
};
+<dc {
+ bootph-all;
+
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+};
+
&panel_rgb {
- compatible = "simple-panel";
+ compatible = "rocktech,rk043fn48h", "simple-panel";
display-timings {
timing@0 {
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
deleted file mode 100644
index 4312751..0000000
--- a/arch/arm/dts/stm32f746-disco.dts
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f746-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "STMicroelectronics STM32F746-DISCO board";
- compatible = "st,stm32f746-disco", "st,stm32f746";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x800000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x80000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- /* This turns on vbus for otg fs for host mode (dwc2) */
- vcc5v_otg_fs: vcc5v-otg-fs-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpiod 5 0>;
- regulator-name = "vcc5_host1";
- regulator-always-on;
- };
-
- vcc_3v3: vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- panel_rgb: panel-rgb {
- compatible = "rocktech,rk043fn48h";
- power-supply = <&vcc_3v3>;
- backlight = <&backlight>;
- enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
- status = "okay";
- port {
- panel_in_rgb: endpoint {
- remote-endpoint = <<dc_out_rgb>;
- };
- };
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins_a>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
- status = "okay";
-
- touchscreen@38 {
- compatible = "edt,edt-ft5306";
- reg = <0x38>;
- interrupt-parent = <&gpioi>;
- interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
- touchscreen-size-x = <480>;
- touchscreen-size-y = <272>;
- };
-};
-
-<dc {
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-
- port {
- ltdc_out_rgb: endpoint {
- remote-endpoint = <&panel_in_rgb>;
- };
- };
-};
-
-&sdio1 {
- status = "okay";
- vmmc-supply = <&vcc_3v3>;
- cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins_a>;
- pinctrl-1 = <&sdio_pins_od_a>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_fs {
- dr_mode = "host";
- pinctrl-0 = <&usbotg_fs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "host";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_b>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f746-pinctrl.dtsi b/arch/arm/dts/stm32f746-pinctrl.dtsi
deleted file mode 100644
index fcfd2ac..0000000
--- a/arch/arm/dts/stm32f746-pinctrl.dtsi
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl{
- compatible = "st,stm32f746-pinctrl";
-};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
deleted file mode 100644
index 79dad31..0000000
--- a/arch/arm/dts/stm32f746.dtsi
+++ /dev/null
@@ -1,613 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
- *
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/clock/stm32fx-clock.h>
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_i2s_ckin: clk-i2s-ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- };
- };
-
- soc {
- timers2: timers@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
- };
-
- timers3: timers@40000400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- timers4: timers@40000800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
- };
-
- timers5: timers@40000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
- };
-
- timers6: timers@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
- clock-names = "int";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timers@40001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001400 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
- clock-names = "int";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timers@40001800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001800 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timers@40001c00 {
- compatible = "st,stm32-timers";
- reg = <0x40001C00 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers14: timers@40002000 {
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- rtc: rtc@40002800 {
- compatible = "st,stm32-rtc";
- reg = <0x40002800 0x400>;
- clocks = <&rcc 1 CLK_RTC>;
- assigned-clocks = <&rcc 1 CLK_RTC>;
- assigned-clock-parents = <&rcc 1 CLK_LSE>;
- interrupt-parent = <&exti>;
- interrupts = <17 1>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- can3: can@40003400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40003400 0x200>;
- interrupts = <104>, <105>, <106>, <107>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- st,gcan = <&gcan3>;
- status = "disabled";
- };
-
- gcan3: gcan@40003600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40003600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- clocks = <&rcc 1 CLK_USART2>;
- status = "disabled";
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- clocks = <&rcc 1 CLK_USART3>;
- status = "disabled";
- };
-
- usart4: serial@40004c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- clocks = <&rcc 1 CLK_UART4>;
- status = "disabled";
- };
-
- usart5: serial@40005000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40005000 0x400>;
- interrupts = <53>;
- clocks = <&rcc 1 CLK_UART5>;
- status = "disabled";
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
- clocks = <&rcc 1 CLK_I2C1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
- clocks = <&rcc 1 CLK_I2C2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40005c00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
- clocks = <&rcc 1 CLK_I2C3>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@40006000 {
- compatible = "st,stm32f7-i2c";
- reg = <0x40006000 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
- clocks = <&rcc 1 CLK_I2C4>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@40006400 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006400 0x200>;
- interrupts = <19>, <20>, <21>, <22>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- st,can-primary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- gcan1: gcan@40006600 {
- compatible = "st,stm32f4-gcan", "syscon";
- reg = <0x40006600 0x200>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
- };
-
- can2: can@40006800 {
- compatible = "st,stm32f4-bxcan";
- reg = <0x40006800 0x200>;
- interrupts = <63>, <64>, <65>, <66>;
- interrupt-names = "tx", "rx0", "rx1", "sce";
- resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
- st,can-secondary;
- st,gcan = <&gcan1>;
- status = "disabled";
- };
-
- cec: cec@40006c00 {
- compatible = "st,stm32-cec";
- reg = <0x40006C00 0x400>;
- interrupts = <94>;
- clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
- clock-names = "cec", "hdmi-cec";
- status = "disabled";
- };
-
- usart7: serial@40007800 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007800 0x400>;
- interrupts = <82>;
- clocks = <&rcc 1 CLK_UART7>;
- status = "disabled";
- };
-
- usart8: serial@40007c00 {
- compatible = "st,stm32f7-uart";
- reg = <0x40007c00 0x400>;
- interrupts = <83>;
- clocks = <&rcc 1 CLK_UART8>;
- status = "disabled";
- };
-
- timers1: timers@40010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
- };
-
- timers8: timers@40010400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40010400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- clocks = <&rcc 1 CLK_USART1>;
- status = "disabled";
- };
-
- usart6: serial@40011400 {
- compatible = "st,stm32f7-uart";
- reg = <0x40011400 0x400>;
- interrupts = <71>;
- clocks = <&rcc 1 CLK_USART6>;
- status = "disabled";
- };
-
- sdio2: mmc@40011c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40011c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
- clock-names = "apb_pclk";
- interrupts = <103>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- sdio1: mmc@40012c00 {
- compatible = "arm,pl180", "arm,primecell";
- arm,primecell-periphid = <0x00880180>;
- reg = <0x40012c00 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
- clock-names = "apb_pclk";
- interrupts = <49>;
- max-frequency = <48000000>;
- status = "disabled";
- };
-
- syscfg: syscon@40013800 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x40013800 0x400>;
- };
-
- exti: interrupt-controller@40013c00 {
- compatible = "st,stm32-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40013C00 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
- };
-
- timers9: timers@40014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40014000 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@8 {
- compatible = "st,stm32-timer-trigger";
- reg = <8>;
- status = "disabled";
- };
- };
-
- timers10: timers@40014400 {
- compatible = "st,stm32-timers";
- reg = <0x40014400 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- timers11: timers@40014800 {
- compatible = "st,stm32-timers";
- reg = <0x40014800 0x400>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
- clocks = <&rcc 1 CLK_LCD>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- pwrcfg: power-config@40007000 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x40007000 0x400>;
- };
-
- crc: crc@40023000 {
- compatible = "st,stm32f7-crc";
- reg = <0x40023000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
- status = "disabled";
- };
-
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>;
- compatible = "st,stm32f746-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- clocks = <&clk_hse>, <&clk_i2s_ckin>;
- st,syscfg = <&pwrcfg>;
- assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
- assigned-clock-rates = <1000000>;
- };
-
- dma1: dma-controller@40026000 {
- compatible = "st,stm32-dma";
- reg = <0x40026000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
- #dma-cells = <4>;
- status = "disabled";
- };
-
- dma2: dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
- #dma-cells = <4>;
- st,mem2mem;
- status = "disabled";
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@50000000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x50000000 0x40000>;
- interrupts = <67>;
- clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
- clock-names = "otg";
- status = "disabled";
- };
- };
-};
-
-&systick {
- clocks = <&rcc 1 0>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi
new file mode 100644
index 0000000..43dd3b9
--- /dev/null
+++ b/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (c) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com>
+//
+
+#include <stm32f769-disco-u-boot.dtsi>
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index 7c99a6e..f677bb9 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -23,57 +23,14 @@
spi0 = &qspi;
};
- panel: panel {
- compatible = "orisetech,otm8009a";
- reset-gpios = <&gpioj 15 1>;
- status = "okay";
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-
- soc {
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
- <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
- <&clk_hse>;
- clock-names = "pclk", "px_clk", "ref";
- bootph-all;
- status = "okay";
-
- ports {
- port@0 {
- dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- port@1 {
- dsi_in: endpoint {
- remote-endpoint = <&dp_out>;
- };
- };
- };
- };
- };
};
-<dc {
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+&dsi {
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
+ <&clk_hse>;
+ clock-names = "pclk", "px_clk", "ref";
bootph-all;
-
- ports {
- port@0 {
- dp_out: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
- };
};
&fmc {
@@ -100,6 +57,12 @@
};
};
+<dc {
+ bootph-all;
+
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+};
+
&pinctrl {
ethernet_mii: mii@0 {
pins {
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
deleted file mode 100644
index d63cd2b..0000000
--- a/arch/arm/dts/stm32f769-disco.dts
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
- *
- */
-
-/dts-v1/;
-#include "stm32f746.dtsi"
-#include "stm32f769-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "STMicroelectronics STM32F769-DISCO board";
- compatible = "st,stm32f769-disco", "st,stm32f769";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x1000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- leds {
- compatible = "gpio-leds";
- led-green {
- gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- led-red {
- gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- button-0 {
- label = "User";
- linux,code = <KEY_HOME>;
- gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
- };
-
- mmc_vcard: mmc_vcard {
- compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&rcc {
- compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
-};
-
-&cec {
- pinctrl-0 = <&cec_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_b>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-<dc {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdio2 {
- status = "okay";
- vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
- broken-cd;
- pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdio_pins_b>;
- pinctrl-1 = <&sdio_pins_od_b>;
- bus-width = <4>;
-};
-
-&timers5 {
- /* Override timer5 to act as clockevent */
- compatible = "st,stm32-timer";
- interrupts = <50>;
- status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
- /delete-property/clock-names;
- /delete-node/pwm;
- /delete-node/timer@4;
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- dr_mode = "otg";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32f769-pinctrl.dtsi b/arch/arm/dts/stm32f769-pinctrl.dtsi
deleted file mode 100644
index 31005dd..0000000
--- a/arch/arm/dts/stm32f769-pinctrl.dtsi
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32f7-pinctrl.dtsi"
-
-&pinctrl{
- compatible = "st,stm32f769-pinctrl";
-};
diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi b/arch/arm/dts/stm32h7-pinctrl.dtsi
deleted file mode 100644
index aefa324..0000000
--- a/arch/arm/dts/stm32h7-pinctrl.dtsi
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
- <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- ethernet_rmii: rmii-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 11, AF11)>,
- <STM32_PINMUX('G', 13, AF11)>,
- <STM32_PINMUX('G', 12, AF11)>,
- <STM32_PINMUX('C', 4, AF11)>,
- <STM32_PINMUX('C', 5, AF11)>,
- <STM32_PINMUX('A', 7, AF11)>,
- <STM32_PINMUX('C', 1, AF11)>,
- <STM32_PINMUX('A', 2, AF11)>,
- <STM32_PINMUX('A', 1, AF11)>;
- slew-rate = <2>;
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2{
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2{
- pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2{
- pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- spi1_pins: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>,
- /* SPI1_CLK */
- <STM32_PINMUX('B', 5, AF5)>;
- /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 9, AF5)>;
- /* SPI1_MISO */
- bias-disable;
- };
- };
-
- uart4_pins: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- usart1_pins: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart2_pins: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart3_pins: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
- <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
- <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
- <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
- <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
- <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
- <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
- <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
- <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
- <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
- <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-};
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index dea4db3..9148a1f 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -53,7 +53,6 @@
bootph-all;
};
-
&fmc {
bootph-all;
};
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
deleted file mode 100644
index c490d0a..0000000
--- a/arch/arm/dts/stm32h743.dtsi
+++ /dev/null
@@ -1,695 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/clock/stm32h7-clks.h>
-#include <dt-bindings/mfd/stm32h7-rcc.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_i2s: i2s_ckin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
- };
-
- soc {
- timer5: timer@40000c00 {
- compatible = "st,stm32-timer";
- reg = <0x40000c00 0x400>;
- interrupts = <50>;
- clocks = <&rcc TIM5_CK>;
- };
-
- lptimer1: timer@40002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40002400 0x400>;
- clocks = <&rcc LPTIM1_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- spi2: spi@40003800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003800 0x400>;
- interrupts = <36>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
- clocks = <&rcc SPI2_CK>;
- status = "disabled";
-
- };
-
- spi3: spi@40003c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40003c00 0x400>;
- interrupts = <51>;
- resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
- clocks = <&rcc SPI3_CK>;
- status = "disabled";
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- status = "disabled";
- clocks = <&rcc USART2_CK>;
- };
-
- usart3: serial@40004800 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004800 0x400>;
- interrupts = <39>;
- status = "disabled";
- clocks = <&rcc USART3_CK>;
- };
-
- uart4: serial@40004c00 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004c00 0x400>;
- interrupts = <52>;
- status = "disabled";
- clocks = <&rcc UART4_CK>;
- };
-
- i2c1: i2c@40005400 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
- clocks = <&rcc I2C1_CK>;
- status = "disabled";
- };
-
- i2c2: i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005800 0x400>;
- interrupts = <33>,
- <34>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
- clocks = <&rcc I2C2_CK>;
- status = "disabled";
- };
-
- i2c3: i2c@40005c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005C00 0x400>;
- interrupts = <72>,
- <73>;
- resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
- clocks = <&rcc I2C3_CK>;
- status = "disabled";
- };
-
- dac: dac@40007400 {
- compatible = "st,stm32h7-dac-core";
- reg = <0x40007400 0x400>;
- clocks = <&rcc DAC12_CK>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- status = "disabled";
- clocks = <&rcc USART1_CK>;
- };
-
- spi1: spi@40013000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013000 0x400>;
- interrupts = <35>;
- resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
- clocks = <&rcc SPI1_CK>;
- status = "disabled";
- };
-
- spi4: spi@40013400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40013400 0x400>;
- interrupts = <84>;
- resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
- clocks = <&rcc SPI4_CK>;
- status = "disabled";
- };
-
- spi5: spi@40015000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x40015000 0x400>;
- interrupts = <85>;
- resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
- clocks = <&rcc SPI5_CK>;
- status = "disabled";
- };
-
- dma1: dma-controller@40020000 {
- compatible = "st,stm32-dma";
- reg = <0x40020000 0x400>;
- interrupts = <11>,
- <12>,
- <13>,
- <14>,
- <15>,
- <16>,
- <17>,
- <47>;
- clocks = <&rcc DMA1_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dma2: dma-controller@40020400 {
- compatible = "st,stm32-dma";
- reg = <0x40020400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&rcc DMA2_CK>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- status = "disabled";
- };
-
- dmamux1: dma-router@40020800 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x40020800 0x40>;
- #dma-cells = <3>;
- dma-channels = <16>;
- dma-requests = <128>;
- dma-masters = <&dma1 &dma2>;
- clocks = <&rcc DMA1_CK>;
- };
-
- adc_12: adc@40022000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x40022000 0x400>;
- interrupts = <18>;
- clocks = <&rcc ADC12_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_12>;
- interrupts = <0>;
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x100>;
- interrupt-parent = <&adc_12>;
- interrupts = <1>;
- status = "disabled";
- };
- };
-
- usbotg_hs: usb@40040000 {
- compatible = "st,stm32f7-hsotg";
- reg = <0x40040000 0x40000>;
- interrupts = <77>;
- clocks = <&rcc USB1OTG_CK>;
- clock-names = "otg";
- g-rx-fifo-size = <256>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- usbotg_fs: usb@40080000 {
- compatible = "st,stm32f4x9-fsotg";
- reg = <0x40080000 0x40000>;
- interrupts = <101>;
- clocks = <&rcc USB2OTG_CK>;
- clock-names = "otg";
- status = "disabled";
- };
-
- ltdc: display-controller@50001000 {
- compatible = "st,stm32-ltdc";
- reg = <0x50001000 0x200>;
- interrupts = <88>, <89>;
- resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
- clocks = <&rcc LTDC_CK>;
- clock-names = "lcd";
- status = "disabled";
- };
-
- mdma1: dma-controller@52000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x52000000 0x1000>;
- interrupts = <122>;
- clocks = <&rcc MDMA_CK>;
- #dma-cells = <5>;
- dma-channels = <16>;
- dma-requests = <32>;
- };
-
- sdmmc1: mmc@52007000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x52007000 0x1000>;
- interrupts = <49>;
- clocks = <&rcc SDMMC1_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- };
-
- sdmmc2: mmc@48022400 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x10153180>;
- reg = <0x48022400 0x400>;
- interrupts = <124>;
- clocks = <&rcc SDMMC2_CK>;
- clock-names = "apb_pclk";
- resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- exti: interrupt-controller@58000000 {
- compatible = "st,stm32h7-exti";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x58000000 0x400>;
- interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
- };
-
- syscfg: syscon@58000400 {
- compatible = "st,stm32-syscfg", "syscon";
- reg = <0x58000400 0x400>;
- };
-
- spi6: spi@58001400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x58001400 0x400>;
- interrupts = <86>;
- resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
- clocks = <&rcc SPI6_CK>;
- status = "disabled";
- };
-
- i2c4: i2c@58001c00 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x58001C00 0x400>;
- interrupts = <95>,
- <96>;
- resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
- clocks = <&rcc I2C4_CK>;
- status = "disabled";
- };
-
- lptimer2: timer@58002400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002400 0x400>;
- clocks = <&rcc LPTIM2_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- lptimer3: timer@58002800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x58002800 0x400>;
- clocks = <&rcc LPTIM3_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- lptimer4: timer@58002c00 {
- compatible = "st,stm32-lptimer";
- reg = <0x58002c00 0x400>;
- clocks = <&rcc LPTIM4_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer5: timer@58003000 {
- compatible = "st,stm32-lptimer";
- reg = <0x58003000 0x400>;
- clocks = <&rcc LPTIM5_CK>;
- clock-names = "mux";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- vrefbuf: regulator@58003c00 {
- compatible = "st,stm32-vrefbuf";
- reg = <0x58003C00 0x8>;
- clocks = <&rcc VREF_CK>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <2500000>;
- status = "disabled";
- };
-
- rtc: rtc@58004000 {
- compatible = "st,stm32h7-rtc";
- reg = <0x58004000 0x400>;
- clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
- clock-names = "pclk", "rtc_ck";
- assigned-clocks = <&rcc RTC_CK>;
- assigned-clock-parents = <&rcc LSE_CK>;
- interrupt-parent = <&exti>;
- interrupts = <17 IRQ_TYPE_EDGE_RISING>;
- st,syscfg = <&pwrcfg 0x00 0x100>;
- status = "disabled";
- };
-
- rcc: reset-clock-controller@58024400 {
- compatible = "st,stm32h743-rcc", "st,stm32-rcc";
- reg = <0x58024400 0x400>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
- st,syscfg = <&pwrcfg>;
- };
-
- pwrcfg: power-config@58024800 {
- compatible = "st,stm32-power-config", "syscon";
- reg = <0x58024800 0x400>;
- };
-
- adc_3: adc@58026000 {
- compatible = "st,stm32h7-adc-core";
- reg = <0x58026000 0x400>;
- interrupts = <127>;
- clocks = <&rcc ADC3_CK>;
- clock-names = "bus";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc3: adc@0 {
- compatible = "st,stm32h7-adc";
- #io-channel-cells = <1>;
- reg = <0x0>;
- interrupt-parent = <&adc_3>;
- interrupts = <0>;
- status = "disabled";
- };
- };
-
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- interrupts = <61>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
- clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
- st,syscon = <&syscfg 0x4>;
- snps,pbl = <8>;
- status = "disabled";
- };
-
- pinctrl: pinctrl@58020000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32h743-pinctrl";
- ranges = <0 0x58020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
-
- gpioa: gpio@58020000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA_CK>;
- st,bank-name = "GPIOA";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@58020400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc GPIOB_CK>;
- st,bank-name = "GPIOB";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@58020800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc GPIOC_CK>;
- st,bank-name = "GPIOC";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@58020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc GPIOD_CK>;
- st,bank-name = "GPIOD";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@58021000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOE_CK>;
- st,bank-name = "GPIOE";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@58021400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc GPIOF_CK>;
- st,bank-name = "GPIOF";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@58021800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc GPIOG_CK>;
- st,bank-name = "GPIOG";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@58021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc GPIOH_CK>;
- st,bank-name = "GPIOH";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@58022000 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOI_CK>;
- st,bank-name = "GPIOI";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@58022400 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc GPIOJ_CK>;
- st,bank-name = "GPIOJ";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@58022800 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc GPIOK_CK>;
- st,bank-name = "GPIOK";
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
- };
-};
-
-&systick {
- clock-frequency = <250000000>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts
deleted file mode 100644
index b31188f..0000000
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2017 - Patrice Chotard <patrice.chotard@foss.st.com>
- *
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32H743i-Discovery board";
- compatible = "st,stm32h743i-disco", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart2;
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts
deleted file mode 100644
index 5c5d805..0000000
--- a/arch/arm/dts/stm32h743i-eval.dts
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "stm32h743.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32H743i-EVAL board";
- compatible = "st,stm32h743i-eval", "st,stm32h743";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:115200n8";
- };
-
- memory@d0000000 {
- device_type = "memory";
- reg = <0xd0000000 0x2000000>;
- };
-
- aliases {
- serial0 = &usart1;
- };
-
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- v2v9_sd: regulator-v2v9_sd {
- compatible = "regulator-fixed";
- regulator-name = "v2v9_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- regulator-always-on;
- };
-
- usbotg_hs_phy: usb-phy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc USB1ULPI_CK>;
- clock-names = "main_clk";
- };
-};
-
-&adc_12 {
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "okay";
- adc1: adc@0 {
- /* potentiometer */
- st,adc-channels = <0>;
- status = "okay";
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-names = "default";
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- broken-cd;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&v2v9_sd>;
- status = "okay";
-};
-
-&usart1 {
- pinctrl-0 = <&usart1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbotg_hs_phy>;
- phy-names = "usb2-phy";
- dr_mode = "otg";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32h750.dtsi b/arch/arm/dts/stm32h750.dtsi
deleted file mode 100644
index 99533f3..0000000
--- a/arch/arm/dts/stm32h750.dtsi
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
-
-#include "stm32h743.dtsi"
-
diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts
deleted file mode 100644
index c7c7132..0000000
--- a/arch/arm/dts/stm32h750i-art-pi.dts
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
- *
- */
-
-/dts-v1/;
-#include "stm32h750.dtsi"
-#include "stm32h7-pinctrl.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "RT-Thread STM32H750i-ART-PI board";
- compatible = "st,stm32h750i-art-pi", "st,stm32h750";
-
- chosen {
- bootargs = "root=/dev/ram";
- stdout-path = "serial0:2000000n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x2000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- no-map;
- size = <0x100000>;
- linux,dma-default;
- };
- };
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- };
-
- leds {
- compatible = "gpio-leds";
- led-red {
- gpios = <&gpioi 8 0>;
- };
- led-green {
- gpios = <&gpioc 15 0>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- v3v3: regulator-v3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- wlan_pwr: regulator-wlan {
- compatible = "regulator-fixed";
-
- regulator-name = "wl-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&clk_hse {
- clock-frequency = <25000000>;
-};
-
-&dma1 {
- status = "okay";
-};
-
-&dma2 {
- status = "okay";
-};
-
-&mac {
- status = "disabled";
- pinctrl-0 = <ðernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
- broken-cd;
- non-removable;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&wlan_pwr>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
- brcmf: bcrmf@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-&spi1 {
- status = "okay";
- pinctrl-0 = <&spi1_pins>;
- pinctrl-names = "default";
- cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
- dma-names = "rx", "tx";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "winbond,w25q128", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
-
- partition@0 {
- label = "root filesystem";
- reg = <0 0x1000000>;
- };
- };
-};
-
-&usart2 {
- pinctrl-0 = <&usart2_pins>;
- pinctrl-names = "default";
- status = "disabled";
-};
-
-&usart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&usart3_pins>;
- dmas = <&dmamux1 45 0x400 0x05>,
- <&dmamux1 46 0x400 0x05>;
- dma-names = "rx", "tx";
- st,hw-flow-ctrl;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
- max-speed = <115200>;
- };
-};
-
-&uart4 {
- pinctrl-0 = <&uart4_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
deleted file mode 100644
index 52c2a9f..0000000
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ /dev/null
@@ -1,888 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
- adc1_pins_a: adc1-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
- };
- };
-
- adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
- <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
- };
- };
-
- adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
- <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
- };
- };
-
- eth1_rgmii_pins_a: eth1-rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
- bias-disable;
- };
-
- };
-
- eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
- };
- };
-
- eth2_rgmii_pins_a: eth2-rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
- bias-disable;
- };
- };
-
- eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
- <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
- };
- };
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_sleep_pins_a: i2c1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c5_pins_a: i2c5-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_a: i2c5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
- };
- };
-
- i2c5_pins_b: i2c5-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_b: i2c5-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
- };
- };
-
- m_can1_pins_a: m-can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_a: m_can1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can2_pins_a: m-can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
- bias-disable;
- };
- };
-
- m_can2_sleep_pins_a: m_can2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
- <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
- };
- };
-
- mcp23017_pins_a: mcp23017-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, GPIO)>;
- bias-pull-up;
- };
- };
-
- pwm1_ch3n_pins_a: pwm1-ch3n-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */
- };
- };
-
- pwm3_pins_a: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm3_sleep_pins_a: pwm3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
- };
- };
-
- pwm4_pins_a: pwm4-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm4_sleep_pins_a: pwm4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
- };
- };
-
- pwm5_pins_a: pwm5-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm5_sleep_pins_a: pwm5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
- };
- };
-
- pwm8_pins_a: pwm8-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_sleep_pins_a: pwm8-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
- };
- };
-
- pwm13_pins_a: pwm13-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm13_sleep_pins_a: pwm13-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
- };
- };
-
- pwm14_pins_a: pwm14-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm14_sleep_pins_a: pwm14-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
- };
- };
-
- qspi_clk_pins_a: qspi-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
- };
- };
-
- qspi_bk1_pins_a: qspi-bk1-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
- };
- };
-
- qspi_cs1_pins_a: qspi-cs1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
- };
- };
-
- sai1a_pins_a: sai1a-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
- <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
- <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai1a_sleep_pins_a: sai1a-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
- <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
- <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
- };
- };
-
- sai1b_pins_a: sai1b-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
- bias-disable;
- };
- };
-
- sai1b_sleep_pins_a: sai1b-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_clk_pins_a: sdmmc1-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
- <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
- <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
- <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
- };
- };
-
- sdmmc2_clk_pins_a: sdmmc2-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_pins_a: sdmmc2-d47-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
- <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- spi2_pins_a: spi2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
- <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
- bias-disable;
- };
- };
-
- spi2_sleep_pins_a: spi2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
- <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
- <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
- };
- };
-
- spi3_pins_a: spi3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
- <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
- bias-disable;
- };
- };
-
- spi3_sleep_pins_a: spi3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
- <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
- <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
- };
- };
-
- spi5_pins_a: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
- <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
- bias-disable;
- };
- };
-
- spi5_sleep_pins_a: spi5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
- <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
- <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
- };
- };
-
- stm32g0_intn_pins_a: stm32g0-intn-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, GPIO)>;
- bias-pull-up;
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_idle_pins_a: uart4-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_sleep_pins_a: uart4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-pull-up;
- };
- };
-
- uart4_idle_pins_b: uart4-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
- bias-pull-up;
- };
- };
-
- uart4_sleep_pins_b: uart4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
- <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
- <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
- bias-disable;
- };
- };
-
- uart7_idle_pins_a: uart7-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
- <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
- bias-disable;
- };
- };
-
- uart7_sleep_pins_a: uart7-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
- <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
- <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
- <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
- bias-pull-up;
- };
- };
-
- uart8_idle_pins_a: uart8-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
- bias-pull-up;
- };
- };
-
- uart8_sleep_pins_a: uart8-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
- <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
- <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
- <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart1_idle_pins_a: usart1-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
- bias-pull-up;
- };
- };
-
- usart1_sleep_pins_a: usart1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
- <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
- <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
- bias-pull-up;
- };
- };
-
- usart1_idle_pins_b: usart1-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
- bias-pull-up;
- };
- };
-
- usart1_sleep_pins_b: usart1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
- };
- };
-
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
- <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_idle_pins_a: usart2-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_a: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart2_pins_b: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_idle_pins_b: usart2-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_b: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi
index af7edc7..1fe6966 100644
--- a/arch/arm/dts/stm32mp13-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp13-u-boot.dtsi
@@ -48,6 +48,10 @@
bootph-all;
};
+&etzpc {
+ bootph-all;
+};
+
&gpioa {
bootph-all;
};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
deleted file mode 100644
index ad331b7..0000000
--- a/arch/arm/dts/stm32mp131.dtsi
+++ /dev/null
@@ -1,1567 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/stm32mp13-clks.h>
-#include <dt-bindings/reset/stm32mp13-resets.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
- interrupt-parent = <&intc>;
- };
-
- firmware {
- optee {
- method = "smc";
- compatible = "linaro,optee-tz";
- interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- scmi: scmi {
- compatible = "linaro,scmi-optee";
- #address-cells = <1>;
- #size-cells = <0>;
- linaro,optee-channel-id = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
-
- scmi_voltd: protocol@17 {
- reg = <0x17>;
-
- scmi_regu: regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_reg11: regulator@0 {
- reg = <VOLTD_SCMI_REG11>;
- regulator-name = "reg11";
- };
- scmi_reg18: regulator@1 {
- reg = <VOLTD_SCMI_REG18>;
- regulator-name = "reg18";
- };
- scmi_usb33: regulator@2 {
- reg = <VOLTD_SCMI_USB33>;
- regulator-name = "usb33";
- };
- };
- };
- };
- };
-
- intc: interrupt-controller@a0021000 {
- compatible = "arm,cortex-a7-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xa0021000 0x1000>,
- <0xa0022000 0x2000>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- interrupt-parent = <&intc>;
- always-on;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
-
- timers2: timer@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM2_K>;
- clock-names = "int";
- dmas = <&dmamux1 18 0x400 0x1>,
- <&dmamux1 19 0x400 0x1>,
- <&dmamux1 20 0x400 0x1>,
- <&dmamux1 21 0x400 0x1>,
- <&dmamux1 22 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers3: timer@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM3_K>;
- clock-names = "int";
- dmas = <&dmamux1 23 0x400 0x1>,
- <&dmamux1 24 0x400 0x1>,
- <&dmamux1 25 0x400 0x1>,
- <&dmamux1 26 0x400 0x1>,
- <&dmamux1 27 0x400 0x1>,
- <&dmamux1 28 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers4: timer@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM4_K>;
- clock-names = "int";
- dmas = <&dmamux1 29 0x400 0x1>,
- <&dmamux1 30 0x400 0x1>,
- <&dmamux1 31 0x400 0x1>,
- <&dmamux1 32 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers5: timer@40003000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40003000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM5_K>;
- clock-names = "int";
- dmas = <&dmamux1 55 0x400 0x1>,
- <&dmamux1 56 0x400 0x1>,
- <&dmamux1 57 0x400 0x1>,
- <&dmamux1 58 0x400 0x1>,
- <&dmamux1 59 0x400 0x1>,
- <&dmamux1 60 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers6: timer@40004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40004000 0x400>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM6_K>;
- clock-names = "int";
- dmas = <&dmamux1 69 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timer@40005000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40005000 0x400>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM7_K>;
- clock-names = "int";
- dmas = <&dmamux1 70 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- lptimer1: timer@40009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40009000 0x400>;
- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM1_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- i2s2: audio-controller@4000b000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x4000b000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 39 0x400 0x01>,
- <&dmamux1 40 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi2: spi@4000b000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI2_K>;
- resets = <&rcc SPI2_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 39 0x400 0x01>,
- <&dmamux1 40 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s3: audio-controller@4000c000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x4000c000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 61 0x400 0x01>,
- <&dmamux1 62 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi3: spi@4000c000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4000c000 0x400>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI3_K>;
- resets = <&rcc SPI3_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 61 0x400 0x01>,
- <&dmamux1 62 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spdifrx: audio-controller@4000d000 {
- compatible = "st,stm32h7-spdifrx";
- reg = <0x4000d000 0x400>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SPDIF_K>;
- clock-names = "kclk";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 93 0x400 0x01>,
- <&dmamux1 94 0x400 0x01>;
- dma-names = "rx", "rx-ctrl";
- status = "disabled";
- };
-
- usart3: serial@4000f000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4000f000 0x400>;
- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART3_K>;
- resets = <&rcc USART3_R>;
- wakeup-source;
- dmas = <&dmamux1 45 0x400 0x5>,
- <&dmamux1 46 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart4: serial@40010000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40010000 0x400>;
- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART4_K>;
- resets = <&rcc UART4_R>;
- wakeup-source;
- dmas = <&dmamux1 63 0x400 0x5>,
- <&dmamux1 64 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart5: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART5_K>;
- resets = <&rcc UART5_R>;
- wakeup-source;
- dmas = <&dmamux1 65 0x400 0x5>,
- <&dmamux1 66 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c1: i2c@40012000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x40012000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C1_K>;
- resets = <&rcc I2C1_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 33 0x400 0x1>,
- <&dmamux1 34 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x1>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c2: i2c@40013000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x40013000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C2_K>;
- resets = <&rcc I2C2_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 35 0x400 0x1>,
- <&dmamux1 36 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x2>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- uart7: serial@40018000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40018000 0x400>;
- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART7_K>;
- resets = <&rcc UART7_R>;
- wakeup-source;
- dmas = <&dmamux1 79 0x400 0x5>,
- <&dmamux1 80 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart8: serial@40019000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40019000 0x400>;
- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART8_K>;
- resets = <&rcc UART8_R>;
- wakeup-source;
- dmas = <&dmamux1 81 0x400 0x5>,
- <&dmamux1 82 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- timers1: timer@44000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44000000 0x400>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM1_K>;
- clock-names = "int";
- dmas = <&dmamux1 11 0x400 0x1>,
- <&dmamux1 12 0x400 0x1>,
- <&dmamux1 13 0x400 0x1>,
- <&dmamux1 14 0x400 0x1>,
- <&dmamux1 15 0x400 0x1>,
- <&dmamux1 16 0x400 0x1>,
- <&dmamux1 17 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers8: timer@44001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44001000 0x400>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM8_K>;
- clock-names = "int";
- dmas = <&dmamux1 47 0x400 0x1>,
- <&dmamux1 48 0x400 0x1>,
- <&dmamux1 49 0x400 0x1>,
- <&dmamux1 50 0x400 0x1>,
- <&dmamux1 51 0x400 0x1>,
- <&dmamux1 52 0x400 0x1>,
- <&dmamux1 53 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- usart6: serial@44003000 {
- compatible = "st,stm32h7-uart";
- reg = <0x44003000 0x400>;
- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART6_K>;
- resets = <&rcc USART6_R>;
- wakeup-source;
- dmas = <&dmamux1 71 0x400 0x5>,
- <&dmamux1 72 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s1: audio-controller@44004000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x44004000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 37 0x400 0x01>,
- <&dmamux1 38 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi1: spi@44004000 {
- compatible = "st,stm32h7-spi";
- reg = <0x44004000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI1_K>;
- resets = <&rcc SPI1_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 37 0x400 0x01>,
- <&dmamux1 38 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai1: sai@4400a000 {
- compatible = "st,stm32h7-sai";
- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
- ranges = <0 0x4400a000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI1_R>;
- status = "disabled";
-
- sai1a: audio-controller@4400a004 {
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 87 0x400 0x01>;
- status = "disabled";
- };
-
- sai1b: audio-controller@4400a024 {
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 88 0x400 0x01>;
- status = "disabled";
- };
- };
-
- sai2: sai@4400b000 {
- compatible = "st,stm32h7-sai";
- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
- ranges = <0 0x4400b000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI2_R>;
- status = "disabled";
-
- sai2a: audio-controller@4400b004 {
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 89 0x400 0x01>;
- status = "disabled";
- };
-
- sai2b: audio-controller@4400b024 {
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- #sound-dai-cells = <0>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 90 0x400 0x01>;
- status = "disabled";
- };
- };
-
- dfsdm: dfsdm@4400d000 {
- compatible = "st,stm32mp1-dfsdm";
- reg = <0x4400d000 0x800>;
- clocks = <&rcc DFSDM_K>;
- clock-names = "dfsdm";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dfsdm0: filter@0 {
- compatible = "st,stm32-dfsdm-adc";
- reg = <0>;
- #io-channel-cells = <1>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 101 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm1: filter@1 {
- compatible = "st,stm32-dfsdm-adc";
- reg = <1>;
- #io-channel-cells = <1>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 102 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- dma1: dma-controller@48000000 {
- compatible = "st,stm32-dma";
- reg = <0x48000000 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA1>;
- resets = <&rcc DMA1_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dma2: dma-controller@48001000 {
- compatible = "st,stm32-dma";
- reg = <0x48001000 0x400>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA2>;
- resets = <&rcc DMA2_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dmamux1: dma-router@48002000 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x48002000 0x40>;
- clocks = <&rcc DMAMUX1>;
- resets = <&rcc DMAMUX1_R>;
- #dma-cells = <3>;
- dma-masters = <&dma1 &dma2>;
- dma-requests = <128>;
- dma-channels = <16>;
- };
-
- adc_2: adc@48004000 {
- compatible = "st,stm32mp13-adc-core";
- reg = <0x48004000 0x400>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc ADC2>, <&rcc ADC2_K>;
- clock-names = "bus", "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc2: adc@0 {
- compatible = "st,stm32mp13-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0>;
- interrupt-parent = <&adc_2>;
- interrupts = <0>;
- dmas = <&dmamux1 10 0x400 0x80000001>;
- dma-names = "rx";
- status = "disabled";
-
- channel@13 {
- reg = <13>;
- label = "vrefint";
- };
- channel@14 {
- reg = <14>;
- label = "vddcore";
- };
- channel@16 {
- reg = <16>;
- label = "vddcpu";
- };
- channel@17 {
- reg = <17>;
- label = "vddq_ddr";
- };
- };
- };
-
- usbotg_hs: usb@49000000 {
- compatible = "st,stm32mp15-hsotg", "snps,dwc2";
- reg = <0x49000000 0x40000>;
- clocks = <&rcc USBO_K>;
- clock-names = "otg";
- resets = <&rcc USBO_R>;
- reset-names = "dwc2";
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- g-rx-fifo-size = <512>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
- dr_mode = "otg";
- otg-rev = <0x200>;
- usb33d-supply = <&scmi_usb33>;
- status = "disabled";
- };
-
- usart1: serial@4c000000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4c000000 0x400>;
- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART1_K>;
- resets = <&rcc USART1_R>;
- wakeup-source;
- dmas = <&dmamux1 41 0x400 0x5>,
- <&dmamux1 42 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- usart2: serial@4c001000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4c001000 0x400>;
- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART2_K>;
- resets = <&rcc USART2_R>;
- wakeup-source;
- dmas = <&dmamux1 43 0x400 0x5>,
- <&dmamux1 44 0x400 0x1>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s4: audio-controller@4c002000 {
- compatible = "st,stm32h7-i2s";
- reg = <0x4c002000 0x400>;
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 83 0x400 0x01>,
- <&dmamux1 84 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi4: spi@4c002000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4c002000 0x400>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI4_K>;
- resets = <&rcc SPI4_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 83 0x400 0x01>,
- <&dmamux1 84 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi5: spi@4c003000 {
- compatible = "st,stm32h7-spi";
- reg = <0x4c003000 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI5_K>;
- resets = <&rcc SPI5_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 85 0x400 0x01>,
- <&dmamux1 86 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c3: i2c@4c004000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x4c004000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C3_K>;
- resets = <&rcc I2C3_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 73 0x400 0x1>,
- <&dmamux1 74 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x4>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c4: i2c@4c005000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x4c005000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C4_K>;
- resets = <&rcc I2C4_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 75 0x400 0x1>,
- <&dmamux1 76 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x8>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c5: i2c@4c006000 {
- compatible = "st,stm32mp13-i2c";
- reg = <0x4c006000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C5_K>;
- resets = <&rcc I2C5_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&dmamux1 115 0x400 0x1>,
- <&dmamux1 116 0x400 0x1>;
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x10>;
- i2c-analog-filter;
- status = "disabled";
- };
-
- timers12: timer@4c007000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c007000 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM12_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timer@4c008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c008000 0x400>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM13_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@12 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <12>;
- status = "disabled";
- };
- };
-
- timers14: timer@4c009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c009000 0x400>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM14_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@13 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <13>;
- status = "disabled";
- };
- };
-
- timers15: timer@4c00a000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c00a000 0x400>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM15_K>;
- clock-names = "int";
- dmas = <&dmamux1 105 0x400 0x1>,
- <&dmamux1 106 0x400 0x1>,
- <&dmamux1 107 0x400 0x1>,
- <&dmamux1 108 0x400 0x1>;
- dma-names = "ch1", "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@14 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <14>;
- status = "disabled";
- };
- };
-
- timers16: timer@4c00b000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c00b000 0x400>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM16_K>;
- clock-names = "int";
- dmas = <&dmamux1 109 0x400 0x1>,
- <&dmamux1 110 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@15 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <15>;
- status = "disabled";
- };
- };
-
- timers17: timer@4c00c000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x4c00c000 0x400>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM17_K>;
- clock-names = "int";
- dmas = <&dmamux1 111 0x400 0x1>,
- <&dmamux1 112 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@16 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <16>;
- status = "disabled";
- };
- };
-
- rcc: rcc@50000000 {
- compatible = "st,stm32mp13-rcc", "syscon";
- reg = <0x50000000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
- };
-
- pwr_regulators: pwr@50001000 {
- compatible = "st,stm32mp1,pwr-reg";
- reg = <0x50001000 0x10>;
- status = "disabled";
-
- reg11: reg11 {
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- reg18: reg18 {
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- usb33: usb33 {
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
-
- exti: interrupt-controller@5000d000 {
- compatible = "st,stm32mp13-exti", "syscon";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000d000 0x400>;
- };
-
- syscfg: syscon@50020000 {
- compatible = "st,stm32mp157-syscfg", "syscon";
- reg = <0x50020000 0x400>;
- clocks = <&rcc SYSCFG>;
- };
-
- lptimer2: timer@50021000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50021000 0x400>;
- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM2_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- lptimer3: timer@50022000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50022000 0x400>;
- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM3_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- lptimer4: timer@50023000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50023000 0x400>;
- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM4_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- lptimer5: timer@50024000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50024000 0x400>;
- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM5_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer {
- compatible = "st,stm32-lptimer-timer";
- status = "disabled";
- };
- };
-
- rng: rng@54004000 {
- compatible = "st,stm32mp13-rng";
- reg = <0x54004000 0x400>;
- clocks = <&rcc RNG1_K>;
- resets = <&rcc RNG1_R>;
- status = "disabled";
- };
-
- mdma: dma-controller@58000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x58000000 0x1000>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc MDMA>;
- #dma-cells = <5>;
- dma-channels = <32>;
- dma-requests = <48>;
- };
-
- fmc: memory-controller@58002000 {
- compatible = "st,stm32mp1-fmc2-ebi";
- reg = <0x58002000 0x1000>;
- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
- <4 0 0x80000000 0x10000000>; /* NAND */
- #address-cells = <2>;
- #size-cells = <1>;
- clocks = <&rcc FMC_K>;
- resets = <&rcc FMC_R>;
- status = "disabled";
-
- nand-controller@4,0 {
- compatible = "st,stm32mp1-fmc2-nfc";
- reg = <4 0x00000000 0x1000>,
- <4 0x08010000 0x1000>,
- <4 0x08020000 0x1000>,
- <4 0x01000000 0x1000>,
- <4 0x09010000 0x1000>,
- <4 0x09020000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
- <&mdma 24 0x2 0x12000a08 0x0 0x0>,
- <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
- dma-names = "tx", "rx", "ecc";
- status = "disabled";
- };
- };
-
- qspi: spi@58003000 {
- compatible = "st,stm32f469-qspi";
- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
- reg-names = "qspi", "qspi_mm";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
- <&mdma 26 0x2 0x10100008 0x0 0x0>;
- dma-names = "tx", "rx";
- clocks = <&rcc QSPI_K>;
- resets = <&rcc QSPI_R>;
- status = "disabled";
- };
-
- sdmmc1: mmc@58005000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x20253180>;
- reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC1_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC1_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <130000000>;
- status = "disabled";
- };
-
- sdmmc2: mmc@58007000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x20253180>;
- reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC2_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC2_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <130000000>;
- status = "disabled";
- };
-
- eth1: eth1@5800a000 {
- compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
- reg = <0x5800a000 0x2000>;
- reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <&exti 68 1>;
- interrupt-names = "macirq", "eth_wake_irq";
- clock-names = "stmmaceth",
- "mac-clk-tx",
- "mac-clk-rx",
- "ethstp",
- "eth-ck";
- clocks = <&rcc ETH1MAC>,
- <&rcc ETH1TX>,
- <&rcc ETH1RX>,
- <&rcc ETH1STP>,
- <&rcc ETH1CK_K>;
- st,syscon = <&syscfg 0x4 0xff0000>;
- snps,mixed-burst;
- snps,pbl = <2>;
- snps,axi-config = <&stmmac_axi_config_1>;
- snps,tso;
- status = "disabled";
-
- stmmac_axi_config_1: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
- };
-
- usbh_ohci: usb@5800c000 {
- compatible = "generic-ohci";
- reg = <0x5800c000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- usbh_ehci: usb@5800d000 {
- compatible = "generic-ehci";
- reg = <0x5800d000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- companion = <&usbh_ohci>;
- status = "disabled";
- };
-
- iwdg2: watchdog@5a002000 {
- compatible = "st,stm32mp1-iwdg";
- reg = <0x5a002000 0x400>;
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
- clock-names = "pclk", "lsi";
- status = "disabled";
- };
-
- usbphyc: usbphyc@5a006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "st,stm32mp1-usbphyc";
- reg = <0x5a006000 0x1000>;
- clocks = <&rcc USBPHY_K>;
- resets = <&rcc USBPHY_R>;
- vdda1v1-supply = <&scmi_reg11>;
- vdda1v8-supply = <&scmi_reg18>;
- status = "disabled";
-
- usbphyc_port0: usb-phy@0 {
- #phy-cells = <0>;
- reg = <0>;
- };
-
- usbphyc_port1: usb-phy@1 {
- #phy-cells = <1>;
- reg = <1>;
- };
- };
-
- rtc: rtc@5c004000 {
- compatible = "st,stm32mp1-rtc";
- reg = <0x5c004000 0x400>;
- interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scmi_clk CK_SCMI_RTCAPB>,
- <&scmi_clk CK_SCMI_RTC>;
- clock-names = "pclk", "rtc_ck";
- status = "disabled";
- };
-
- bsec: efuse@5c005000 {
- compatible = "st,stm32mp13-bsec";
- reg = <0x5c005000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- part_number_otp: part_number_otp@4 {
- reg = <0x4 0x2>;
- bits = <0 12>;
- };
- ts_cal1: calib@5c {
- reg = <0x5c 0x2>;
- };
- ts_cal2: calib@5e {
- reg = <0x5e 0x2>;
- };
- ethernet_mac1_address: mac1@e4 {
- reg = <0xe4 0x6>;
- };
- ethernet_mac2_address: mac2@ea {
- reg = <0xea 0x6>;
- };
- };
-
- /*
- * Break node order to solve dependency probe issue between
- * pinctrl and exti.
- */
- pinctrl: pinctrl@50002000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp135-pinctrl";
- ranges = <0 0x50002000 0x8400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioa: gpio@50002000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA>;
- st,bank-name = "GPIOA";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOB>;
- st,bank-name = "GPIOB";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOC>;
- st,bank-name = "GPIOC";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x400>;
- clocks = <&rcc GPIOD>;
- st,bank-name = "GPIOD";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x400>;
- clocks = <&rcc GPIOE>;
- st,bank-name = "GPIOE";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x400>;
- clocks = <&rcc GPIOF>;
- st,bank-name = "GPIOF";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x400>;
- clocks = <&rcc GPIOG>;
- st,bank-name = "GPIOG";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x400>;
- clocks = <&rcc GPIOH>;
- st,bank-name = "GPIOH";
- ngpios = <15>;
- gpio-ranges = <&pinctrl 0 112 15>;
- };
-
- gpioi: gpio@5000a000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x400>;
- clocks = <&rcc GPIOI>;
- st,bank-name = "GPIOI";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 128 8>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
deleted file mode 100644
index 5cd5bde..0000000
--- a/arch/arm/dts/stm32mp133.dtsi
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-#include "stm32mp131.dtsi"
-
-/ {
- soc {
- m_can1: can@4400e000 {
- compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- m_can2: can@4400f000 {
- compatible = "bosch,m_can";
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- adc_1: adc@48003000 {
- compatible = "st,stm32mp13-adc-core";
- reg = <0x48003000 0x400>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc ADC1>, <&rcc ADC1_K>;
- clock-names = "bus", "adc";
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32mp13-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0>;
- interrupt-parent = <&adc_1>;
- interrupts = <0>;
- dmas = <&dmamux1 9 0x400 0x80000001>;
- dma-names = "rx";
- status = "disabled";
-
- channel@18 {
- reg = <18>;
- label = "vrefint";
- };
- };
- };
-
- eth2: eth2@5800e000 {
- compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
- reg = <0x5800e000 0x2000>;
- reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth",
- "mac-clk-tx",
- "mac-clk-rx",
- "ethstp",
- "eth-ck";
- clocks = <&rcc ETH2MAC>,
- <&rcc ETH2TX>,
- <&rcc ETH2RX>,
- <&rcc ETH2STP>,
- <&rcc ETH2CK_K>;
- st,syscon = <&syscfg 0x4 0xff000000>;
- snps,mixed-burst;
- snps,pbl = <2>;
- snps,axi-config = <&stmmac_axi_config_2>;
- snps,tso;
- status = "disabled";
-
- stmmac_axi_config_2: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp135.dtsi b/arch/arm/dts/stm32mp135.dtsi
deleted file mode 100644
index abf2acd..0000000
--- a/arch/arm/dts/stm32mp135.dtsi
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-#include "stm32mp133.dtsi"
-
-/ {
- soc {
- };
-};
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
deleted file mode 100644
index 275823d..0000000
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ /dev/null
@@ -1,376 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
-#include "stm32mp135.dtsi"
-#include "stm32mp13xf.dtsi"
-#include "stm32mp13-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP135F-DK Discovery Board";
- compatible = "st,stm32mp135f-dk", "st,stm32mp135";
-
- aliases {
- serial0 = &uart4;
- serial1 = &usart1;
- serial2 = &uart8;
- serial3 = &usart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x20000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- optee@dd000000 {
- reg = <0xdd000000 0x3000000>;
- no-map;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- button-user {
- label = "User-PA13";
- linux,code = <BTN_1>;
- gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-};
-
-&adc_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&adc1_usb_cc_pins_a>;
- vdda-supply = <&scmi_vdd_adc>;
- vref-supply = <&scmi_vdd_adc>;
- status = "okay";
- adc1: adc@0 {
- status = "okay";
- /*
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
- * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
- * Use arbitrary margin here (e.g. 5us).
- */
- channel@6 {
- reg = <6>;
- st,min-sample-time-ns = <5000>;
- };
- channel@12 {
- reg = <12>;
- st,min-sample-time-ns = <5000>;
- };
- };
-};
-
-&i2c1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-1 = <&i2c1_sleep_pins_a>;
- i2c-scl-rising-time-ns = <96>;
- i2c-scl-falling-time-ns = <3>;
- clock-frequency = <1000000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- mcp23017: pinctrl@21 {
- compatible = "microchip,mcp23017";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpiog>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcp23017_pins_a>;
- interrupt-controller;
- #interrupt-cells = <2>;
- microchip,irq-mirror;
- };
-
- typec@53 {
- compatible = "st,stm32g0-typec";
- reg = <0x53>;
- /* Alert pin on PI2 */
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpioi>;
- /* Internal pull-up on PI2 */
- pinctrl-names = "default";
- pinctrl-0 = <&stm32g0_intn_pins_a>;
- firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
-
- port {
- con_usb_c_g0_ep: endpoint {
- remote-endpoint = <&usbotg_hs_ep>;
- };
- };
- };
- };
-};
-
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <170>;
- i2c-scl-falling-time-ns = <5>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&scmi_regu {
- scmi_vdd_adc: regulator@10 {
- reg = <VOLTD_SCMI_STPMIC1_LDO1>;
- regulator-name = "vdd_adc";
- };
- scmi_vdd_usb: regulator@13 {
- reg = <VOLTD_SCMI_STPMIC1_LDO4>;
- regulator-name = "vdd_usb";
- };
- scmi_vdd_sd: regulator@14 {
- reg = <VOLTD_SCMI_STPMIC1_LDO5>;
- regulator-name = "vdd_sd";
- };
- scmi_v1v8_periph: regulator@15 {
- reg = <VOLTD_SCMI_STPMIC1_LDO6>;
- regulator-name = "v1v8_periph";
- };
- scmi_v3v3_sw: regulator@19 {
- reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
- regulator-name = "v3v3_sw";
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&scmi_vdd_sd>;
- status = "okay";
-};
-
-&spi5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi5_pins_a>;
- pinctrl-1 = <&spi5_sleep_pins_a>;
- status = "disabled";
-};
-
-&timers1 {
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
- pwm1: pwm {
- pinctrl-0 = <&pwm1_ch3n_pins_a>;
- pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
-};
-
-&timers3 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm3_pins_a>;
- pinctrl-1 = <&pwm3_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@2 {
- status = "okay";
- };
-};
-
-&timers4 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm4_pins_a>;
- pinctrl-1 = <&pwm4_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@3 {
- status = "okay";
- };
-};
-
-&timers8 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-1 = <&pwm8_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@7 {
- status = "okay";
- };
-};
-
-&timers14 {
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm14_pins_a>;
- pinctrl-1 = <&pwm14_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@13 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart8 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart8_pins_a>;
- pinctrl-1 = <&uart8_sleep_pins_a>;
- pinctrl-2 = <&uart8_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
-};
-
-&usart1 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart1_pins_a>;
- pinctrl-1 = <&usart1_sleep_pins_a>;
- pinctrl-2 = <&usart1_idle_pins_a>;
- uart-has-rtscts;
- status = "disabled";
-};
-
-/* Bluetooth */
-&usart2 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-1 = <&usart2_sleep_pins_a>;
- pinctrl-2 = <&usart2_idle_pins_a>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- /* onboard HUB */
- hub@1 {
- compatible = "usb424,2514";
- reg = <1>;
- vdd-supply = <&scmi_v3v3_sw>;
- };
-};
-
-&usbotg_hs {
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- usb-role-switch;
- status = "okay";
- port {
- usbotg_hs_ep: endpoint {
- remote-endpoint = <&con_usb_c_g0_ep>;
- };
- };
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&scmi_vdd_usb>;
- st,current-boost-microamp = <1000>;
- st,decrease-hs-slew-rate;
- st,tune-hs-dc-level = <2>;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <11>;
- st,trim-hs-impedance = <2>;
- st,tune-squelch-level = <1>;
- st,enable-hs-rx-gain-eq;
- st,no-hs-ftime-ctrl;
- st,no-lsfs-sc;
-};
-
-&usbphyc_port1 {
- phy-supply = <&scmi_vdd_usb>;
- st,current-boost-microamp = <1000>;
- st,decrease-hs-slew-rate;
- st,tune-hs-dc-level = <2>;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <11>;
- st,trim-hs-impedance = <2>;
- st,tune-squelch-level = <1>;
- st,enable-hs-rx-gain-eq;
- st,no-hs-ftime-ctrl;
- st,no-lsfs-sc;
-};
diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi
deleted file mode 100644
index 4d00e75..0000000
--- a/arch/arm/dts/stm32mp13xc.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
- soc {
- cryp: crypto@54002000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54002000 0x400>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi
deleted file mode 100644
index 4d00e75..0000000
--- a/arch/arm/dts/stm32mp13xf.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
- soc {
- cryp: crypto@54002000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54002000 0x400>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
deleted file mode 100644
index 098153e..0000000
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ /dev/null
@@ -1,2826 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
- adc1_ain_pins_a: adc1-ain-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
- <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
- <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
- };
- };
-
- adc1_in6_pins_a: adc1-in6-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
- };
- };
-
- adc12_ain_pins_a: adc12-ain-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
- <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
- <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
- <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
- };
- };
-
- adc12_ain_pins_b: adc12-ain-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
- <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
- };
- };
-
- adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
- <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
- };
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_sleep_pins_a: cec-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- cec_pins_b: cec-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF5)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_sleep_pins_b: cec-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- dac_ch1_pins_a: dac-ch1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
- };
- };
-
- dac_ch2_pins_a: dac-ch2-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
- };
- };
-
- dcmi_pins_a: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
- bias-disable;
- };
- };
-
- dcmi_sleep_pins_a: dcmi-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
- };
- };
-
- dcmi_pins_b: dcmi-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
- bias-disable;
- };
- };
-
- dcmi_sleep_pins_b: dcmi-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
- };
- };
-
- dcmi_pins_c: dcmi-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */
- bias-pull-up;
- };
- };
-
- dcmi_sleep_pins_c: dcmi-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */
- };
- };
-
- ethernet0_rgmii_pins_a: rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_b: rgmii-1 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_c: rgmii-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_d: rgmii-3 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rgmii_pins_e: rgmii-4 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- ethernet0_rmii_pins_a: rmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
- bias-disable;
- };
- };
-
- ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
- };
- };
-
- ethernet0_rmii_pins_b: rmii-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
- <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
- <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
- bias-disable;
- };
- pins4 {
- pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
- };
- };
-
- ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
- <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
- <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
- };
- };
-
- ethernet0_rmii_pins_c: rmii-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
- bias-disable;
- };
- };
-
- ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
- };
- };
-
- fmc_pins_a: fmc-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
- <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
- bias-pull-up;
- };
- };
-
- fmc_sleep_pins_a: fmc-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
- <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
- };
- };
-
- fmc_pins_b: fmc-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
- <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
- <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
- <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
- <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
- <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
- <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
- <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
- <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
- <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
- <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
- <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- fmc_sleep_pins_b: fmc-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
- <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
- <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
- <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
- <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
- <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
- <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
- <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
- };
- };
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_sleep_pins_a: i2c1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c1_pins_b: i2c1-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_sleep_pins_b: i2c1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c2_pins_a: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_sleep_pins_a: i2c2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c2_pins_b1: i2c2-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_sleep_pins_b1: i2c2-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c2_pins_c: i2c2-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_c: i2c2-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c5_pins_a: i2c5-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_a: i2c5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
-
- };
- };
-
- i2c5_pins_b: i2c5-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_sleep_pins_b: i2c5-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
- };
- };
-
- i2s2_pins_a: i2s2-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- i2s2_sleep_pins_a: i2s2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
- };
- };
-
- ltdc_pins_a: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_sleep_pins_a: ltdc-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
- };
- };
-
- ltdc_pins_b: ltdc-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_sleep_pins_b: ltdc-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
- };
- };
-
- ltdc_pins_c: ltdc-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
- <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
- <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */
- <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
- <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
- <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */
- <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */
- <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
- <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
- <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */
- <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
- <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
- <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
- <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
- <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
- <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */
- <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
- <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_sleep_pins_c: ltdc-sleep-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
- <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */
- <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */
- <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */
- <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */
- <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
- <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */
- <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
- <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */
- <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */
- <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */
- };
- };
-
- ltdc_pins_d: ltdc-3 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
- <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
- <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
- <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- ltdc_sleep_pins_d: ltdc-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
- };
- };
-
- mco1_pins_a: mco1-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- mco1_sleep_pins_a: mco1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
- };
- };
-
- mco2_pins_a: mco2-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- mco2_sleep_pins_a: mco2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
- };
- };
-
- m_can1_pins_a: m-can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_a: m_can1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can1_pins_b: m-can1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_b: m_can1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can1_pins_c: m-can1-2 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_c: m_can1-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */
- };
- };
-
- m_can2_pins_a: m-can2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
- bias-disable;
- };
- };
-
- m_can2_sleep_pins_a: m_can2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
- <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
- };
- };
-
- pwm1_pins_a: pwm1-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
- <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
- <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_sleep_pins_a: pwm1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
- <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
- <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
- };
- };
-
- pwm1_pins_b: pwm1-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_sleep_pins_b: pwm1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
- };
- };
-
- pwm1_pins_c: pwm1-2 {
- pins {
- pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm1_sleep_pins_c: pwm1-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */
- };
- };
-
- pwm2_pins_a: pwm2-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm2_sleep_pins_a: pwm2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
- };
- };
-
- pwm3_pins_a: pwm3-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm3_sleep_pins_a: pwm3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
- };
- };
-
- pwm3_pins_b: pwm3-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm3_sleep_pins_b: pwm3-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */
- };
- };
-
- pwm4_pins_a: pwm4-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
- <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm4_sleep_pins_a: pwm4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
- <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
- };
- };
-
- pwm4_pins_b: pwm4-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm4_sleep_pins_b: pwm4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
- };
- };
-
- pwm5_pins_a: pwm5-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm5_sleep_pins_a: pwm5-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
- };
- };
-
- pwm5_pins_b: pwm5-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */
- <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */
- <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm5_sleep_pins_b: pwm5-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */
- <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
- };
- };
-
- pwm8_pins_a: pwm8-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_sleep_pins_a: pwm8-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
- };
- };
-
- pwm8_pins_b: pwm8-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
- <STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */
- <STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */
- <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_sleep_pins_b: pwm8-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
- <STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */
- <STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */
- <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */
- };
- };
-
- pwm12_pins_a: pwm12-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm12_sleep_pins_a: pwm12-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
- };
- };
-
- qspi_clk_pins_a: qspi-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
- };
- };
-
- qspi_bk1_pins_a: qspi-bk1-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
- };
- };
-
- qspi_bk2_pins_a: qspi-bk2-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
- };
- };
-
- qspi_cs1_pins_a: qspi-cs1-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
- };
- };
-
- qspi_cs2_pins_a: qspi-cs2-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
- };
- };
-
- sai2a_pins_a: sai2a-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_a: sai2a-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
- };
- };
-
- sai2a_pins_b: sai2a-1 {
- pins1 {
- pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
- <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_b: sai2a-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
- <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
- };
- };
-
- sai2a_pins_c: sai2a-2 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
- <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_c: sai2a-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
- <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
- };
- };
-
- sai2b_pins_a: sai2b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_a: sai2b-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
- <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
- };
- };
-
- sai2b_pins_b: sai2b-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_b: sai2b-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai2b_pins_c: sai2b-2 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_c: sai2b-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai2b_pins_d: sai2b-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
- <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
- <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_d: sai2b-sleep-3 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
- <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
- <STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
- <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai4a_pins_a: sai4a-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai4a_sleep_pins_a: sai4a-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_b4_pins_b: sdmmc1-b4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc1_dir_pins_b: sdmmc1-dir-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- sdmmc2_b4_pins_a: sdmmc2-b4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
- <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- pins3 {
- pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
- <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
- <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
- };
- };
-
- sdmmc2_b4_pins_b: sdmmc2-b4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
- <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
- <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
- <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
- <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-disable;
- };
- pins3 {
- pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc2_d47_pins_a: sdmmc2-d47-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_b: sdmmc2-d47-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_c: sdmmc2-d47-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_d: sdmmc2-d47-3 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc2_d47_pins_e: sdmmc2-d47-4 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
- pins {
- pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
- <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
- <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
- <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
- };
- };
-
- sdmmc3_b4_pins_a: sdmmc3-b4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
- <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- pins3 {
- pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
- <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
- <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
- <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
- };
- };
-
- sdmmc3_b4_pins_b: sdmmc3-b4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
- <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
- <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
- slew-rate = <1>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
- slew-rate = <2>;
- drive-push-pull;
- bias-pull-up;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
- slew-rate = <1>;
- drive-open-drain;
- bias-pull-up;
- };
- };
-
- sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
- <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
- <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
- <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
- <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
- <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
- };
- };
-
- spdifrx_pins_a: spdifrx-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
- bias-disable;
- };
- };
-
- spdifrx_sleep_pins_a: spdifrx-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
- };
- };
-
- spi1_pins_b: spi1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
-
- spi2_pins_a: spi2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
- <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
- bias-disable;
- };
- };
-
- spi2_pins_b: spi2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
- <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
- bias-disable;
- };
- };
-
- spi2_pins_c: spi2-2 {
- pins1 {
- pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
- <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
- bias-disable;
- drive-push-pull;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
- bias-pull-down;
- };
- };
-
- spi4_pins_a: spi4-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
- <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
- bias-disable;
- };
- };
-
- spi5_pins_a: spi5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
- <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
- bias-disable;
- };
- };
-
- stusb1600_pins_a: stusb1600-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 11, GPIO)>;
- bias-pull-up;
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_idle_pins_a: uart4-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_sleep_pins_a: uart4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_c: uart4-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_d: uart4-3 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_idle_pins_d: uart4-idle-3 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_sleep_pins_d: uart4-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
- <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
- };
- };
-
- uart5_pins_a: uart5-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */
- bias-disable;
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
- <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
- <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
- bias-disable;
- };
- };
-
- uart7_pins_b: uart7-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
- bias-disable;
- };
- };
-
- uart7_pins_c: uart7-2 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-pull-up;
- };
- };
-
- uart7_idle_pins_c: uart7-idle-2 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-pull-up;
- };
- };
-
- uart7_sleep_pins_c: uart7-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
- <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
- bias-disable;
- };
- };
-
- uart8_rtscts_pins_a: uart8rtscts-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
- <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
- bias-disable;
- };
- };
-
- usart1_idle_pins_a: usart1-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
- <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
- };
- };
-
- usart1_sleep_pins_a: usart1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
- <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
- };
- };
-
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_a: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart2_pins_b: usart2-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_b: usart2-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart2_pins_c: usart2-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
- bias-disable;
- };
- };
-
- usart2_idle_pins_c: usart2-idle-2 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_c: usart2-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart3_pins_a: usart3-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usart3_idle_pins_a: usart3-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usart3_sleep_pins_a: usart3-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_b: usart3-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
- <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart3_idle_pins_b: usart3-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-pull-up;
- };
- };
-
- usart3_sleep_pins_b: usart3-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_c: usart3-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
- <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart3_idle_pins_c: usart3-idle-2 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
- bias-pull-up;
- };
- };
-
- usart3_sleep_pins_c: usart3-sleep-2 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_d: usart3-3 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usart3_idle_pins_d: usart3-idle-3 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
- bias-disable;
- };
- };
-
- usart3_sleep_pins_d: usart3-sleep-3 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_e: usart3-4 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-pull-up;
- };
- };
-
- usart3_idle_pins_e: usart3-idle-4 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
- };
- pins2 {
- pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins3 {
- pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
- bias-pull-up;
- };
- };
-
- usart3_sleep_pins_e: usart3-sleep-4 {
- pins {
- pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
- <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
- <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */
- };
- };
-
- usart3_pins_f: usart3-5 {
- pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
- <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
- <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
- bias-disable;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
- };
- };
-
- usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
- };
- };
-};
-
-&pinctrl_z {
- i2c2_pins_b2: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_sleep_pins_b2: i2c2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
- };
- };
-
- i2c4_pins_a: i2c4-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c4_sleep_pins_a: i2c4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
- };
- };
-
- i2c6_pins_a: i2c6-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */
- <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c6_sleep_pins_a: i2c6-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */
- <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */
- };
- };
-
- spi1_pins_a: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
-
- spi1_sleep_pins_a: spi1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
- <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
- <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
- };
- };
-
- usart1_pins_b: usart1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_idle_pins_b: usart1-idle-1 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_sleep_pins_b: usart1-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
- <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi
deleted file mode 100644
index dc3b09f..0000000
--- a/arch/arm/dts/stm32mp15-scmi.dtsi
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- scmi: scmi {
- compatible = "linaro,scmi-optee";
- #address-cells = <1>;
- #size-cells = <0>;
- linaro,optee-channel-id = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
-
- scmi_voltd: protocol@17 {
- reg = <0x17>;
-
- scmi_reguls: regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_reg11: regulator@0 {
- reg = <0>;
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- scmi_reg18: regulator@1 {
- reg = <1>;
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- scmi_usb33: regulator@2 {
- reg = <2>;
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
- };
- };
-};
-
-®11 {
- status = "disabled";
-};
-
-®18 {
- status = "disabled";
-};
-
-&usb33 {
- status = "disabled";
-};
-
-&usbotg_hs {
- usb33d-supply = <&scmi_usb33>;
-};
-
-&usbphyc {
- vdda1v1-supply = <&scmi_reg11>;
- vdda1v8-supply = <&scmi_reg18>;
-};
-
-/delete-node/ &clk_hse;
-/delete-node/ &clk_hsi;
-/delete-node/ &clk_lse;
-/delete-node/ &clk_lsi;
-/delete-node/ &clk_csi;
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
index 3f57bd5..327d776 100644
--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
@@ -106,6 +106,10 @@
operating-points-v2 = <&cpu0_opp_table>;
};
+&etzpc {
+ bootph-all;
+};
+
&gpioa {
bootph-all;
};
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
deleted file mode 100644
index e277140..0000000
--- a/arch/arm/dts/stm32mp151.dtsi
+++ /dev/null
@@ -1,1868 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
-#include <dt-bindings/reset/stm32mp1-resets.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
- device_type = "cpu";
- reg = <0>;
- operating-points-v2 = <&cpu0_opp_table>;
- nvmem-cells = <&part_number_otp>;
- nvmem-cell-names = "part_number";
- };
- };
-
- cpu0_opp_table: cpu0-opp-table {
- compatible = "operating-points-v2";
- opp-shared;
- opp-650000000 {
- opp-hz = /bits/ 64 <650000000>;
- opp-microvolt = <1200000>;
- opp-supported-hw = <0x1>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1350000>;
- opp-supported-hw = <0x2>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
- interrupt-parent = <&intc>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- intc: interrupt-controller@a0021000 {
- compatible = "arm,cortex-a7-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xa0021000 0x1000>,
- <0xa0022000 0x2000>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- interrupt-parent = <&intc>;
- };
-
- clocks {
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
- clk_hsi: clk-hsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- clk_lse: clk-lse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_csi: clk-csi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <4000000>;
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&dts>;
-
- trips {
- cpu_alert1: cpu-alert1 {
- temperature = <85000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- cpu-crit {
- temperature = <120000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
-
- cooling-maps {
- };
- };
- };
-
- booster: regulator-booster {
- compatible = "st,stm32mp1-booster";
- st,syscfg = <&syscfg>;
- status = "disabled";
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
-
- timers2: timer@40000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40000000 0x400>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM2_K>;
- clock-names = "int";
- dmas = <&dmamux1 18 0x400 0x1>,
- <&dmamux1 19 0x400 0x1>,
- <&dmamux1 20 0x400 0x1>,
- <&dmamux1 21 0x400 0x1>,
- <&dmamux1 22 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@1 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers3: timer@40001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40001000 0x400>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM3_K>;
- clock-names = "int";
- dmas = <&dmamux1 23 0x400 0x1>,
- <&dmamux1 24 0x400 0x1>,
- <&dmamux1 25 0x400 0x1>,
- <&dmamux1 26 0x400 0x1>,
- <&dmamux1 27 0x400 0x1>,
- <&dmamux1 28 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@2 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <2>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers4: timer@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40002000 0x400>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM4_K>;
- clock-names = "int";
- dmas = <&dmamux1 29 0x400 0x1>,
- <&dmamux1 30 0x400 0x1>,
- <&dmamux1 31 0x400 0x1>,
- <&dmamux1 32 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@3 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <3>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers5: timer@40003000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40003000 0x400>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM5_K>;
- clock-names = "int";
- dmas = <&dmamux1 55 0x400 0x1>,
- <&dmamux1 56 0x400 0x1>,
- <&dmamux1 57 0x400 0x1>,
- <&dmamux1 58 0x400 0x1>,
- <&dmamux1 59 0x400 0x1>,
- <&dmamux1 60 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers6: timer@40004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40004000 0x400>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM6_K>;
- clock-names = "int";
- dmas = <&dmamux1 69 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
- };
-
- timers7: timer@40005000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40005000 0x400>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM7_K>;
- clock-names = "int";
- dmas = <&dmamux1 70 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
- };
-
- timers12: timer@40006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40006000 0x400>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM12_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
- };
-
- timers13: timer@40007000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40007000 0x400>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM13_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@12 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <12>;
- status = "disabled";
- };
- };
-
- timers14: timer@40008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40008000 0x400>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM14_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@13 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <13>;
- status = "disabled";
- };
- };
-
- lptimer1: timer@40009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40009000 0x400>;
- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM1_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- spi2: spi@4000b000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI2_K>;
- resets = <&rcc SPI2_R>;
- dmas = <&dmamux1 39 0x400 0x05>,
- <&dmamux1 40 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s2: audio-controller@4000b000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 39 0x400 0x01>,
- <&dmamux1 40 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi3: spi@4000c000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x4000c000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI3_K>;
- resets = <&rcc SPI3_R>;
- dmas = <&dmamux1 61 0x400 0x05>,
- <&dmamux1 62 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s3: audio-controller@4000c000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
- reg = <0x4000c000 0x400>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 61 0x400 0x01>,
- <&dmamux1 62 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spdifrx: audio-controller@4000d000 {
- compatible = "st,stm32h7-spdifrx";
- #sound-dai-cells = <0>;
- reg = <0x4000d000 0x400>;
- clocks = <&rcc SPDIF_K>;
- clock-names = "kclk";
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 93 0x400 0x01>,
- <&dmamux1 94 0x400 0x01>;
- dma-names = "rx", "rx-ctrl";
- status = "disabled";
- };
-
- usart2: serial@4000e000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4000e000 0x400>;
- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART2_K>;
- wakeup-source;
- dmas = <&dmamux1 43 0x400 0x15>,
- <&dmamux1 44 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- usart3: serial@4000f000 {
- compatible = "st,stm32h7-uart";
- reg = <0x4000f000 0x400>;
- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART3_K>;
- wakeup-source;
- dmas = <&dmamux1 45 0x400 0x15>,
- <&dmamux1 46 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart4: serial@40010000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40010000 0x400>;
- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART4_K>;
- wakeup-source;
- dmas = <&dmamux1 63 0x400 0x15>,
- <&dmamux1 64 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart5: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART5_K>;
- wakeup-source;
- dmas = <&dmamux1 65 0x400 0x15>,
- <&dmamux1 66 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c1: i2c@40012000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40012000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C1_K>;
- resets = <&rcc I2C1_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x1>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c2: i2c@40013000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40013000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C2_K>;
- resets = <&rcc I2C2_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x2>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c3: i2c@40014000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40014000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C3_K>;
- resets = <&rcc I2C3_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x4>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- i2c5: i2c@40015000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x40015000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C5_K>;
- resets = <&rcc I2C5_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x10>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- cec: cec@40016000 {
- compatible = "st,stm32-cec";
- reg = <0x40016000 0x400>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CEC_K>, <&rcc CEC>;
- clock-names = "cec", "hdmi-cec";
- status = "disabled";
- };
-
- dac: dac@40017000 {
- compatible = "st,stm32h7-dac-core";
- reg = <0x40017000 0x400>;
- clocks = <&rcc DAC12>;
- clock-names = "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dac1: dac@1 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <1>;
- status = "disabled";
- };
-
- dac2: dac@2 {
- compatible = "st,stm32-dac";
- #io-channel-cells = <1>;
- reg = <2>;
- status = "disabled";
- };
- };
-
- uart7: serial@40018000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40018000 0x400>;
- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART7_K>;
- wakeup-source;
- dmas = <&dmamux1 79 0x400 0x15>,
- <&dmamux1 80 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart8: serial@40019000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40019000 0x400>;
- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc UART8_K>;
- wakeup-source;
- dmas = <&dmamux1 81 0x400 0x15>,
- <&dmamux1 82 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- timers1: timer@44000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44000000 0x400>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM1_K>;
- clock-names = "int";
- dmas = <&dmamux1 11 0x400 0x1>,
- <&dmamux1 12 0x400 0x1>,
- <&dmamux1 13 0x400 0x1>,
- <&dmamux1 14 0x400 0x1>,
- <&dmamux1 15 0x400 0x1>,
- <&dmamux1 16 0x400 0x1>,
- <&dmamux1 17 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@0 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- timers8: timer@44001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44001000 0x400>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "brk", "up", "trg-com", "cc";
- clocks = <&rcc TIM8_K>;
- clock-names = "int";
- dmas = <&dmamux1 47 0x400 0x1>,
- <&dmamux1 48 0x400 0x1>,
- <&dmamux1 49 0x400 0x1>,
- <&dmamux1 50 0x400 0x1>,
- <&dmamux1 51 0x400 0x1>,
- <&dmamux1 52 0x400 0x1>,
- <&dmamux1 53 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4",
- "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@7 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <7>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
- };
-
- usart6: serial@44003000 {
- compatible = "st,stm32h7-uart";
- reg = <0x44003000 0x400>;
- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART6_K>;
- wakeup-source;
- dmas = <&dmamux1 71 0x400 0x15>,
- <&dmamux1 72 0x400 0x11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi1: spi@44004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x44004000 0x400>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI1_K>;
- resets = <&rcc SPI1_R>;
- dmas = <&dmamux1 37 0x400 0x05>,
- <&dmamux1 38 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2s1: audio-controller@44004000 {
- compatible = "st,stm32h7-i2s";
- #sound-dai-cells = <0>;
- reg = <0x44004000 0x400>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 37 0x400 0x01>,
- <&dmamux1 38 0x400 0x01>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- spi4: spi@44005000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x44005000 0x400>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI4_K>;
- resets = <&rcc SPI4_R>;
- dmas = <&dmamux1 83 0x400 0x05>,
- <&dmamux1 84 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- timers15: timer@44006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44006000 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM15_K>;
- clock-names = "int";
- dmas = <&dmamux1 105 0x400 0x1>,
- <&dmamux1 106 0x400 0x1>,
- <&dmamux1 107 0x400 0x1>,
- <&dmamux1 108 0x400 0x1>;
- dma-names = "ch1", "up", "trig", "com";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@14 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <14>;
- status = "disabled";
- };
- };
-
- timers16: timer@44007000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44007000 0x400>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM16_K>;
- clock-names = "int";
- dmas = <&dmamux1 109 0x400 0x1>,
- <&dmamux1 110 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
- timer@15 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <15>;
- status = "disabled";
- };
- };
-
- timers17: timer@44008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x44008000 0x400>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM17_K>;
- clock-names = "int";
- dmas = <&dmamux1 111 0x400 0x1>,
- <&dmamux1 112 0x400 0x1>;
- dma-names = "ch1", "up";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@16 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <16>;
- status = "disabled";
- };
- };
-
- spi5: spi@44009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x44009000 0x400>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI5_K>;
- resets = <&rcc SPI5_R>;
- dmas = <&dmamux1 85 0x400 0x05>,
- <&dmamux1 86 0x400 0x05>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai1: sai@4400a000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x4400a000 0x400>;
- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI1_R>;
- status = "disabled";
-
- sai1a: audio-controller@4400a004 {
- #sound-dai-cells = <0>;
-
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 87 0x400 0x01>;
- status = "disabled";
- };
-
- sai1b: audio-controller@4400a024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI1_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 88 0x400 0x01>;
- status = "disabled";
- };
- };
-
- sai2: sai@4400b000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x4400b000 0x400>;
- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI2_R>;
- status = "disabled";
-
- sai2a: audio-controller@4400b004 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x20>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 89 0x400 0x01>;
- status = "disabled";
- };
-
- sai2b: audio-controller@4400b024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 90 0x400 0x01>;
- status = "disabled";
- };
- };
-
- sai3: sai@4400c000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x4400c000 0x400>;
- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI3_R>;
- status = "disabled";
-
- sai3a: audio-controller@4400c004 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x20>;
- clocks = <&rcc SAI3_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 113 0x400 0x01>;
- status = "disabled";
- };
-
- sai3b: audio-controller@4400c024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI3_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 114 0x400 0x01>;
- status = "disabled";
- };
- };
-
- dfsdm: dfsdm@4400d000 {
- compatible = "st,stm32mp1-dfsdm";
- reg = <0x4400d000 0x800>;
- clocks = <&rcc DFSDM_K>;
- clock-names = "dfsdm";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dfsdm0: filter@0 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <0>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 101 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm1: filter@1 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <1>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 102 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm2: filter@2 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <2>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 103 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm3: filter@3 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <3>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 104 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm4: filter@4 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <4>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 91 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- dfsdm5: filter@5 {
- compatible = "st,stm32-dfsdm-adc";
- #io-channel-cells = <1>;
- reg = <5>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmamux1 92 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
- };
-
- dma1: dma-controller@48000000 {
- compatible = "st,stm32-dma";
- reg = <0x48000000 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA1>;
- resets = <&rcc DMA1_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dma2: dma-controller@48001000 {
- compatible = "st,stm32-dma";
- reg = <0x48001000 0x400>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc DMA2>;
- resets = <&rcc DMA2_R>;
- #dma-cells = <4>;
- st,mem2mem;
- dma-requests = <8>;
- };
-
- dmamux1: dma-router@48002000 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x48002000 0x40>;
- #dma-cells = <3>;
- dma-requests = <128>;
- dma-masters = <&dma1 &dma2>;
- dma-channels = <16>;
- clocks = <&rcc DMAMUX>;
- resets = <&rcc DMAMUX_R>;
- };
-
- adc: adc@48003000 {
- compatible = "st,stm32mp1-adc-core";
- reg = <0x48003000 0x400>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc ADC12>, <&rcc ADC12_K>;
- clock-names = "bus", "adc";
- interrupt-controller;
- st,syscfg = <&syscfg>;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- adc1: adc@0 {
- compatible = "st,stm32mp1-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0>;
- interrupt-parent = <&adc>;
- interrupts = <0>;
- dmas = <&dmamux1 9 0x400 0x01>;
- dma-names = "rx";
- status = "disabled";
- };
-
- adc2: adc@100 {
- compatible = "st,stm32mp1-adc";
- #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x100>;
- interrupt-parent = <&adc>;
- interrupts = <1>;
- dmas = <&dmamux1 10 0x400 0x01>;
- dma-names = "rx";
- nvmem-cells = <&vrefint>;
- nvmem-cell-names = "vrefint";
- status = "disabled";
- channel@13 {
- reg = <13>;
- label = "vrefint";
- };
- channel@14 {
- reg = <14>;
- label = "vddcore";
- };
- };
- };
-
- sdmmc3: mmc@48004000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00253180>;
- reg = <0x48004000 0x400>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC3_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC3_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- usbotg_hs: usb-otg@49000000 {
- compatible = "st,stm32mp15-hsotg", "snps,dwc2";
- reg = <0x49000000 0x10000>;
- clocks = <&rcc USBO_K>, <&usbphyc>;
- clock-names = "otg", "utmi";
- resets = <&rcc USBO_R>;
- reset-names = "dwc2";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- g-rx-fifo-size = <512>;
- g-np-tx-fifo-size = <32>;
- g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
- dr_mode = "otg";
- otg-rev = <0x200>;
- usb33d-supply = <&usb33>;
- status = "disabled";
- };
-
- ipcc: mailbox@4c001000 {
- compatible = "st,stm32mp1-ipcc";
- #mbox-cells = <1>;
- reg = <0x4c001000 0x400>;
- st,proc-id = <0>;
- interrupts-extended =
- <&exti 61 1>,
- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rx", "tx";
- clocks = <&rcc IPCC>;
- wakeup-source;
- status = "disabled";
- };
-
- dcmi: dcmi@4c006000 {
- compatible = "st,stm32-dcmi";
- reg = <0x4c006000 0x400>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc CAMITF_R>;
- clocks = <&rcc DCMI>;
- clock-names = "mclk";
- dmas = <&dmamux1 75 0x400 0x01>;
- dma-names = "tx";
- status = "disabled";
- };
-
- rcc: rcc@50000000 {
- compatible = "st,stm32mp1-rcc", "syscon";
- reg = <0x50000000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
- <&clk_lse>, <&clk_lsi>;
- };
-
- pwr_regulators: pwr@50001000 {
- compatible = "st,stm32mp1,pwr-reg";
- reg = <0x50001000 0x10>;
-
- reg11: reg11 {
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- reg18: reg18 {
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- usb33: usb33 {
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
-
- pwr_mcu: pwr_mcu@50001014 {
- compatible = "st,stm32mp151-pwr-mcu", "syscon";
- reg = <0x50001014 0x4>;
- };
-
- exti: interrupt-controller@5000d000 {
- compatible = "st,stm32mp1-exti", "syscon";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000d000 0x400>;
- };
-
- syscfg: syscon@50020000 {
- compatible = "st,stm32mp157-syscfg", "syscon";
- reg = <0x50020000 0x400>;
- clocks = <&rcc SYSCFG>;
- };
-
- lptimer2: timer@50021000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50021000 0x400>;
- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM2_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@1 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <1>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- lptimer3: timer@50022000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x50022000 0x400>;
- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM3_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@2 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <2>;
- status = "disabled";
- };
- };
-
- lptimer4: timer@50023000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50023000 0x400>;
- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM4_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- lptimer5: timer@50024000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50024000 0x400>;
- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM5_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- vrefbuf: vrefbuf@50025000 {
- compatible = "st,stm32-vrefbuf";
- reg = <0x50025000 0x8>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <2500000>;
- clocks = <&rcc VREF>;
- status = "disabled";
- };
-
- sai4: sai@50027000 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x50027000 0x400>;
- reg = <0x50027000 0x4>, <0x500273f0 0x10>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rcc SAI4_R>;
- status = "disabled";
-
- sai4a: audio-controller@50027004 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x20>;
- clocks = <&rcc SAI4_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 99 0x400 0x01>;
- status = "disabled";
- };
-
- sai4b: audio-controller@50027024 {
- #sound-dai-cells = <0>;
- compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x20>;
- clocks = <&rcc SAI4_K>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 100 0x400 0x01>;
- status = "disabled";
- };
- };
-
- dts: thermal@50028000 {
- compatible = "st,stm32-thermal";
- reg = <0x50028000 0x100>;
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc TMPSENS>;
- clock-names = "pclk";
- #thermal-sensor-cells = <0>;
- status = "disabled";
- };
-
- hash1: hash@54002000 {
- compatible = "st,stm32f756-hash";
- reg = <0x54002000 0x400>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc HASH1>;
- resets = <&rcc HASH1_R>;
- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
- dma-names = "in";
- dma-maxburst = <2>;
- status = "disabled";
- };
-
- rng1: rng@54003000 {
- compatible = "st,stm32-rng";
- reg = <0x54003000 0x400>;
- clocks = <&rcc RNG1_K>;
- resets = <&rcc RNG1_R>;
- status = "disabled";
- };
-
- mdma1: dma-controller@58000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x58000000 0x1000>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc MDMA>;
- resets = <&rcc MDMA_R>;
- #dma-cells = <5>;
- dma-channels = <32>;
- dma-requests = <48>;
- };
-
- fmc: memory-controller@58002000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "st,stm32mp1-fmc2-ebi";
- reg = <0x58002000 0x1000>;
- clocks = <&rcc FMC_K>;
- resets = <&rcc FMC_R>;
- status = "disabled";
-
- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
- <4 0 0x80000000 0x10000000>; /* NAND */
-
- nand-controller@4,0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32mp1-fmc2-nfc";
- reg = <4 0x00000000 0x1000>,
- <4 0x08010000 0x1000>,
- <4 0x08020000 0x1000>,
- <4 0x01000000 0x1000>,
- <4 0x09010000 0x1000>,
- <4 0x09020000 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
- <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
- dma-names = "tx", "rx", "ecc";
- status = "disabled";
- };
- };
-
- qspi: spi@58003000 {
- compatible = "st,stm32f469-qspi";
- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
- reg-names = "qspi", "qspi_mm";
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
- <&mdma1 22 0x2 0x10100008 0x0 0x0>;
- dma-names = "tx", "rx";
- clocks = <&rcc QSPI_K>;
- resets = <&rcc QSPI_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sdmmc1: mmc@58005000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00253180>;
- reg = <0x58005000 0x1000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC1_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC1_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- sdmmc2: mmc@58007000 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00253180>;
- reg = <0x58007000 0x1000>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SDMMC2_K>;
- clock-names = "apb_pclk";
- resets = <&rcc SDMMC2_R>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <120000000>;
- status = "disabled";
- };
-
- crc1: crc@58009000 {
- compatible = "st,stm32f7-crc";
- reg = <0x58009000 0x400>;
- clocks = <&rcc CRC1>;
- status = "disabled";
- };
-
- ethernet0: ethernet@5800a000 {
- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
- reg = <0x5800a000 0x2000>;
- reg-names = "stmmaceth";
- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clock-names = "stmmaceth",
- "mac-clk-tx",
- "mac-clk-rx",
- "eth-ck",
- "ptp_ref",
- "ethstp";
- clocks = <&rcc ETHMAC>,
- <&rcc ETHTX>,
- <&rcc ETHRX>,
- <&rcc ETHCK_K>,
- <&rcc ETHPTP_K>,
- <&rcc ETHSTP>;
- st,syscon = <&syscfg 0x4>;
- snps,mixed-burst;
- snps,pbl = <2>;
- snps,en-tx-lpi-clockgating;
- snps,axi-config = <&stmmac_axi_config_0>;
- snps,tso;
- status = "disabled";
-
- stmmac_axi_config_0: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
- };
-
- usbh_ohci: usb@5800c000 {
- compatible = "generic-ohci";
- reg = <0x5800c000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- usbh_ehci: usb@5800d000 {
- compatible = "generic-ehci";
- reg = <0x5800d000 0x1000>;
- clocks = <&usbphyc>, <&rcc USBH>;
- resets = <&rcc USBH_R>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- companion = <&usbh_ohci>;
- status = "disabled";
- };
-
- ltdc: display-controller@5a001000 {
- compatible = "st,stm32-ltdc";
- reg = <0x5a001000 0x400>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LTDC_PX>;
- clock-names = "lcd";
- resets = <&rcc LTDC_R>;
- status = "disabled";
- };
-
- iwdg2: watchdog@5a002000 {
- compatible = "st,stm32mp1-iwdg";
- reg = <0x5a002000 0x400>;
- clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
- clock-names = "pclk", "lsi";
- status = "disabled";
- };
-
- usbphyc: usbphyc@5a006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "st,stm32mp1-usbphyc";
- reg = <0x5a006000 0x1000>;
- clocks = <&rcc USBPHY_K>;
- resets = <&rcc USBPHY_R>;
- vdda1v1-supply = <®11>;
- vdda1v8-supply = <®18>;
- status = "disabled";
-
- usbphyc_port0: usb-phy@0 {
- #phy-cells = <0>;
- reg = <0>;
- };
-
- usbphyc_port1: usb-phy@1 {
- #phy-cells = <1>;
- reg = <1>;
- };
- };
-
- usart1: serial@5c000000 {
- compatible = "st,stm32h7-uart";
- reg = <0x5c000000 0x400>;
- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc USART1_K>;
- wakeup-source;
- status = "disabled";
- };
-
- spi6: spi@5c001000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x5c001000 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI6_K>;
- resets = <&rcc SPI6_R>;
- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
- <&mdma1 35 0x0 0x40002 0x0 0x0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c4: i2c@5c002000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x5c002000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C4_K>;
- resets = <&rcc I2C4_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x8>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- rtc: rtc@5c004000 {
- compatible = "st,stm32mp1-rtc";
- reg = <0x5c004000 0x400>;
- clocks = <&rcc RTCAPB>, <&rcc RTC>;
- clock-names = "pclk", "rtc_ck";
- interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- bsec: efuse@5c005000 {
- compatible = "st,stm32mp15-bsec";
- reg = <0x5c005000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- part_number_otp: part-number-otp@4 {
- reg = <0x4 0x1>;
- };
- vrefint: vrefin-cal@52 {
- reg = <0x52 0x2>;
- };
- ts_cal1: calib@5c {
- reg = <0x5c 0x2>;
- };
- ts_cal2: calib@5e {
- reg = <0x5e 0x2>;
- };
- };
-
- i2c6: i2c@5c009000 {
- compatible = "st,stm32mp15-i2c";
- reg = <0x5c009000 0x400>;
- interrupt-names = "event", "error";
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C6_K>;
- resets = <&rcc I2C6_R>;
- #address-cells = <1>;
- #size-cells = <0>;
- st,syscfg-fmp = <&syscfg 0x4 0x20>;
- wakeup-source;
- i2c-analog-filter;
- status = "disabled";
- };
-
- tamp: tamp@5c00a000 {
- compatible = "st,stm32-tamp", "syscon", "simple-mfd";
- reg = <0x5c00a000 0x400>;
- };
-
- /*
- * Break node order to solve dependency probe issue between
- * pinctrl and exti.
- */
- pinctrl: pinctrl@50002000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-pinctrl";
- ranges = <0 0x50002000 0xa400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioa: gpio@50002000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA>;
- st,bank-name = "GPIOA";
- status = "disabled";
- };
-
- gpiob: gpio@50003000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOB>;
- st,bank-name = "GPIOB";
- status = "disabled";
- };
-
- gpioc: gpio@50004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOC>;
- st,bank-name = "GPIOC";
- status = "disabled";
- };
-
- gpiod: gpio@50005000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x400>;
- clocks = <&rcc GPIOD>;
- st,bank-name = "GPIOD";
- status = "disabled";
- };
-
- gpioe: gpio@50006000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x400>;
- clocks = <&rcc GPIOE>;
- st,bank-name = "GPIOE";
- status = "disabled";
- };
-
- gpiof: gpio@50007000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x400>;
- clocks = <&rcc GPIOF>;
- st,bank-name = "GPIOF";
- status = "disabled";
- };
-
- gpiog: gpio@50008000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x400>;
- clocks = <&rcc GPIOG>;
- st,bank-name = "GPIOG";
- status = "disabled";
- };
-
- gpioh: gpio@50009000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x400>;
- clocks = <&rcc GPIOH>;
- st,bank-name = "GPIOH";
- status = "disabled";
- };
-
- gpioi: gpio@5000a000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x400>;
- clocks = <&rcc GPIOI>;
- st,bank-name = "GPIOI";
- status = "disabled";
- };
-
- gpioj: gpio@5000b000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x9000 0x400>;
- clocks = <&rcc GPIOJ>;
- st,bank-name = "GPIOJ";
- status = "disabled";
- };
-
- gpiok: gpio@5000c000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xa000 0x400>;
- clocks = <&rcc GPIOK>;
- st,bank-name = "GPIOK";
- status = "disabled";
- };
- };
-
- pinctrl_z: pinctrl@54004000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-z-pinctrl";
- ranges = <0 0x54004000 0x400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioz: gpio@54004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x400>;
- clocks = <&rcc GPIOZ>;
- st,bank-name = "GPIOZ";
- st,bank-ioport = <11>;
- status = "disabled";
- };
- };
- };
-
- mlahb: ahb {
- compatible = "st,mlahb", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- dma-ranges = <0x00000000 0x38000000 0x10000>,
- <0x10000000 0x10000000 0x60000>,
- <0x30000000 0x30000000 0x60000>;
-
- m4_rproc: m4@10000000 {
- compatible = "st,stm32mp1-m4";
- reg = <0x10000000 0x40000>,
- <0x30000000 0x40000>,
- <0x38000000 0x10000>;
- resets = <&rcc MCU_R>;
- reset-names = "mcu_rst";
- st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
- st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
- st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi
deleted file mode 100644
index 486084e..0000000
--- a/arch/arm/dts/stm32mp153.dtsi
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32mp151.dtsi"
-
-/ {
- cpus {
- cpu1: cpu@1 {
- compatible = "arm,cortex-a7";
- clock-frequency = <650000000>;
- device_type = "cpu";
- reg = <1>;
- };
- };
-
- arm-pmu {
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- timer {
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- soc {
- m_can1: can@4400e000 {
- compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- m_can2: can@4400f000 {
- compatible = "bosch,m_can";
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
deleted file mode 100644
index 6197d87..0000000
--- a/arch/arm/dts/stm32mp157.dtsi
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include "stm32mp153.dtsi"
-
-/ {
- soc {
- gpu: gpu@59000000 {
- compatible = "vivante,gc";
- reg = <0x59000000 0x800>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc GPU>, <&rcc GPU_K>;
- clock-names = "bus" ,"core";
- resets = <&rcc GPU_R>;
- };
-
- dsi: dsi@5a000000 {
- compatible = "st,stm32-dsi";
- reg = <0x5a000000 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
- clock-names = "pclk", "ref", "px_clk";
- phy-dsi-supply = <®18>;
- resets = <&rcc DSI_R>;
- reset-names = "apb";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts
deleted file mode 100644
index afcd628..0000000
--- a/arch/arm/dts/stm32mp157a-dk1-scmi.dts
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157a-dk1.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
- compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
-
- reserved-memory {
- optee@de000000 {
- reg = <0xde000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
deleted file mode 100644
index 0da3667..0000000
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxac-pinctrl.dtsi"
-#include "stm32mp15xx-dkx.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
- compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
-
- aliases {
- ethernet0 = ðernet0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
deleted file mode 100644
index 1f75f1d..0000000
--- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/dts-v1/;
-#include "stm32mp157.dtsi"
-#include "stm32mp157a-icore-stm32mp1.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
- compatible = "engicam,icore-stm32mp1-ctouch2",
- "engicam,icore-stm32mp1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&sdmmc1 {
- bus-width = <4>;
- disable-wp;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- st,neg-edge;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
deleted file mode 100644
index f4a4942..0000000
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/dts-v1/;
-#include "stm32mp157.dtsi"
-#include "stm32mp157a-microgea-stm32mp1.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
- compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
- "engicam,microgea-stm32mp1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- serial1 = &uart8;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
- default-on;
- };
-
- lcd_3v3: regulator-lcd-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "lcd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- power-supply = <&panel_pwr>;
- };
-
- panel_pwr: regulator-panel-pwr {
- compatible = "regulator-fixed";
- regulator-name = "panel_pwr";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>;
- regulator-always-on;
- };
-
- panel {
- compatible = "auo,b101aw03";
- backlight = <&backlight>;
- enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
- power-supply = <&lcd_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <<dc_ep0_out>;
- };
- };
- };
-};
-
-&i2c2 {
- i2c-scl-falling-time-ns = <20>;
- i2c-scl-rising-time-ns = <185>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_pins_a>;
- pinctrl-1 = <&i2c2_sleep_pins_a>;
- status = "okay";
-};
-
-<dc {
- pinctrl-names = "default";
- pinctrl-0 = <<dc_pins>;
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ltdc_ep0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
-&pinctrl {
- ltdc_pins: ltdc-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
- <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
- <STM32_PINMUX('H', 11, AF14)>, /* LTDC_R5 */
- <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
- <STM32_PINMUX('D', 9, AF14)>, /* LTDC_B0 */
- <STM32_PINMUX('E', 5, AF14)>, /* LTDC_G0 */
- <STM32_PINMUX('E', 6, AF14)>, /* LTDC_G1 */
- <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
- <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
- <STM32_PINMUX('G', 7, AF14)>, /* LTDC_CLK */
- <STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */
- <STM32_PINMUX('H', 2, AF14)>, /* LTDC_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LTDC_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
- <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
- <STM32_PINMUX('H', 14, AF14)>, /* LTDC_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
- <STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */
- <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
- <STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */
- <STM32_PINMUX('I', 4, AF14)>, /* LTDC_B4 */
- <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LTDC_B6 */
- <STM32_PINMUX('I', 7, AF14)>, /* LTDC_B7 */
- <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
- <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-};
-
-&sdmmc1 {
- bus-width = <4>;
- disable-wp;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- st,neg-edge;
- vmmc-supply = <&vdd>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-/* J31: RS323 */
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
deleted file mode 100644
index b9d0d3d..0000000
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/dts-v1/;
-#include "stm32mp157.dtsi"
-#include "stm32mp157a-microgea-stm32mp1.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
- compatible = "engicam,microgea-stm32mp1-microdev2.0",
- "engicam,microgea-stm32mp1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- serial1 = &uart8;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&sdmmc1 {
- bus-width = <4>;
- disable-wp;
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- st,neg-edge;
- vmmc-supply = <&vdd>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-/* J31: RS323 */
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
deleted file mode 100644
index 0b85175..0000000
--- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-/ {
- compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x10000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
- };
-
- vin: regulator-vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vddcore: regulator-vddcore {
- compatible = "regulator-fixed";
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- vin-supply = <&vin>;
- };
-
- vdd: regulator-vdd {
- compatible = "regulator-fixed";
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <&vin>;
- };
-
- vddq_ddr: regulator-vddq-ddr {
- compatible = "regulator-fixed";
- regulator-name = "vddq_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- vin-supply = <&vin>;
- };
-};
-
-&dts {
- status = "okay";
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_a>;
- pinctrl-1 = <&fmc_sleep_pins_a>;
- status = "okay";
-
- nand-controller@4,0 {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2{
- timeout-sec = <32>;
- status = "okay";
-};
-
-&m4_rproc{
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc{
- status = "okay";
-};
-
-&vrefbuf {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- vdda-supply = <&vdd>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts
deleted file mode 100644
index 39358d9..0000000
--- a/arch/arm/dts/stm32mp157c-dk2-scmi.dts
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157c-dk2.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
- compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
-
- reserved-memory {
- optee@de000000 {
- reg = <0xde000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cryp1 {
- clocks = <&scmi_clk CK_SCMI_CRYP1>;
- resets = <&scmi_reset RST_SCMI_CRYP1>;
-};
-
-&dsi {
- phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
deleted file mode 100644
index 510cca5..0000000
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxac-pinctrl.dtsi"
-#include "stm32mp15xx-dkx.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
- compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
-
- aliases {
- ethernet0 = ðernet0;
- serial3 = &usart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&cryp1 {
- status = "okay";
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>;
- reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
- power-supply = <&v3v3>;
- status = "okay";
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-&dsi_in {
- remote-endpoint = <<dc_ep1_out>;
-};
-
-&dsi_out {
- remote-endpoint = <&panel_in>;
-};
-
-&i2c1 {
- touchscreen@38 {
- compatible = "focaltech,ft6236";
- reg = <0x38>;
- interrupts = <2 2>;
- interrupt-parent = <&gpiof>;
- interrupt-controller;
- touchscreen-size-x = <480>;
- touchscreen-size-y = <800>;
- status = "okay";
- };
-};
-
-<dc {
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ltdc_ep1_out: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&usart2 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart2_pins_c>;
- pinctrl-1 = <&usart2_sleep_pins_c>;
- pinctrl-2 = <&usart2_idle_pins_c>;
- status = "disabled";
-};
diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dts
deleted file mode 100644
index 07ea765..0000000
--- a/arch/arm/dts/stm32mp157c-ed1-scmi.dts
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157c-ed1.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
- compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
-
- reserved-memory {
- optee@fe000000 {
- reg = <0xfe000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cryp1 {
- clocks = <&scmi_clk CK_SCMI_CRYP1>;
- resets = <&scmi_reset RST_SCMI_CRYP1>;
-};
-
-&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
deleted file mode 100644
index 66ed5f9..0000000
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ /dev/null
@@ -1,403 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15-pinctrl.dtsi"
-#include "stm32mp15xxaa-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
- model = "STMicroelectronics STM32MP157C eval daughter";
- compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
-
- aliases {
- serial0 = &uart4;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xC0000000 0x40000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
- };
-
- sd_switch: regulator-sd_switch {
- compatible = "regulator-gpio";
- regulator-name = "sd_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-type = "voltage";
- regulator-always-on;
-
- gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
- states = <1800000 0x1>,
- <2900000 0x0>;
- };
-
- vin: vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&adc {
- /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
- pinctrl-0 = <&adc1_in6_pins_a>;
- pinctrl-names = "default";
- vdd-supply = <&vdd>;
- vdda-supply = <&vdda>;
- vref-supply = <&vdda>;
- status = "disabled";
- adc1: adc@0 {
- status = "okay";
- channel@0 {
- reg = <0>;
- /* 16.5 ck_cycles sampling time */
- st,min-sample-time-ns = <400>;
- };
- channel@1 {
- reg = <1>;
- st,min-sample-time-ns = <400>;
- };
- channel@6 {
- reg = <6>;
- st,min-sample-time-ns = <400>;
- };
- };
-};
-
-&crc1 {
- status = "okay";
-};
-
-&cryp1 {
- status = "okay";
-};
-
-&dac {
- pinctrl-names = "default";
- pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
- vref-supply = <&vdda>;
- status = "disabled";
- dac1: dac@1 {
- status = "okay";
- };
- dac2: dac@2 {
- status = "okay";
- };
-};
-
-&dts {
- status = "okay";
-};
-
-&hash1 {
- status = "okay";
-};
-
-&i2c4 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_pins_a>;
- pinctrl-1 = <&i2c4_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- buck1-supply = <&vin>;
- buck2-supply = <&vin>;
- buck3-supply = <&vin>;
- buck4-supply = <&vin>;
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo4-supply = <&vin>;
- ldo5-supply = <&v3v3>;
- ldo6-supply = <&v3v3>;
- vref_ddr-supply = <&vin>;
- boost-supply = <&vin>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- vdda: ldo1 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v2v8: ldo2 {
- regulator-name = "v2v8";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdd_sd: ldo5 {
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
- mbox-names = "vq0", "vq1", "shutdown", "detach";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- status = "okay";
-};
-
-&sdmmc2 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- vqmmc-supply = <&vdd>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-
-&timers6 {
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- timer@5 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&usbotg_hs {
- vbus-supply = <&vbus_otg>;
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts
deleted file mode 100644
index 813086e..0000000
--- a/arch/arm/dts/stm32mp157c-ev1-scmi.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp157c-ev1.dts"
-#include "stm32mp15-scmi.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
- compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
- "st,stm32mp157";
-
- reserved-memory {
- optee@fe000000 {
- reg = <0xfe000000 0x2000000>;
- no-map;
- };
- };
-};
-
-&cpu0 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cpu1 {
- clocks = <&scmi_clk CK_SCMI_MPU>;
-};
-
-&cryp1 {
- clocks = <&scmi_clk CK_SCMI_CRYP1>;
- resets = <&scmi_reset RST_SCMI_CRYP1>;
-};
-
-&dsi {
- phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
-};
-
-&gpioz {
- clocks = <&scmi_clk CK_SCMI_GPIOZ>;
-};
-
-&hash1 {
- clocks = <&scmi_clk CK_SCMI_HASH1>;
- resets = <&scmi_reset RST_SCMI_HASH1>;
-};
-
-&i2c4 {
- clocks = <&scmi_clk CK_SCMI_I2C4>;
- resets = <&scmi_reset RST_SCMI_I2C4>;
-};
-
-&iwdg2 {
- clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
-};
-
-&m_can1 {
- clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
-};
-
-&mdma1 {
- resets = <&scmi_reset RST_SCMI_MDMA>;
-};
-
-&m4_rproc {
- /delete-property/ st,syscfg-holdboot;
- resets = <&scmi_reset RST_SCMI_MCU>,
- <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
-};
-
-&rcc {
- compatible = "st,stm32mp1-rcc-secure", "syscon";
- clock-names = "hse", "hsi", "csi", "lse", "lsi";
- clocks = <&scmi_clk CK_SCMI_HSE>,
- <&scmi_clk CK_SCMI_HSI>,
- <&scmi_clk CK_SCMI_CSI>,
- <&scmi_clk CK_SCMI_LSE>,
- <&scmi_clk CK_SCMI_LSI>;
-};
-
-&rng1 {
- clocks = <&scmi_clk CK_SCMI_RNG1>;
- resets = <&scmi_reset RST_SCMI_RNG1>;
-};
-
-&rtc {
- clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
-};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
deleted file mode 100644
index cd9c3ff..0000000
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ /dev/null
@@ -1,414 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-/dts-v1/;
-
-#include "stm32mp157c-ed1.dts"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/media/video-interfaces.h>
-
-/ {
- model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
- compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
-
- aliases {
- serial1 = &usart3;
- ethernet0 = ðernet0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- clocks {
- clk_ext_camera: clk-ext-camera {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- joystick {
- compatible = "gpio-keys";
- pinctrl-0 = <&joystick_pins>;
- pinctrl-names = "default";
- button-0 {
- label = "JoySel";
- linux,code = <KEY_ENTER>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
- };
- button-1 {
- label = "JoyDown";
- linux,code = <KEY_DOWN>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <1 IRQ_TYPE_EDGE_RISING>;
- };
- button-2 {
- label = "JoyLeft";
- linux,code = <KEY_LEFT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
- };
- button-3 {
- label = "JoyRight";
- linux,code = <KEY_RIGHT>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- };
- button-4 {
- label = "JoyUp";
- linux,code = <KEY_UP>;
- interrupt-parent = <&stmfx_pinctrl>;
- interrupts = <4 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- panel_backlight: panel-backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
- default-on;
- status = "okay";
- };
-};
-
-&cec {
- pinctrl-names = "default";
- pinctrl-0 = <&cec_pins_a>;
- status = "okay";
-};
-
-&dcmi {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dcmi_pins_a>;
- pinctrl-1 = <&dcmi_sleep_pins_a>;
-
- port {
- dcmi_0: endpoint {
- remote-endpoint = <&ov5640_0>;
- bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
- bus-width = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
-&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- panel@0 {
- compatible = "raydium,rm68200";
- reg = <0>;
- reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
- backlight = <&panel_backlight>;
- power-supply = <&v3v3>;
- status = "okay";
-
- port {
- dsi_panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
-};
-
-&dsi_in {
- remote-endpoint = <<dc_ep0_out>;
-};
-
-&dsi_out {
- remote-endpoint = <&dsi_panel_in>;
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&fmc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&fmc_pins_a>;
- pinctrl-1 = <&fmc_sleep_pins_a>;
- status = "okay";
-
- nand-controller@4,0 {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-};
-
-&i2c2 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_pins_a>;
- pinctrl-1 = <&i2c2_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- ov5640: camera@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&clk_ext_camera>;
- clock-names = "xclk";
- AVDD-supply = <&v2v8>;
- DOVDD-supply = <&v2v8>;
- DVDD-supply = <&v2v8>;
- powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
- reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
- rotation = <180>;
- status = "okay";
-
- port {
- ov5640_0: endpoint {
- remote-endpoint = <&dcmi_0>;
- bus-width = <8>;
- data-shift = <2>; /* lines 9:2 are used */
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
- };
-
- stmfx: stmfx@42 {
- compatible = "st,stmfx-0300";
- reg = <0x42>;
- interrupts = <8 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpioi>;
- vdd-supply = <&v3v3>;
-
- stmfx_pinctrl: pinctrl {
- compatible = "st,stmfx-0300-pinctrl";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&stmfx_pinctrl 0 0 24>;
-
- joystick_pins: joystick-pins {
- pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- bias-pull-down;
- };
- };
- };
-};
-
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-<dc {
- status = "okay";
-
- port {
- ltdc_ep0_out: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
-};
-
-&m_can1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&m_can1_pins_a>;
- pinctrl-1 = <&m_can1_sleep_pins_a>;
- status = "okay";
-};
-
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a
- &qspi_bk1_pins_a
- &qspi_cs1_pins_a
- &qspi_bk2_pins_a
- &qspi_cs2_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a
- &qspi_bk1_sleep_pins_a
- &qspi_cs1_sleep_pins_a
- &qspi_bk2_sleep_pins_a
- &qspi_cs2_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash0: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- flash1: flash@1 {
- compatible = "jedec,spi-nor";
- reg = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "disabled";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>;
- status = "disabled";
-};
-
-&timers2 {
- /* spare dmas for other usage (un-delete to enable pwm capture) */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-1 = <&pwm2_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@1 {
- status = "okay";
- };
-};
-
-&timers8 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-1 = <&pwm8_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@7 {
- status = "okay";
- };
-};
-
-&timers12 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-1 = <&pwm12_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@11 {
- status = "okay";
- };
-};
-
-&usart3 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart3_pins_b>;
- pinctrl-1 = <&usart3_sleep_pins_b>;
- pinctrl-2 = <&usart3_idle_pins_b>;
- /*
- * HW flow control USART3_RTS is optional, and isn't default wired to
- * the connector. SB23 needs to be soldered in order to use it, and R77
- * (ETH_CLK) should be removed.
- */
- uart-has-rtscts;
- status = "disabled";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- /* onboard HUB */
- hub@1 {
- compatible = "usb424,2514";
- reg = <1>;
- vdd-supply = <&v3v3>;
- };
-};
-
-&usbotg_hs {
- pinctrl-0 = <&usbotg_hs_pins_a>;
- pinctrl-names = "default";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-
- connector {
- compatible = "usb-a-connector";
- vbus-supply = <&vbus_sw>;
- };
-};
-
-&usbphyc_port1 {
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-};
diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi
deleted file mode 100644
index b06a55a..0000000
--- a/arch/arm/dts/stm32mp15xc.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-/ {
- soc {
- cryp1: cryp@54001000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54001000 0x400>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
deleted file mode 100644
index 511113f..0000000
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ /dev/null
@@ -1,741 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x20000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
- };
-
- led {
- compatible = "gpio-leds";
- led-blue {
- label = "heartbeat";
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-
- sound {
- compatible = "audio-graph-card";
- label = "STM32MP15-DK";
- routing =
- "Playback" , "MCLK",
- "Capture" , "MCLK",
- "MICL" , "Mic Bias";
- dais = <&sai2a_port &sai2b_port &i2s2_port>;
- status = "okay";
- };
-
- vin: vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc12_usb_cc_pins_a>;
- vdd-supply = <&vdd>;
- vdda-supply = <&vdd>;
- vref-supply = <&vrefbuf>;
- status = "okay";
- adc1: adc@0 {
- status = "okay";
- /*
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
- * 5 * (56 + 47kOhms) * 5pF => 2.5us.
- * Use arbitrary margin here (e.g. 5us).
- */
- channel@18 {
- reg = <18>;
- st,min-sample-time-ns = <5000>;
- };
- channel@19 {
- reg = <19>;
- st,min-sample-time-ns = <5000>;
- };
- };
- adc2: adc@100 {
- status = "okay";
- /* USB Type-C CC1 & CC2 */
- channel@18 {
- reg = <18>;
- st,min-sample-time-ns = <5000>;
- };
- channel@19 {
- reg = <19>;
- st,min-sample-time-ns = <5000>;
- };
- };
-};
-
-&cec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cec_pins_b>;
- pinctrl-1 = <&cec_sleep_pins_b>;
- status = "okay";
-};
-
-&crc1 {
- status = "okay";
-};
-
-&dts {
- status = "okay";
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&hash1 {
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-1 = <&i2c1_sleep_pins_a>;
- i2c-scl-rising-time-ns = <100>;
- i2c-scl-falling-time-ns = <7>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-
- hdmi-transmitter@39 {
- compatible = "sil,sii9022";
- reg = <0x39>;
- iovcc-supply = <&v3v3_hdmi>;
- cvcc12-supply = <&v1v2_hdmi>;
- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpiog>;
- #sound-dai-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- sii9022_in: endpoint {
- remote-endpoint = <<dc_ep0_out>;
- };
- };
-
- port@3 {
- reg = <3>;
- sii9022_tx_endpoint: endpoint {
- remote-endpoint = <&i2s2_endpoint>;
- };
- };
- };
- };
-
- cs42l51: cs42l51@4a {
- compatible = "cirrus,cs42l51";
- reg = <0x4a>;
- #sound-dai-cells = <0>;
- VL-supply = <&v3v3>;
- VD-supply = <&v1v8_audio>;
- VA-supply = <&v1v8_audio>;
- VAHP-supply = <&v1v8_audio>;
- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
- clocks = <&sai2a>;
- clock-names = "MCLK";
- status = "okay";
-
- cs42l51_port: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cs42l51_tx_endpoint: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&sai2a_endpoint>;
- frame-master = <&cs42l51_tx_endpoint>;
- bitclock-master = <&cs42l51_tx_endpoint>;
- };
-
- cs42l51_rx_endpoint: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&sai2b_endpoint>;
- frame-master = <&cs42l51_rx_endpoint>;
- bitclock-master = <&cs42l51_rx_endpoint>;
- };
- };
- };
-};
-
-&i2c4 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_pins_a>;
- pinctrl-1 = <&i2c4_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- stusb1600@28 {
- compatible = "st,stusb1600";
- reg = <0x28>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpioi>;
- pinctrl-names = "default";
- pinctrl-0 = <&stusb1600_pins_a>;
- status = "okay";
- vdd-supply = <&vin>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- typec-power-opmode = "default";
-
- port {
- con_usbotg_hs_ep: endpoint {
- remote-endpoint = <&usbotg_hs_ep>;
- };
- };
- };
- };
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- buck1-supply = <&vin>;
- buck2-supply = <&vin>;
- buck3-supply = <&vin>;
- buck4-supply = <&vin>;
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&vin>;
- ldo3-supply = <&vdd_ddr>;
- ldo4-supply = <&vin>;
- ldo5-supply = <&vin>;
- ldo6-supply = <&v3v3>;
- vref_ddr-supply = <&vin>;
- boost-supply = <&vin>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- v1v8_audio: ldo1 {
- regulator-name = "v1v8_audio";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v3v3_hdmi: ldo2 {
- regulator-name = "v3v3_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdda: ldo5 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v2_hdmi: ldo6 {
- regulator-name = "v1v2_hdmi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&i2c5 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_pins_a>;
- pinctrl-1 = <&i2c5_sleep_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- clock-frequency = <400000>;
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
-};
-
-&i2s2 {
- clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "i2sclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2s2_pins_a>;
- pinctrl-1 = <&i2s2_sleep_pins_a>;
- status = "okay";
-
- i2s2_port: port {
- i2s2_endpoint: endpoint {
- remote-endpoint = <&sii9022_tx_endpoint>;
- dai-format = "i2s";
- mclk-fs = <256>;
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-<dc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-1 = <<dc_sleep_pins_a>;
- status = "okay";
-
- port {
- ltdc_ep0_out: endpoint {
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
- mbox-names = "vq0", "vq1", "shutdown", "detach";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
- status = "okay";
-
- sai2a: audio-controller@4400b004 {
- #clock-cells = <0>;
- dma-names = "tx";
- status = "okay";
-
- sai2a_port: port {
- sai2a_endpoint: endpoint {
- remote-endpoint = <&cs42l51_tx_endpoint>;
- dai-format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-
- sai2b: audio-controller@4400b024 {
- dma-names = "rx";
- st,sync = <&sai2a 2>;
- clocks = <&rcc SAI2_K>, <&sai2a>;
- clock-names = "sai_ck", "MCLK";
- status = "okay";
-
- sai2b_port: port {
- sai2b_endpoint: endpoint {
- remote-endpoint = <&cs42l51_rx_endpoint>;
- dai-format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- disable-wp;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&sdmmc3 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc3_b4_pins_a>;
- pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "disabled";
-};
-
-&timers1 {
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm1_pins_a>;
- pinctrl-1 = <&pwm1_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@0 {
- status = "okay";
- };
-};
-
-&timers3 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm3_pins_a>;
- pinctrl-1 = <&pwm3_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@2 {
- status = "okay";
- };
-};
-
-&timers4 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
- pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@3 {
- status = "okay";
- };
-};
-
-&timers5 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm5_pins_a>;
- pinctrl-1 = <&pwm5_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@4 {
- status = "okay";
- };
-};
-
-&timers6 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- timer@5 {
- status = "okay";
- };
-};
-
-&timers12 {
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
- pwm {
- pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-1 = <&pwm12_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- status = "okay";
- };
- timer@11 {
- status = "okay";
- };
-};
-
-&uart4 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart4_pins_a>;
- pinctrl-1 = <&uart4_sleep_pins_a>;
- pinctrl-2 = <&uart4_idle_pins_a>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
-};
-
-&uart7 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&uart7_pins_c>;
- pinctrl-1 = <&uart7_sleep_pins_c>;
- pinctrl-2 = <&uart7_idle_pins_c>;
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "disabled";
-};
-
-&usart3 {
- pinctrl-names = "default", "sleep", "idle";
- pinctrl-0 = <&usart3_pins_c>;
- pinctrl-1 = <&usart3_sleep_pins_c>;
- pinctrl-2 = <&usart3_idle_pins_c>;
- uart-has-rtscts;
- status = "disabled";
-};
-
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- /* onboard HUB */
- hub@1 {
- compatible = "usb424,2514";
- reg = <1>;
- vdd-supply = <&v3v3>;
- };
-};
-
-&usbotg_hs {
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- usb-role-switch;
- status = "okay";
-
- port {
- usbotg_hs_ep: endpoint {
- remote-endpoint = <&con_usbotg_hs_ep>;
- };
- };
-};
-
-&usbphyc {
- status = "okay";
-};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
- st,tune-hs-dc-level = <2>;
- st,enable-fs-rftime-tuning;
- st,enable-hs-rftime-reduction;
- st,trim-hs-current = <15>;
- st,trim-hs-impedance = <1>;
- st,tune-squelch-level = <3>;
- st,tune-hs-rx-offset = <2>;
- st,no-lsfs-sc;
-};
-
-&vrefbuf {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- vdda-supply = <&vdd>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
deleted file mode 100644
index 04f7a43..0000000
--- a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AA>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@5000b000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@5000c000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
-
-&pinctrl_z {
- st,package = <STM32MP_PKG_AA>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
-};
diff --git a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
deleted file mode 100644
index 328dad1..0000000
--- a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AB>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
-};
diff --git a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
deleted file mode 100644
index 7eaa245..0000000
--- a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AC>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
-};
-
-&pinctrl_z {
- st,package = <STM32MP_PKG_AC>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
-};
diff --git a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
deleted file mode 100644
index b63e207..0000000
--- a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AD>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
-};
diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi
deleted file mode 100644
index d34a1d5..0000000
--- a/arch/arm/dts/stm32mp25-pinctrl.dtsi
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-&pinctrl {
- usart2_pins_a: usart2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_idle_pins_a: usart2-idle-0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
- bias-disable;
- };
- };
-
- usart2_sleep_pins_a: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi
deleted file mode 100644
index e2d1c88..0000000
--- a/arch/arm/dts/stm32mp251.dtsi
+++ /dev/null
@@ -1,301 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a35";
- device_type = "cpu";
- reg = <0>;
- enable-method = "psci";
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a35-pmu";
- interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
- interrupt-parent = <&intc>;
- };
-
- arm_wdt: watchdog {
- compatible = "arm,smc-wdt";
- arm,smc-id = <0xb200005a>;
- status = "disabled";
- };
-
- clocks {
- ck_flexgen_08: ck-flexgen-08 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- ck_flexgen_51: ck-flexgen-51 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
-
- ck_icn_ls_mcu: ck-icn-ls-mcu {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- };
- };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- scmi {
- compatible = "linaro,scmi-optee";
- #address-cells = <1>;
- #size-cells = <0>;
- linaro,optee-channel-id = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
- };
- };
-
- intc: interrupt-controller@4ac00000 {
- compatible = "arm,cortex-a7-gic";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- interrupt-controller;
- reg = <0x0 0x4ac10000 0x0 0x1000>,
- <0x0 0x4ac20000 0x0 0x2000>,
- <0x0 0x4ac40000 0x0 0x2000>,
- <0x0 0x4ac60000 0x0 0x2000>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- always-on;
- };
-
- soc@0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges = <0x0 0x0 0x0 0x80000000>;
-
- rifsc: rifsc-bus@42080000 {
- compatible = "simple-bus";
- reg = <0x42080000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usart2: serial@400e0000 {
- compatible = "st,stm32h7-uart";
- reg = <0x400e0000 0x400>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ck_flexgen_08>;
- status = "disabled";
- };
- };
-
- bsec: efuse@44000000 {
- compatible = "st,stm32mp25-bsec";
- reg = <0x44000000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- part_number_otp@24 {
- reg = <0x24 0x4>;
- };
-
- package_otp@1e8 {
- reg = <0x1e8 0x1>;
- bits = <0 3>;
- };
- };
-
- syscfg: syscon@44230000 {
- compatible = "st,stm32mp25-syscfg", "syscon";
- reg = <0x44230000 0x10000>;
- };
-
- pinctrl: pinctrl@44240000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp257-pinctrl";
- ranges = <0 0x44240000 0xa0400>;
- pins-are-numbered;
-
- gpioa: gpio@44240000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOA";
- status = "disabled";
- };
-
- gpiob: gpio@44250000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x10000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOB";
- status = "disabled";
- };
-
- gpioc: gpio@44260000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x20000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOC";
- status = "disabled";
- };
-
- gpiod: gpio@44270000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x30000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOD";
- status = "disabled";
- };
-
- gpioe: gpio@44280000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x40000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOE";
- status = "disabled";
- };
-
- gpiof: gpio@44290000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x50000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOF";
- status = "disabled";
- };
-
- gpiog: gpio@442a0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x60000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOG";
- status = "disabled";
- };
-
- gpioh: gpio@442b0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x70000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOH";
- status = "disabled";
- };
-
- gpioi: gpio@442c0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x80000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOI";
- status = "disabled";
- };
-
- gpioj: gpio@442d0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x90000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOJ";
- status = "disabled";
- };
-
- gpiok: gpio@442e0000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xa0000 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOK";
- status = "disabled";
- };
- };
-
- pinctrl_z: pinctrl@46200000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp257-z-pinctrl";
- ranges = <0 0x46200000 0x400>;
- pins-are-numbered;
-
- gpioz: gpio@46200000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x400>;
- clocks = <&ck_icn_ls_mcu>;
- st,bank-name = "GPIOZ";
- st,bank-ioport = <11>;
- status = "disabled";
- };
-
- };
- };
-};
diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi
deleted file mode 100644
index af48e82..0000000
--- a/arch/arm/dts/stm32mp253.dtsi
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include "stm32mp251.dtsi"
-
-/ {
- cpus {
- cpu1: cpu@1 {
- compatible = "arm,cortex-a35";
- device_type = "cpu";
- reg = <1>;
- enable-method = "psci";
- };
- };
-
- arm-pmu {
- interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-};
diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi
deleted file mode 100644
index e6fa596..0000000
--- a/arch/arm/dts/stm32mp255.dtsi
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include "stm32mp253.dtsi"
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi
deleted file mode 100644
index 5c5000d..0000000
--- a/arch/arm/dts/stm32mp257.dtsi
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-#include "stm32mp255.dtsi"
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
index a35a9b9..d778b8d 100644
--- a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
@@ -5,8 +5,89 @@
#include "stm32mp25-u-boot.dtsi"
+/ {
+ config {
+ u-boot,boot-led = "led-blue";
+ u-boot,mmc-env-partition = "u-boot-env";
+ };
+
+ clocks {
+ ck_flexgen_08: ck-flexgen-08 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ ck_flexgen_51: ck-flexgen-51 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+
+ ck_icn_ls_mcu: ck-icn-ls-mcu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+};
+
+&gpioa {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiob {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioc {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiod {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioe {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiof {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiog {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioh {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioi {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioj {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpiok {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&gpioz {
+ clocks = <&ck_icn_ls_mcu>;
+};
+
+&sdmmc1 {
+ clocks = <&ck_flexgen_51>;
+ /delete-property/resets;
+};
+
&usart2 {
bootph-all;
+ clocks = <&ck_flexgen_08>;
};
&usart2_pins_a {
diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts
deleted file mode 100644
index a88494e..0000000
--- a/arch/arm/dts/stm32mp257f-ev1.dts
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/dts-v1/;
-
-#include "stm32mp257.dtsi"
-#include "stm32mp25xf.dtsi"
-#include "stm32mp25-pinctrl.dtsi"
-#include "stm32mp25xxai-pinctrl.dtsi"
-
-/ {
- model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
- compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
-
- aliases {
- serial0 = &usart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x1 0x0>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- fw@80000000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x80000000 0x0 0x4000000>;
- no-map;
- };
- };
-};
-
-&arm_wdt {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&usart2 {
- pinctrl-names = "default", "idle", "sleep";
- pinctrl-0 = <&usart2_pins_a>;
- pinctrl-1 = <&usart2_idle_pins_a>;
- pinctrl-2 = <&usart2_sleep_pins_a>;
- status = "okay";
-};
diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi
deleted file mode 100644
index 5e83a69..0000000
--- a/arch/arm/dts/stm32mp25xc.dtsi
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi
deleted file mode 100644
index 5e83a69..0000000
--- a/arch/arm/dts/stm32mp25xf.dtsi
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
-};
diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
deleted file mode 100644
index abdbc7a..0000000
--- a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AI>;
-
- gpioa: gpio@44240000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@44250000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@44260000 {
- status = "okay";
- ngpios = <14>;
- gpio-ranges = <&pinctrl 0 32 14>;
- };
-
- gpiod: gpio@44270000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@44280000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@44290000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@442a0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@442b0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 2 114 12>;
- };
-
- gpioi: gpio@442c0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@442d0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@442e0000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
-};
-
-&pinctrl_z {
- gpioz: gpio@46200000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl_z 0 400 10>;
- };
-};
diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
deleted file mode 100644
index 2e0d4d3..0000000
--- a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AK>;
-
- gpioa: gpio@44240000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@44250000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@44260000 {
- status = "okay";
- ngpios = <14>;
- gpio-ranges = <&pinctrl 0 32 14>;
- };
-
- gpiod: gpio@44270000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@44280000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@44290000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@442a0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@442b0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 2 114 12>;
- };
-
- gpioi: gpio@442c0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
-};
-
-&pinctrl_z {
- gpioz: gpio@46200000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl_z 0 400 10>;
- };
-};
diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
deleted file mode 100644
index 2406e97..0000000
--- a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AL>;
-
- gpioa: gpio@44240000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@44250000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@44260000 {
- status = "okay";
- ngpios = <14>;
- gpio-ranges = <&pinctrl 0 32 14>;
- };
-
- gpiod: gpio@44270000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@44280000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@44290000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@442a0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@442b0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 2 114 12>;
- };
-
- gpioi: gpio@442c0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
-};
-
-&pinctrl_z {
- gpioz: gpio@46200000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl_z 0 400 10>;
- };
-};
diff --git a/arch/arm/include/asm/arch-apple/rtkit.h b/arch/arm/include/asm/arch-apple/rtkit.h
index eff18dd..4b11e2a 100644
--- a/arch/arm/include/asm/arch-apple/rtkit.h
+++ b/arch/arm/include/asm/arch-apple/rtkit.h
@@ -12,6 +12,7 @@
u64 dva;
size_t size;
bool is_mapped;
+ int endpoint;
};
typedef int (*apple_rtkit_shmem_setup)(void *cookie,
@@ -26,4 +27,8 @@
apple_rtkit_shmem_destroy shmem_destroy);
void apple_rtkit_free(struct apple_rtkit *rtk);
int apple_rtkit_boot(struct apple_rtkit *rtk);
+int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate);
+int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout);
int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate);
+
+int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout);
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 0d7a573..1f669c7 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -76,6 +76,8 @@
#define MXC_CPU_IMX9111 0xCD /* dummy ID */
#define MXC_CPU_IMX9101 0xCE /* dummy ID */
+#define MXC_CPU_IMX95 0x1C1 /* dummy ID */
+
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define MXC_SOC_IMX8M 0x80
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index 60d48b1..ffaf6b5 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -255,5 +255,15 @@
void enable_usboh3_clk(unsigned char enable);
int set_clk_enet(enum enet_freq type);
int set_clk_eqos(enum enet_freq type);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
void set_arm_clk(ulong freq);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index ef9538b..5127fe8 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -13,6 +13,7 @@
#define CCM_BASE_ADDR 0x44450000UL
#define CCM_CCGR_BASE_ADDR 0x44458000UL
#define SYSCNT_CTRL_BASE_ADDR 0x44290000
+#define SYSCNT_CMP_BASE_ADDR (SYSCNT_CTRL_BASE_ADDR + 0x10000)
#define ANATOP_BASE_ADDR 0x44480000UL
@@ -20,6 +21,11 @@
#define WDG4_BASE_ADDR 0x424a0000UL
#define WDG5_BASE_ADDR 0x424b0000UL
+#define GPIO2_BASE_ADDR 0x43810000UL
+#define GPIO3_BASE_ADDR 0x43820000UL
+#define GPIO4_BASE_ADDR 0x43840000UL
+#define GPIO5_BASE_ADDR 0x43850000UL
+
#define FSB_BASE_ADDR 0x47510000UL
#define ANATOP_BASE_ADDR 0x44480000UL
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index e4bf6a6..df2148a 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -12,6 +12,7 @@
VOLT_LOW_DRIVE = 0,
VOLT_NOMINAL_DRIVE,
VOLT_OVER_DRIVE,
+ VOLT_SUPER_OVER_DRIVE,
};
void soc_power_init(void);
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 24c8139..d79aea9 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -26,11 +26,21 @@
.word 0xe580e004 // str lr, [r0, #4]
.word 0xe10fe000 // mrs lr, CPSR
.word 0xe580e008 // str lr, [r0, #8]
+ .word 0xe101e300 // mrs lr, SP_irq
+ .word 0xe580e014 // str lr, [r0, #20]
.word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0}
.word 0xe580e00c // str lr, [r0, #12]
.word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0}
.word 0xe580e010 // str lr, [r0, #16]
-
+#ifdef CONFIG_MACH_SUN55I_A523
+ .word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5}
+ .word 0xe31e0001 // tst lr, #1
+ .word 0x0a000003 // beq cc <start32+0x48>
+ .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0}
+ .word 0xe580e018 // str lr, [r0, #24]
+ .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7}
+ .word 0xe580e01c // str lr, [r0, #28]
+#endif
.word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS
.word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE
.word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 2cec91c..00bdd5f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -10,6 +10,12 @@
#ifndef _SUNXI_CLOCK_SUN4I_H
#define _SUNXI_CLOCK_SUN4I_H
+#define CCU_AHB_GATE0 0x60
+#define CCU_MMC0_CLK_CFG 0x88
+#define CCU_MMC1_CLK_CFG 0x8c
+#define CCU_MMC2_CLK_CFG 0x90
+#define CCU_MMC3_CLK_CFG 0x94
+
struct sunxi_ccm_reg {
u32 pll1_cfg; /* 0x00 pll1 control */
u32 pll1_tun; /* 0x04 pll1 tuning */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 76dd33c..ccacc99 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -13,218 +13,23 @@
#include <linux/bitops.h>
#endif
-struct sunxi_ccm_reg {
- u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
- u8 reserved_0x004[12];
- u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
- u8 reserved_0x014[12];
- u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
- u8 reserved_0x020[4];
- u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
- u8 reserved_0x028[4];
- u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
- u8 reserved_0x034[12];
- u32 pll3_cfg; /* 0x040 pll3 (video0) control */
- u8 reserved_0x044[4];
- u32 pll_video1_cfg; /* 0x048 pll video1 control */
- u8 reserved_0x04c[12];
- u32 pll4_cfg; /* 0x058 pll4 (ve) control */
- u8 reserved_0x05c[4];
- u32 pll10_cfg; /* 0x060 pll10 (de) control */
- u8 reserved_0x064[12];
- u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
- u8 reserved_0x074[4];
- u32 pll2_cfg; /* 0x078 pll2 (audio) control */
- u8 reserved_0x07c[148];
- u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */
- u8 reserved_0x114[20];
- u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */
- u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */
- u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */
- u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */
- u8 reserved_0x138[8];
- u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */
- u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */
- u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */
- u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */
- u8 reserved_0x150[8];
- u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */
- u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */
- u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */
- u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */
- u8 reserved_0x168[8];
- u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */
- u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */
- u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */
- u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */
- u8 reserved_0x180[384];
- u32 pll1_bias; /* 0x300 pll1 (cpux) bias */
- u8 reserved_0x304[12];
- u32 pll5_bias; /* 0x310 pll5 (ddr) bias */
- u8 reserved_0x314[12];
- u32 pll6_bias; /* 0x320 pll6 (periph0) bias */
- u8 reserved_0x324[4];
- u32 pll_periph1_bias; /* 0x328 pll periph1 bias */
- u8 reserved_0x32c[4];
- u32 pll7_bias; /* 0x330 pll7 (gpu) bias */
- u8 reserved_0x334[12];
- u32 pll3_bias; /* 0x340 pll3 (video0) bias */
- u8 reserved_0x344[4];
- u32 pll_video1_bias; /* 0x348 pll video1 bias */
- u8 reserved_0x34c[12];
- u32 pll4_bias; /* 0x358 pll4 (ve) bias */
- u8 reserved_0x35c[4];
- u32 pll10_bias; /* 0x360 pll10 (de) bias */
- u8 reserved_0x364[12];
- u32 pll9_bias; /* 0x370 pll9 (hsic) bias */
- u8 reserved_0x374[4];
- u32 pll2_bias; /* 0x378 pll2 (audio) bias */
- u8 reserved_0x37c[132];
- u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */
- u8 reserved_0x404[252];
- u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/
- u8 reserved_0x504[12];
- u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */
- u8 reserved_0x514[8];
- u32 ahb3_cfg; /* 0x51c AHB3 clock control */
- u32 apb1_cfg; /* 0x520 APB1 clock control */
- u32 apb2_cfg; /* 0x524 APB2 clock control */
- u8 reserved_0x528[24];
- u32 mbus_cfg; /* 0x540 MBUS clock control */
- u8 reserved_0x544[188];
- u32 de_clk_cfg; /* 0x600 DE clock control */
- u8 reserved_0x604[8];
- u32 de_gate_reset; /* 0x60c DE gate/reset control */
- u8 reserved_0x610[16];
- u32 di_clk_cfg; /* 0x620 DI clock control */
- u8 reserved_0x024[8];
- u32 di_gate_reset; /* 0x62c DI gate/reset control */
- u8 reserved_0x630[64];
- u32 gpu_clk_cfg; /* 0x670 GPU clock control */
- u8 reserved_0x674[8];
- u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */
- u32 ce_clk_cfg; /* 0x680 CE clock control */
- u8 reserved_0x684[8];
- u32 ce_gate_reset; /* 0x68c CE gate/reset control */
- u32 ve_clk_cfg; /* 0x690 VE clock control */
- u8 reserved_0x694[8];
- u32 ve_gate_reset; /* 0x69c VE gate/reset control */
- u8 reserved_0x6a0[16];
- u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */
- u8 reserved_0x6b4[8];
- u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */
- u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */
- u8 reserved_0x6c4[8];
- u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */
- u8 reserved_0x6d0[60];
- u32 dma_gate_reset; /* 0x70c DMA gate/reset control */
- u8 reserved_0x710[12];
- u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */
- u8 reserved_0x720[12];
- u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
- u8 reserved_0x730[12];
- u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */
- u32 avs_gate_reset; /* 0x740 AVS gate/reset control */
- u8 reserved_0x744[72];
- u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */
- u8 reserved_0x790[12];
- u32 psi_gate_reset; /* 0x79c PSI gate/reset control */
- u8 reserved_0x7a0[12];
- u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */
- u8 reserved_0x7b0[12];
- u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */
- u8 reserved_0x7c0[64];
- u32 dram_clk_cfg; /* 0x800 DRAM clock control */
- u32 mbus_gate; /* 0x804 MBUS gate control */
- u8 reserved_0x808[4];
- u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */
- u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */
- u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */
- u8 reserved_0x818[20];
- u32 nand_gate_reset; /* 0x82c NAND gate/reset control */
- u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */
- u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */
- u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */
- u8 reserved_0x83c[16];
- u32 sd_gate_reset; /* 0x84c MMC gate/reset control */
- u8 reserved_0x850[188];
- u32 uart_gate_reset; /* 0x90c UART gate/reset control */
- u8 reserved_0x910[12];
- u32 twi_gate_reset; /* 0x91c I2C gate/reset control */
- u8 reserved_0x920[28];
- u32 scr_gate_reset; /* 0x93c SCR gate/reset control */
- u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */
- u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */
- u8 reserved_0x948[36];
- u32 spi_gate_reset; /* 0x96c SPI gate/reset control */
- u8 reserved_0x970[12];
- u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */
- u8 reserved_0x980[48];
- u32 ts_clk_cfg; /* 0x9b0 TS clock control */
- u8 reserved_0x9b4[8];
- u32 ts_gate_reset; /* 0x9bc TS gate/reset control */
- u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */
- u8 reserved_0x9c4[8];
- u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */
- u8 reserved_0x9d0[44];
- u32 ths_gate_reset; /* 0x9fc THS gate/reset control */
- u8 reserved_0xa00[12];
- u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */
- u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */
- u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */
- u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */
- u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */
- u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */
- u8 reserved_0xa24[8];
- u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */
- u8 reserved_0xa30[16];
- u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */
- u8 reserved_0xa44[8];
- u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */
- u8 reserved_0xa50[16];
- u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */
- u8 reserved_0xa64[8];
- u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */
- u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */
- u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */
- u8 reserved_0xa78[4];
- u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */
- u8 reserved_0xa80[12];
- u32 usb_gate_reset; /* 0xa8c USB gate/reset control */
- u8 reserved_0xa90[32];
- u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */
- u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */
- u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */
- u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */
- u8 reserved_0xac0[64];
- u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */
- u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */
- u8 reserved_0xb08[8];
- u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */
- u8 reserved_0xb14[8];
- u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */
- u8 reserved_0xb20[60];
- u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
- u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */
- u8 reserved_0xb64[24];
- u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
- u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */
- u8 reserved_0xb84[24];
- u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */
- u8 reserved_0xba0[96];
- u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */
- u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */
- u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */
- u8 reserved_0xc0c[32];
- u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */
- u8 reserved_0xc30[16];
- u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */
- u8 reserved_0xc44[8];
- u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */
- u8 reserved_0xc50[688];
- u32 ccu_sec_switch; /* 0xf00 CCU security switch */
- u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */
-};
+#define CCU_H6_PLL1_CFG 0x000
+#define CCU_H6_PLL5_CFG 0x010
+#define CCU_H6_PLL6_CFG 0x020
+#define CCU_H6_CPU_AXI_CFG 0x500
+#define CCU_H6_PSI_AHB1_AHB2_CFG 0x510
+#define CCU_H6_AHB3_CFG 0x51c
+#define CCU_H6_APB1_CFG 0x520
+#define CCU_H6_APB2_CFG 0x524
+#define CCU_H6_MBUS_CFG 0x540
+#define CCU_H6_DRAM_CLK_CFG 0x800
+#define CCU_H6_DRAM_GATE_RESET 0x80c
+#define CCU_MMC0_CLK_CFG 0x830
+#define CCU_MMC1_CLK_CFG 0x834
+#define CCU_MMC2_CLK_CFG 0x838
+#define CCU_H6_MMC_GATE_RESET 0x84c
+#define CCU_H6_UART_GATE_RESET 0x90c
+#define CCU_H6_I2C_GATE_RESET 0x91c
/* pll1 bit field */
#define CCM_PLL1_CTRL_EN BIT(31)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 7fcf340..28c3fac 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -10,6 +10,13 @@
#ifndef _SUNXI_CLOCK_SUN6I_H
#define _SUNXI_CLOCK_SUN6I_H
+#define CCU_AHB_GATE0 0x060
+#define CCU_MMC0_CLK_CFG 0x088
+#define CCU_MMC1_CLK_CFG 0x08c
+#define CCU_MMC2_CLK_CFG 0x090
+#define CCU_MMC3_CLK_CFG 0x094
+#define CCU_AHB_RESET0_CFG 0x2c0
+
struct sunxi_ccm_reg {
u32 pll1_cfg; /* 0x00 pll1 control */
u32 reserved0;
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 35ca049..5ad2163 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -13,6 +13,13 @@
#ifndef _SUNXI_CLOCK_SUN8I_A83T_H
#define _SUNXI_CLOCK_SUN8I_A83T_H
+#define CCU_AHB_GATE0 0x060
+#define CCU_MMC0_CLK_CFG 0x088
+#define CCU_MMC1_CLK_CFG 0x08c
+#define CCU_MMC2_CLK_CFG 0x090
+#define CCU_MMC3_CLK_CFG 0x094
+#define CCU_AHB_RESET0_CFG 0x2c0
+
struct sunxi_ccm_reg {
u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */
u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index 006f776..8d696e5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -12,6 +12,13 @@
#include <linux/bitops.h>
#endif
+#define CCU_MMC0_CLK_CFG 0x410
+#define CCU_MMC1_CLK_CFG 0x414
+#define CCU_MMC2_CLK_CFG 0x418
+#define CCU_MMC3_CLK_CFG 0x41c
+#define CCU_AHB_GATE0 0x580
+#define CCU_AHB_RESET0_CFG 0x5a0
+
struct sunxi_ccm_reg {
u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h
new file mode 100644
index 0000000..bc9e0d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Helpers that are commonly used with DW memory controller.
+ *
+ * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com>
+ *
+ */
+
+#ifndef _DRAM_DW_HELPERS_H
+#define _DRAM_DW_HELPERS_H
+
+#include <asm/arch/dram.h>
+
+bool mctl_core_init(const struct dram_para *para,
+ const struct dram_config *config);
+void mctl_auto_detect_rank_width(const struct dram_para *para,
+ struct dram_config *config);
+void mctl_auto_detect_dram_size(const struct dram_para *para,
+ struct dram_config *config);
+unsigned long mctl_calc_size(const struct dram_config *config);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index f0caecc..af6cd33 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -315,12 +315,15 @@
struct dram_para {
u32 clk;
enum sunxi_dram_type type;
+ const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
+ const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
+};
+
+struct dram_config {
u8 cols;
u8 rows;
u8 ranks;
u8 bus_full_width;
- const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
- const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
static inline int ns_to_t(int nanoseconds)
@@ -330,6 +333,6 @@
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}
-void mctl_set_timing_params(struct dram_para *para);
+void mctl_set_timing_params(void);
#endif /* _SUNXI_DRAM_SUN50I_H6_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
index fd63d3a..d6653c3 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
@@ -9,46 +9,12 @@
#define _SUN50I_PRCM_H
#ifndef __ASSEMBLY__
-#include <linux/compiler.h>
-struct sunxi_prcm_reg {
- u32 cpus_cfg; /* 0x000 */
- u8 res0[0x8]; /* 0x004 */
- u32 apbs1_cfg; /* 0x00c */
- u32 apbs2_cfg; /* 0x010 */
- u8 res1[0x108]; /* 0x014 */
- u32 tmr_gate_reset; /* 0x11c */
- u8 res2[0xc]; /* 0x120 */
- u32 twd_gate_reset; /* 0x12c */
- u8 res3[0xc]; /* 0x130 */
- u32 pwm_gate_reset; /* 0x13c */
- u8 res4[0x4c]; /* 0x140 */
- u32 uart_gate_reset; /* 0x18c */
- u8 res5[0xc]; /* 0x190 */
- u32 twi_gate_reset; /* 0x19c */
- u8 res6[0x1c]; /* 0x1a0 */
- u32 rsb_gate_reset; /* 0x1bc */
- u32 cir_cfg; /* 0x1c0 */
- u8 res7[0x8]; /* 0x1c4 */
- u32 cir_gate_reset; /* 0x1cc */
- u8 res8[0x10]; /* 0x1d0 */
- u32 w1_cfg; /* 0x1e0 */
- u8 res9[0x8]; /* 0x1e4 */
- u32 w1_gate_reset; /* 0x1ec */
- u8 res10[0x1c]; /* 0x1f0 */
- u32 rtc_gate_reset; /* 0x20c */
- u8 res11[0x34]; /* 0x210 */
- u32 pll_ldo_cfg; /* 0x244 */
- u8 res12[0x8]; /* 0x248 */
- u32 sys_pwroff_gating; /* 0x250 */
- u8 res13[0xbc]; /* 0x254 */
- u32 res_cal_ctrl; /* 0x310 */
- u32 ohms200; /* 0x314 */
- u32 ohms240; /* 0x318 */
- u32 res_cal_status; /* 0x31c */
-};
-check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
-check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
+#define CCU_PRCM_I2C_GATE_RESET 0x19c
+#define CCU_PRCM_PLL_LDO_CFG 0x244
+#define CCU_PRCM_SYS_PWROFF_GATING 0x250
+#define CCU_PRCM_RES_CAL_CTRL 0x310
+#define CCU_PRCM_OHMS240 0x318
#define PRCM_TWI_GATE (1 << 0)
#define PRCM_TWI_RESET (1 << 16)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 109a806..0780f99 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -97,6 +97,8 @@
#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
+#define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
+
#define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
#define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
#define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101))
@@ -216,6 +218,43 @@
u32 rom_api_download_image(u8 *dest, u32 offset, u32 size);
u32 rom_api_query_boot_infor(u32 info_type, u32 *info);
+#if IS_ENABLED(CONFIG_SCMI_FIRMWARE)
+typedef struct rom_passover {
+ u16 tag; // Tag
+ u8 len; // Fixed value of 0x80
+ u8 ver; // Version
+ u32 boot_mode; // Boot mode
+ u32 card_addr_mode; // SD card address mode
+ u32 bad_blks_of_img_set0; // NAND bad block count skipped 1
+ u32 ap_mu_id; // AP MU ID
+ u32 bad_blks_of_img_set1; // NAND bad block count skipped 1
+ u8 boot_stage; // Boot stage
+ u8 img_set_sel; // Image set booted from
+ u8 rsv0[2]; // Reserved
+ u32 img_set_end; // Offset of Image End
+ u32 rom_version; // ROM version
+ u8 boot_dev_state; // Boot device state
+ u8 boot_dev_inst; // Boot device type
+ u8 boot_dev_type; // Boot device instance
+ u8 rsv1; // Reserved
+ u32 dev_page_size; // Boot device page size
+ u32 cnt_header_ofs; // Container header offset
+ u32 img_ofs; // Image offset
+} __packed rom_passover_t;
+
+/**
+ * struct scmi_rom_passover_out - Response payload for ROM_PASSOVER_GET command
+ * @status: SCMI clock ID
+ * @attributes: Attributes of the targets clock state
+ */
+struct scmi_rom_passover_get_out {
+ u32 status;
+ u32 numPassover;
+ u32 passover[(sizeof(rom_passover_t) + 8) / 4];
+};
+
+#endif
+
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
#define BT0CFG_DUALBOOT_MASK 0x2
diff --git a/arch/arm/mach-apple/Makefile b/arch/arm/mach-apple/Makefile
index 50b465b..d79a3a6 100644
--- a/arch/arm/mach-apple/Makefile
+++ b/arch/arm/mach-apple/Makefile
@@ -3,4 +3,5 @@
obj-y += board.o
obj-y += lowlevel_init.o
obj-y += rtkit.o
+obj-$(CONFIG_APPLE_MTP_KEYB) += rtkit_helper.o
obj-$(CONFIG_NVME_APPLE) += sart.o
diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c
index b8f4771..f356154 100644
--- a/arch/arm/mach-apple/rtkit.c
+++ b/arch/arm/mach-apple/rtkit.c
@@ -11,6 +11,7 @@
#include <linux/apple-mailbox.h>
#include <linux/bitfield.h>
#include <linux/errno.h>
+#include <linux/sizes.h>
#include <linux/types.h>
#define APPLE_RTKIT_EP_MGMT 0
@@ -18,6 +19,7 @@
#define APPLE_RTKIT_EP_SYSLOG 2
#define APPLE_RTKIT_EP_DEBUG 3
#define APPLE_RTKIT_EP_IOREPORT 4
+#define APPLE_RTKIT_EP_OSLOG 8
#define APPLE_RTKIT_EP_TRACEKIT 10
/* Messages for management endpoint. */
@@ -36,6 +38,7 @@
#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE 6
#define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK 7
+#define APPLE_RTKIT_MGMT_SET_AP_PWR_STATE 11
#define APPLE_RTKIT_MGMT_EPMAP 8
#define APPLE_RTKIT_MGMT_EPMAP_LAST BIT(51)
@@ -45,6 +48,11 @@
#define APPLE_RTKIT_MGMT_EPMAP_REPLY 8
#define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT(0)
+#define APPLE_RTKIT_OSLOG_TYPE GENMASK_ULL(63, 56)
+#define APPLE_RTKIT_OSLOG_BUFFER_REQUEST 1
+#define APPLE_RTKIT_OSLOG_SIZE GENMASK_ULL(55, 36)
+#define APPLE_RTKIT_OSLOG_IOVA GENMASK_ULL(35, 0)
+
#define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11
#define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12
@@ -64,6 +72,10 @@
struct apple_rtkit_buffer syslog_buffer;
struct apple_rtkit_buffer crashlog_buffer;
struct apple_rtkit_buffer ioreport_buffer;
+ struct apple_rtkit_buffer oslog_buffer;
+
+ int iop_pwr;
+ int ap_pwr;
};
struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie,
@@ -93,6 +105,17 @@
rtk->shmem_destroy(rtk->cookie, &rtk->crashlog_buffer);
if (rtk->ioreport_buffer.buffer)
rtk->shmem_destroy(rtk->cookie, &rtk->ioreport_buffer);
+ if (rtk->oslog_buffer.buffer)
+ rtk->shmem_destroy(rtk->cookie, &rtk->oslog_buffer);
+ } else {
+ if (rtk->syslog_buffer.buffer)
+ free(rtk->syslog_buffer.buffer);
+ if (rtk->crashlog_buffer.buffer)
+ free(rtk->crashlog_buffer.buffer);
+ if (rtk->ioreport_buffer.buffer)
+ free(rtk->ioreport_buffer.buffer);
+ if (rtk->oslog_buffer.buffer)
+ free(rtk->oslog_buffer.buffer);
}
free(rtk);
}
@@ -100,16 +123,8 @@
static int rtkit_handle_buf_req(struct apple_rtkit *rtk, int endpoint, struct apple_mbox_msg *msg)
{
struct apple_rtkit_buffer *buf;
- size_t num_4kpages;
int ret;
- num_4kpages = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg->msg0);
-
- if (num_4kpages == 0) {
- printf("%s: unexpected request for buffer without size\n", __func__);
- return -1;
- }
-
switch (endpoint) {
case APPLE_RTKIT_EP_CRASHLOG:
buf = &rtk->crashlog_buffer;
@@ -120,14 +135,33 @@
case APPLE_RTKIT_EP_IOREPORT:
buf = &rtk->ioreport_buffer;
break;
+ case APPLE_RTKIT_EP_OSLOG:
+ buf = &rtk->oslog_buffer;
+ break;
default:
printf("%s: unexpected endpoint %d\n", __func__, endpoint);
return -1;
}
+ switch (endpoint) {
+ case APPLE_RTKIT_EP_OSLOG:
+ buf->size = FIELD_GET(APPLE_RTKIT_OSLOG_SIZE, msg->msg0);
+ buf->dva = FIELD_GET(APPLE_RTKIT_OSLOG_IOVA, msg->msg0 << 12);
+ break;
+ default:
+ buf->size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg->msg0) << 12;
+ buf->dva = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg->msg0);
+ break;
+ }
+
+ if (buf->size == 0) {
+ printf("%s: unexpected request for buffer without size\n", __func__);
+ return -1;
+ }
+
buf->dva = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg->msg0);
- buf->size = num_4kpages << 12;
- buf->is_mapped = false;
+ buf->is_mapped = !!buf->dva;
+ buf->endpoint = endpoint;
if (rtk->shmem_setup) {
ret = rtk->shmem_setup(rtk->cookie, buf);
@@ -136,13 +170,27 @@
endpoint);
return ret;
}
+ } else if (!buf->is_mapped){
+ buf->buffer = memalign(SZ_16K, ALIGN(buf->size, SZ_16K));
+ if (!buf->buffer)
+ return -ENOMEM;
+
+ buf->dva = (u64)buf->buffer;
}
if (!buf->is_mapped) {
- msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) |
- FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, num_4kpages) |
- FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva);
- msg->msg1 = endpoint;
+ /* oslog uses different fields */
+ if (endpoint == APPLE_RTKIT_EP_OSLOG) {
+ msg->msg0 = FIELD_PREP(APPLE_RTKIT_OSLOG_TYPE,
+ APPLE_RTKIT_OSLOG_BUFFER_REQUEST);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_OSLOG_SIZE, buf->size);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_OSLOG_IOVA, buf->dva >> 12);
+ } else {
+ msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE,
+ APPLE_RTKIT_BUFFER_REQUEST);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, buf->size >> 12);
+ msg->msg0 |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva);
+ }
return mbox_send(rtk->chan, msg);
}
@@ -150,6 +198,89 @@
return 0;
}
+int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout)
+{
+ struct apple_mbox_msg msg;
+ int ret;
+ int endpoint;
+ int msgtype;
+
+ ret = mbox_recv(rtk->chan, &msg, timeout);
+ if (ret < 0)
+ return ret;
+
+ endpoint = msg.msg1;
+ msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
+
+ if (endpoint == APPLE_RTKIT_EP_CRASHLOG ||
+ endpoint == APPLE_RTKIT_EP_SYSLOG ||
+ endpoint == APPLE_RTKIT_EP_IOREPORT) {
+ if (msgtype == APPLE_RTKIT_BUFFER_REQUEST) {
+ ret = rtkit_handle_buf_req(rtk, endpoint, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ }
+ }
+
+ if (endpoint == APPLE_RTKIT_EP_OSLOG) {
+ msgtype = FIELD_GET(APPLE_RTKIT_OSLOG_TYPE, msg.msg0);
+
+ if (msgtype == APPLE_RTKIT_OSLOG_BUFFER_REQUEST) {
+ ret = rtkit_handle_buf_req(rtk, endpoint, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ } else {
+ /* Ignore */
+ return 0;
+ }
+ }
+
+ if (endpoint == APPLE_RTKIT_EP_IOREPORT) {
+ // these two messages have to be ack-ed for proper startup
+ if (msgtype == 0xc || msgtype == 0x8) {
+ ret = mbox_send(rtk->chan, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ }
+ }
+
+ if (endpoint == APPLE_RTKIT_EP_SYSLOG) {
+ /* Ignore init */
+ if (msgtype == 0x8)
+ return 0;
+
+ /* Ack logs */
+ if (msgtype == 0x5) {
+ ret = mbox_send(rtk->chan, &msg);
+ if (ret < 0)
+ return ret;
+ return 0;
+ }
+ }
+
+ if (endpoint != APPLE_RTKIT_EP_MGMT) {
+ printf("%s: unexpected endpoint %d\n", __func__, endpoint);
+ return -EINVAL;
+ }
+
+ switch (msgtype) {
+ case APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK:
+ rtk->iop_pwr = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
+ return 0;
+ case APPLE_RTKIT_MGMT_SET_AP_PWR_STATE:
+ rtk->ap_pwr = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
+ return 0;
+ default:
+ printf("%s: unexpected message type %d\n", __func__, msgtype);
+
+ /* Just ignore it */
+ return 0;
+ }
+}
+
int apple_rtkit_boot(struct apple_rtkit *rtk)
{
struct apple_mbox_msg msg;
@@ -157,7 +288,7 @@
int nendpoints = 0;
int endpoint;
int min_ver, max_ver, want_ver;
- int msgtype, pwrstate;
+ int msgtype;
u64 reply;
u32 bitmap, base;
int i, ret;
@@ -276,46 +407,37 @@
return ret;
}
- pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP;
- while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) {
- ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
+ rtk->iop_pwr = APPLE_RTKIT_PWR_STATE_SLEEP;
+ rtk->ap_pwr = APPLE_RTKIT_PWR_STATE_QUIESCED;
+
+ while (rtk->iop_pwr != APPLE_RTKIT_PWR_STATE_ON) {
+ ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US);
if (ret < 0)
return ret;
+ }
- endpoint = msg.msg1;
- msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0);
+ return 0;
+}
- if (endpoint == APPLE_RTKIT_EP_CRASHLOG ||
- endpoint == APPLE_RTKIT_EP_SYSLOG ||
- endpoint == APPLE_RTKIT_EP_IOREPORT) {
- if (msgtype == APPLE_RTKIT_BUFFER_REQUEST) {
- ret = rtkit_handle_buf_req(rtk, endpoint, &msg);
- if (ret < 0)
- return ret;
- continue;
- }
- }
+int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate)
+{
+ struct apple_mbox_msg msg;
+ int ret;
- if (endpoint == APPLE_RTKIT_EP_IOREPORT) {
- // these two messages have to be ack-ed for proper startup
- if (msgtype == 0xc || msgtype == 0x8) {
- ret = mbox_send(rtk->chan, &msg);
- if (ret < 0)
- return ret;
- continue;
- }
- }
+ if (rtk->ap_pwr == pwrstate)
+ return 0;
- if (endpoint != APPLE_RTKIT_EP_MGMT) {
- printf("%s: unexpected endpoint %d\n", __func__, endpoint);
- return -EINVAL;
- }
- if (msgtype != APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK) {
- printf("%s: unexpected message type %d\n", __func__, msgtype);
- return -EINVAL;
- }
+ msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_AP_PWR_STATE) |
+ FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate);
+ msg.msg1 = APPLE_RTKIT_EP_MGMT;
+ ret = mbox_send(rtk->chan, &msg);
+ if (ret < 0)
+ return ret;
- pwrstate = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0);
+ while (rtk->ap_pwr != pwrstate) {
+ ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US);
+ if (ret < 0)
+ return ret;
}
return 0;
@@ -326,6 +448,12 @@
struct apple_mbox_msg msg;
int ret;
+ if (rtk->ap_pwr != APPLE_RTKIT_PWR_STATE_QUIESCED) {
+ ret = apple_rtkit_set_ap_power(rtk, APPLE_RTKIT_PWR_STATE_QUIESCED);
+ if (ret < 0)
+ return ret;
+ }
+
msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) |
FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate);
msg.msg1 = APPLE_RTKIT_EP_MGMT;
@@ -333,9 +461,11 @@
if (ret < 0)
return ret;
- ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US);
- if (ret < 0)
- return ret;
+ while (rtk->iop_pwr != pwrstate) {
+ ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US);
+ if (ret < 0)
+ return ret;
+ }
return 0;
}
diff --git a/arch/arm/mach-apple/rtkit_helper.c b/arch/arm/mach-apple/rtkit_helper.c
new file mode 100644
index 0000000..b7d60e1
--- /dev/null
+++ b/arch/arm/mach-apple/rtkit_helper.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright The Asahi Linux Contributors
+ */
+
+#include <dm.h>
+#include <mailbox.h>
+#include <mapmem.h>
+#include <reset.h>
+
+#include <asm/io.h>
+#include <asm/arch/rtkit.h>
+#include <linux/iopoll.h>
+
+/* ASC registers */
+#define REG_CPU_CTRL 0x0044
+#define REG_CPU_CTRL_RUN BIT(4)
+
+#define APPLE_RTKIT_EP_OSLOG 8
+
+struct rtkit_helper_priv {
+ void *asc; /* ASC registers */
+ struct mbox_chan chan;
+ struct apple_rtkit *rtk;
+ bool sram_stolen;
+};
+
+static int shmem_setup(void *cookie, struct apple_rtkit_buffer *buf) {
+ struct udevice *dev = cookie;
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+
+ if (!buf->is_mapped) {
+ /*
+ * Special case: The OSLog buffer on MTP persists on Linux handoff.
+ * Steal some SRAM instead of putting this in DRAM, so we don't
+ * have to hand off DART/DAPF mappings.
+ */
+ if (buf->endpoint == APPLE_RTKIT_EP_OSLOG) {
+ if (priv->sram_stolen) {
+ printf("%s: Tried to map more than one OSLog buffer out of SRAM\n",
+ __func__);
+ } else {
+ fdt_size_t size;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_size_name(dev, "sram", &size);
+
+ if (addr != FDT_ADDR_T_NONE) {
+ buf->dva = ALIGN_DOWN(addr + size - buf->size, SZ_16K);
+ priv->sram_stolen = true;
+
+ return 0;
+ } else {
+ printf("%s: No SRAM, falling back to DRAM\n", __func__);
+ }
+ }
+ }
+
+ buf->buffer = memalign(SZ_16K, ALIGN(buf->size, SZ_16K));
+ if (!buf->buffer)
+ return -ENOMEM;
+
+ buf->dva = (u64)buf->buffer;
+ }
+ return 0;
+}
+
+static void shmem_destroy(void *cookie, struct apple_rtkit_buffer *buf) {
+ if (buf->buffer)
+ free(buf->buffer);
+}
+
+static int rtkit_helper_probe(struct udevice *dev)
+{
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+ u32 ctrl;
+ int ret;
+
+ priv->asc = dev_read_addr_ptr(dev);
+ if (!priv->asc)
+ return -EINVAL;
+
+ ret = mbox_get_by_index(dev, 0, &priv->chan);
+ if (ret < 0)
+ return ret;
+
+ ctrl = readl(priv->asc + REG_CPU_CTRL);
+ writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
+
+ priv->rtk = apple_rtkit_init(&priv->chan, dev, shmem_setup, shmem_destroy);
+ if (!priv->rtk)
+ return -ENOMEM;
+
+ ret = apple_rtkit_boot(priv->rtk);
+ if (ret < 0) {
+ printf("%s: Helper apple_rtkit_boot returned: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = apple_rtkit_set_ap_power(priv->rtk, APPLE_RTKIT_PWR_STATE_ON);
+ if (ret < 0) {
+ printf("%s: Helper apple_rtkit_set_ap_power returned: %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rtkit_helper_remove(struct udevice *dev)
+{
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+ u32 ctrl;
+
+ apple_rtkit_shutdown(priv->rtk, APPLE_RTKIT_PWR_STATE_QUIESCED);
+
+ ctrl = readl(priv->asc + REG_CPU_CTRL);
+ writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL);
+
+ apple_rtkit_free(priv->rtk);
+ priv->rtk = NULL;
+
+ return 0;
+}
+
+int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout)
+{
+ struct rtkit_helper_priv *priv = dev_get_priv(dev);
+
+ return apple_rtkit_poll(priv->rtk, timeout);
+}
+
+static const struct udevice_id rtkit_helper_ids[] = {
+ { .compatible = "apple,rtk-helper-asc4" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rtkit_helper) = {
+ .name = "rtkit_helper",
+ .id = UCLASS_MISC,
+ .of_match = rtkit_helper_ids,
+ .priv_auto = sizeof(struct rtkit_helper_priv),
+ .probe = rtkit_helper_probe,
+ .remove = rtkit_helper_remove,
+ .flags = DM_FLAG_OS_PREPARE,
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 134e420..e401422 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -180,7 +180,7 @@
config IMX8_ROMAPI
def_bool y
- depends on IMX8MN || IMX8MP || IMX8ULP || IMX9
+ depends on IMX8MN || IMX8MP || IMX8ULP || IMX91 || IMX93
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 2afe9d3..f84e23f 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -41,6 +41,52 @@
#define FUSE_IMG_SET_OFF_WORD 720
#endif
+#define MAX_V2X_CTNR_IMG_NUM (4)
+#define MIN_V2X_CTNR_IMG_NUM (2)
+
+#define IMG_FLAGS_IMG_TYPE_SHIFT (0u)
+#define IMG_FLAGS_IMG_TYPE_MASK (0xfU)
+#define IMG_FLAGS_IMG_TYPE(x) (((x) & IMG_FLAGS_IMG_TYPE_MASK) >> \
+ IMG_FLAGS_IMG_TYPE_SHIFT)
+
+#define IMG_FLAGS_CORE_ID_SHIFT (4u)
+#define IMG_FLAGS_CORE_ID_MASK (0xf0U)
+#define IMG_FLAGS_CORE_ID(x) (((x) & IMG_FLAGS_CORE_ID_MASK) >> \
+ IMG_FLAGS_CORE_ID_SHIFT)
+
+#define IMG_TYPE_V2X_PRI_FW (0x0Bu) /* Primary V2X FW */
+#define IMG_TYPE_V2X_SND_FW (0x0Cu) /* Secondary V2X FW */
+
+#define CORE_V2X_PRI 9
+#define CORE_V2X_SND 10
+
+static bool is_v2x_fw_container(ulong addr)
+{
+ struct container_hdr *phdr;
+ struct boot_img_t *img_entry;
+
+ phdr = (struct container_hdr *)addr;
+ if (phdr->tag != 0x87 || phdr->version != 0x0) {
+ debug("Wrong container header\n");
+ return false;
+ }
+
+ if (phdr->num_images >= MIN_V2X_CTNR_IMG_NUM && phdr->num_images <= MAX_V2X_CTNR_IMG_NUM) {
+ img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr));
+
+ if (IMG_FLAGS_IMG_TYPE(img_entry->hab_flags) == IMG_TYPE_V2X_PRI_FW &&
+ IMG_FLAGS_CORE_ID(img_entry->hab_flags) == CORE_V2X_PRI) {
+ img_entry++;
+
+ if (IMG_FLAGS_IMG_TYPE(img_entry->hab_flags) == IMG_TYPE_V2X_SND_FW &&
+ IMG_FLAGS_CORE_ID(img_entry->hab_flags) == CORE_V2X_SND)
+ return true;
+ }
+ }
+
+ return false;
+}
+
int get_container_size(ulong addr, u16 *header_length)
{
struct container_hdr *phdr;
@@ -83,7 +129,7 @@
return max_offset;
}
-static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length)
+static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length, bool *v2x_cntr)
{
u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT);
int ret = 0;
@@ -150,6 +196,9 @@
ret = get_container_size((ulong)buf, header_length);
+ if (v2x_cntr)
+ *v2x_cntr = is_v2x_fw_container((ulong)buf);
+
free(buf);
return ret;
@@ -231,45 +280,67 @@
return offset;
}
-static int get_imageset_end(void *dev, int dev_type)
+static ulong get_imageset_end(void *dev, int dev_type)
{
- unsigned long offset1 = 0, offset2 = 0;
- int value_container[2];
+ unsigned long offset[3] = {};
+ int value_container[3] = {};
u16 hdr_length;
+ bool v2x_fw = false;
- offset1 = get_boot_device_offset(dev, dev_type);
- offset2 = CONTAINER_HDR_ALIGNMENT + offset1;
+ offset[0] = get_boot_device_offset(dev, dev_type);
- value_container[0] = get_dev_container_size(dev, dev_type, offset1, &hdr_length);
+ value_container[0] = get_dev_container_size(dev, dev_type, offset[0], &hdr_length, NULL);
if (value_container[0] < 0) {
printf("Parse seco container failed %d\n", value_container[0]);
- return value_container[0];
+ return 0;
}
debug("seco container size 0x%x\n", value_container[0]);
+ if (is_imx95()) {
+ offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
+
- value_container[1] = get_dev_container_size(dev, dev_type, offset2, &hdr_length);
- if (value_container[1] < 0) {
- debug("Parse scu container failed %d, only seco container\n",
- value_container[1]);
- /* return seco container total size */
- return value_container[0] + offset1;
+ value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw);
+ if (value_container[1] < 0) {
+ printf("Parse v2x container failed %d\n", value_container[1]);
+ return value_container[0] + offset[0]; /* return seco container total size */
+ }
+
+ if (v2x_fw) {
+ debug("v2x container size 0x%x\n", value_container[1]);
+ offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[1];
+ } else {
+ printf("no v2x container included\n");
+ offset[2] = offset[1];
+ }
+ } else {
+ /* Skip offset[1] */
+ offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
+ }
+
+ value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL);
+ if (value_container[2] < 0) {
+ debug("Parse scu container image failed %d, only seco container\n", value_container[2]);
+ if (is_imx95())
+ return value_container[1] + offset[1]; /* return seco + v2x container total size */
+ else
+ return value_container[0] + offset[0]; /* return seco container total size */
}
- debug("scu container size 0x%x\n", value_container[1]);
+ debug("scu container size 0x%x\n", value_container[2]);
- return value_container[1] + offset2;
+ return value_container[2] + offset[2];
}
#ifdef CONFIG_SPL_SPI_LOAD
unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
{
- int end;
+ ulong end;
end = get_imageset_end(flash, QSPI_DEV);
end = ROUND(end, SZ_1K);
- printf("Load image from QSPI 0x%x\n", end);
+ printf("Load image from QSPI 0x%lx\n", end);
return end;
}
@@ -279,12 +350,12 @@
unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
{
- int end;
+ ulong end;
end = get_imageset_end(mmc, MMC_DEV);
end = ROUND(end, SZ_1K);
- printf("Load image from MMC/SD 0x%x\n", end);
+ printf("Load image from MMC/SD 0x%lx\n", end);
return end / mmc->read_bl_len;
}
@@ -312,12 +383,12 @@
#ifdef CONFIG_SPL_NAND_SUPPORT
uint32_t spl_nand_get_uboot_raw_page(void)
{
- int end;
+ ulong end;
end = get_imageset_end((void *)NULL, NAND_DEV);
end = ROUND(end, SZ_16K);
- printf("Load image from NAND 0x%x\n", end);
+ printf("Load image from NAND 0x%lx\n", end);
return end;
}
@@ -326,7 +397,7 @@
#ifdef CONFIG_SPL_NOR_SUPPORT
unsigned long spl_nor_get_uboot_base(void)
{
- int end;
+ ulong end;
/* Calculate the image set end,
* if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
@@ -339,7 +410,7 @@
else
end = ROUND(end, SZ_1K);
- printf("Load image from NOR 0x%x\n", end);
+ printf("Load image from NOR 0x%lx\n", end);
return end;
}
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 1ccdb1c..0fd82dc 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -24,6 +24,13 @@
select IMX9
select ARMV8_SPL_EXCEPTION_VECTORS
+config IMX95
+ bool
+ select ARMV8_SPL_EXCEPTION_VECTORS
+ select IMX9
+ select DM_MAILBOX
+ select SCMI_FIRMWARE
+ select SPL_IMX_CONTAINER_USE_TRAMPOLINE
config SYS_SOC
default "imx9"
@@ -69,6 +76,13 @@
select OF_BOARD_FIXUP
select OF_BOARD_SETUP
+config TARGET_IMX95_19X19_EVK
+ bool "imx95_19x19_evk"
+ select IMX95
+ imply BOOTSTD_BOOTCOMMAND
+ imply BOOTSTD_FULL
+ imply OF_UPSTREAM
+
endchoice
source "board/freescale/imx91_evk/Kconfig"
@@ -76,6 +90,7 @@
source "board/freescale/imx93_qsb/Kconfig"
source "board/phytec/phycore_imx93/Kconfig"
source "board/variscite/imx93_var_som/Kconfig"
+source "board/freescale/imx95_evk/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 45a9105..53cc97c 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,8 +3,13 @@
# Copyright 2022 NXP
obj-y += lowlevel_init.o
+
+ifeq ($(CONFIG_SCMI_FIRMWARE),y)
+obj-y += scmi/
+else
obj-y += soc.o clock.o clock_root.o trdc.o
+endif
-#ifndef CONFIG_XPL_BUILD
+ifneq ($(CONFIG_SPL_BUILD),y)
obj-y += imx_bootaux.o
-#endif
+endif
\ No newline at end of file
diff --git a/arch/arm/mach-imx/imx9/scmi/Makefile b/arch/arm/mach-imx/imx9/scmi/Makefile
new file mode 100644
index 0000000..4534db0
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2025 NXP
+
+obj-y += soc.o
+obj-y += clock_scmi.o clock.o
diff --git a/arch/arm/mach-imx/imx9/scmi/clock.c b/arch/arm/mach-imx/imx9/scmi/clock.c
new file mode 100644
index 0000000..6e6541e
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/clock.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <asm/arch/clock.h>
+#include <dm/uclass.h>
+#include <scmi_agent.h>
+#include "../../../../../dts/upstream/src/arm64/freescale/imx95-clock.h"
+
+u32 get_arm_core_clk(void)
+{
+ u32 val;
+
+ val = imx_clk_scmi_get_rate(IMX95_CLK_SEL_A55C0);
+ if (val)
+ return val;
+ return imx_clk_scmi_get_rate(IMX95_CLK_A55);
+}
+
+void init_uart_clk(u32 index)
+{
+ u32 clock_id;
+
+ switch (index) {
+ case 0:
+ clock_id = IMX95_CLK_LPUART1;
+ break;
+ case 1:
+ clock_id = IMX95_CLK_LPUART2;
+ break;
+ case 2:
+ clock_id = IMX95_CLK_LPUART3;
+ break;
+ default:
+ return;
+ }
+
+ /* 24MHz */
+ imx_clk_scmi_enable(clock_id, false);
+ imx_clk_scmi_set_parent(clock_id, IMX95_CLK_24M);
+ imx_clk_scmi_set_rate(clock_id, 24000000);
+ imx_clk_scmi_enable(clock_id, true);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_arm_core_clk();
+ case MXC_IPG_CLK:
+ return imx_clk_scmi_get_rate(IMX95_CLK_BUSWAKEUP);
+ case MXC_CSPI_CLK:
+ return imx_clk_scmi_get_rate(IMX95_CLK_LPSPI1);
+ case MXC_ESDHC_CLK:
+ return imx_clk_scmi_get_rate(IMX95_CLK_USDHC1);
+ case MXC_ESDHC2_CLK:
+ return imx_clk_scmi_get_rate(IMX95_CLK_USDHC2);
+ case MXC_ESDHC3_CLK:
+ return imx_clk_scmi_get_rate(IMX95_CLK_USDHC3);
+ case MXC_UART_CLK:
+ return imx_clk_scmi_get_rate(IMX95_CLK_LPUART1);
+ case MXC_FLEXSPI_CLK:
+ return imx_clk_scmi_get_rate(IMX95_CLK_FLEXSPI1);
+ default:
+ return -1;
+ };
+
+ return -1;
+};
diff --git a/arch/arm/mach-imx/imx9/scmi/clock_scmi.c b/arch/arm/mach-imx/imx9/scmi/clock_scmi.c
new file mode 100644
index 0000000..fa15b5f
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/clock_scmi.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <dm/uclass.h>
+#include <scmi_agent.h>
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable)
+{
+ struct scmi_clk_state_in in = {
+ .clock_id = clock_id,
+ .attributes = (enable) ? 1 : 0,
+ };
+ struct scmi_clk_state_out out;
+ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_CLOCK_CONFIG_SET,
+ in, out);
+ int ret;
+ struct udevice *dev;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret)
+ return ret;
+
+ return scmi_to_linux_errno(out.status);
+}
+
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate)
+{
+ struct scmi_clk_rate_set_in in = {
+ .clock_id = clock_id,
+ .flags = SCMI_CLK_RATE_ROUND_CLOSEST,
+ .rate_lsb = (u32)rate,
+ .rate_msb = (u32)((u64)rate >> 32),
+ };
+ struct scmi_clk_rate_set_out out;
+ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_CLOCK_RATE_SET,
+ in, out);
+ int ret;
+ struct udevice *dev;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret < 0)
+ return ret;
+
+ ret = scmi_to_linux_errno(out.status);
+ if (ret < 0)
+ return ret;
+
+ struct scmi_clk_rate_get_in in_rate = {
+ .clock_id = clock_id,
+ };
+ struct scmi_clk_rate_get_out out_rate;
+
+ msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, SCMI_CLOCK_RATE_GET, in_rate, out_rate);
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret < 0)
+ return ret;
+
+ ret = scmi_to_linux_errno(out_rate.status);
+ if (ret < 0)
+ return ret;
+
+ return (ulong)(((u64)out_rate.rate_msb << 32) | out_rate.rate_lsb);
+}
+
+ulong imx_clk_scmi_get_rate(u32 clock_id)
+{
+ struct scmi_clk_rate_get_in in = {
+ .clock_id = clock_id,
+ };
+ struct scmi_clk_rate_get_out out;
+ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_CLOCK_RATE_GET,
+ in, out);
+ int ret;
+ struct udevice *dev;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret < 0)
+ return ret;
+
+ ret = scmi_to_linux_errno(out.status);
+ if (ret < 0)
+ return ret;
+
+ return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb);
+}
+
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id)
+{
+ struct scmi_clk_parent_set_in in = {
+ .clock_id = clock_id,
+ .parent_clk = parent_id,
+ };
+ struct scmi_clk_parent_set_out out;
+ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_CLOCK_PARENT_SET,
+ in, out);
+ int ret;
+ struct udevice *dev;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret < 0)
+ return ret;
+
+ ret = scmi_to_linux_errno(out.status);
+ if (ret < 0 && ret != -EACCES)
+ printf("%s: %d, clock_id %u\n", __func__, ret, clock_id);
+
+ return ret;
+}
diff --git a/arch/arm/mach-imx/imx9/scmi/container.cfg b/arch/arm/mach-imx/imx9/scmi/container.cfg
new file mode 100644
index 0000000..441d9be
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/container.cfg
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+BOOT_FROM SD
+SOC_TYPE IMX9
+CONTAINER
+IMAGE A55 bl31.bin 0x8a200000
+IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
diff --git a/arch/arm/mach-imx/imx9/scmi/imximage.cfg b/arch/arm/mach-imx/imx9/scmi/imximage.cfg
new file mode 100644
index 0000000..6af1c4b
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/imximage.cfg
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+BOOT_FROM SD
+SOC_TYPE IMX9
+APPEND mx95a0-ahab-container.img
+CONTAINER
+IMAGE OEI m33-oei-ddrfw.bin 0x1ffc0000
+HOLD 0x10000
+IMAGE OEI oei-m33-tcm.bin 0x1ffc0000
+IMAGE M33 m33_image.bin 0x1ffc0000
+IMAGE A55 spl/u-boot-spl.bin 0x20480000
+DUMMY_V2X 0x8b000000
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
new file mode 100644
index 0000000..d2b0455
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -0,0 +1,749 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/armv8/mmu.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/setup.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <env_internal.h>
+#include <fuse.h>
+#include <imx_thermal.h>
+#include <linux/iopoll.h>
+#include <scmi_agent.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static rom_passover_t rom_passover_data = {0};
+
+uint32_t scmi_get_rom_data(rom_passover_t *rom_data)
+{
+ /* Read ROM passover data */
+ struct scmi_rom_passover_get_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC,
+ .message_id = SCMI_MISC_ROM_PASSOVER_GET,
+ .in_msg = (u8 *)NULL,
+ .in_msg_sz = 0,
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+ struct udevice *dev;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret == 0 && out.status == 0) {
+ memcpy(rom_data, (struct rom_passover_t *)out.passover, sizeof(rom_passover_t));
+ } else {
+ printf("Failed to get ROM passover data, scmi_err = %d, size_of(out) = %ld\n",
+ out.status, sizeof(out));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_get_env_dev(void)
+{
+ int ret;
+ u16 boot_type;
+ u8 boot_instance;
+
+ volatile gd_t *pgd = gd;
+ rom_passover_t *rdata;
+
+#if IS_ENABLED(CONFIG_XPL_BUILD)
+ rdata = &rom_passover_data;
+#else
+ rom_passover_t rom_data = {0};
+
+ if (!pgd->reloc_off)
+ rdata = &rom_data;
+ else
+ rdata = &rom_passover_data;
+#endif
+ if (rdata->tag == 0) {
+ ret = scmi_get_rom_data(rdata);
+ if (ret != 0) {
+ puts("SCMI: failure at rom_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+ }
+ boot_type = rdata->boot_dev_type;
+ boot_instance = rdata->boot_dev_inst;
+ set_gd(pgd);
+
+ debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
+ /* If not boot from sd/mmc, use default value */
+ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+}
+#endif
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ u32 speed, max_speed;
+ int ret;
+ u32 val, word, offset;
+
+ word = 17;
+ offset = 14;
+
+ ret = fuse_read(word / 8, word % 8, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
+ val >>= offset;
+ val &= 0xf;
+
+ max_speed = 2300000000;
+ speed = max_speed - val * 100000000;
+
+ if (is_imx95())
+ max_speed = 2000000000;
+
+ /* In case the fuse of speed grade not programmed */
+ if (speed > max_speed)
+ speed = max_speed;
+
+ return speed;
+}
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ int ret;
+ u32 val, word, offset;
+
+ word = 17;
+ offset = 12;
+
+ ret = fuse_read(word / 8, word % 8, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
+ val >>= offset;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
+static void set_cpu_info(struct ele_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
+u32 get_cpu_rev(void)
+{
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+ return (MXC_CPU_IMX95 << 12) | (CHIP_REV_1_0 + rev);
+}
+
+#define UNLOCK_WORD 0xD928C520
+#define REFRESH_WORD 0xB480A602
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+ int ret = 0;
+
+ if (!(val_cs & 0x80))
+ return;
+
+ /* default is 32bits cmd */
+ writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
+
+ if (!(val_cs & 0x800)) {
+ writel(UNLOCK_WORD, (wdog_base + 0x04));
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ ret = readl_poll_timeout(wdog_base, val_cs, val_cs & 0x400, 100000);
+ if (ret < 0)
+ debug("%s timeout\n", __func__);
+}
+
+static struct mm_region imx9_mem_map[] = {
+ {
+ /* M7 TCM */
+ .virt = 0x203c0000UL,
+ .phys = 0x203c0000UL,
+ .size = 0x80000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* OCRAM */
+ .virt = 0x20480000UL,
+ .phys = 0x20480000UL,
+ .size = 0xA0000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* AIPS */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Flexible Serial Peripheral Interface */
+ .virt = 0x28000000UL,
+ .phys = 0x28000000UL,
+ .size = 0x8000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* DRAM1 */
+ .virt = PHYS_SDRAM,
+ .phys = PHYS_SDRAM,
+ .size = PHYS_SDRAM_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+#ifdef PHYS_SDRAM_2_SIZE
+ /* DRAM2 */
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = PHYS_SDRAM_2_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+#endif
+ /* empty entry to split table entry 5 if needed when TEEs are used */
+ 0,
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = imx9_mem_map;
+
+static unsigned int imx9_find_dram_entry_in_mem_map(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx9_mem_map); i++)
+ if (imx9_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
+ return i;
+
+ hang(); /* Entry not found, this must never happen. */
+}
+
+void enable_caches(void)
+{
+ /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
+ * If OPTEE does not run, still update the MMU table according to dram banks structure
+ * to set correct dram size from board_phys_sdram_size
+ */
+ int i = 0;
+ /*
+ * please make sure that entry initial value matches
+ * imx9_mem_map for DRAM1
+ */
+ int entry = imx9_find_dram_entry_in_mem_map();
+ u64 attrs = imx9_mem_map[entry].attrs;
+
+ while (i < CONFIG_NR_DRAM_BANKS &&
+ entry < ARRAY_SIZE(imx9_mem_map)) {
+ if (gd->bd->bi_dram[i].start == 0)
+ break;
+ imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+ imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+ imx9_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx9_mem_map[entry].attrs = attrs;
+ debug("Added memory mapping (%d): %llx %llx\n", entry,
+ imx9_mem_map[entry].phys, imx9_mem_map[entry].size);
+ i++; entry++;
+ }
+
+ icache_enable();
+ dcache_enable();
+}
+
+__weak int board_phys_sdram_size(phys_size_t *size)
+{
+ phys_size_t start, end;
+ phys_size_t val;
+
+ if (!size)
+ return -EINVAL;
+
+ val = readl(REG_DDR_CS0_BNDS);
+ start = (val >> 16) << 24;
+ end = (val & 0xFFFF);
+ end = end ? end + 1 : 0;
+ end = end << 24;
+ *size = end - start;
+
+ val = readl(REG_DDR_CS1_BNDS);
+ start = (val >> 16) << 24;
+ end = (val & 0xFFFF);
+ end = end ? end + 1 : 0;
+ end = end << 24;
+ *size += end - start;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ phys_size_t sdram_size;
+ int ret;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return ret;
+
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0])
+ gd->ram_size = sdram_size - rom_pointer[1];
+ else
+ gd->ram_size = sdram_size;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ int bank = 0;
+ int ret;
+ phys_size_t sdram_size;
+ phys_size_t sdram_b1_size, sdram_b2_size;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return ret;
+
+ /* Bank 1 can't cross over 4GB space */
+ if (sdram_size > 0x80000000) {
+ sdram_b1_size = 0x100000000UL - PHYS_SDRAM;
+ sdram_b2_size = sdram_size - sdram_b1_size;
+ } else {
+ sdram_b1_size = sdram_size;
+ sdram_b2_size = 0;
+ }
+
+ gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+ if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) {
+ phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
+ phys_size_t optee_size = (size_t)rom_pointer[1];
+
+ gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+ if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
+ puts("CONFIG_NR_DRAM_BANKS is not enough\n");
+ return -1;
+ }
+
+ gd->bd->bi_dram[bank].start = optee_start + optee_size;
+ gd->bd->bi_dram[bank].size = PHYS_SDRAM +
+ sdram_b1_size - gd->bd->bi_dram[bank].start;
+ }
+ } else {
+ gd->bd->bi_dram[bank].size = sdram_b1_size;
+ }
+
+ if (sdram_b2_size) {
+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
+ puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
+ return -1;
+ }
+ gd->bd->bi_dram[bank].start = 0x100000000UL;
+ gd->bd->bi_dram[bank].size = sdram_b2_size;
+ }
+
+ return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ int ret;
+ phys_size_t sdram_size;
+ phys_size_t sdram_b1_size;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (!ret) {
+ /* Bank 1 can't cross over 4GB space */
+ if (sdram_size > 0x80000000)
+ sdram_b1_size = 0x100000000UL - PHYS_SDRAM;
+ else
+ sdram_b1_size = sdram_size;
+
+ if (rom_pointer[1]) {
+ /* We will relocate u-boot to Top of dram1. Tee position has three cases:
+ * 1. At the top of dram1, Then return the size removed optee size.
+ * 2. In the middle of dram1, return the size of dram1.
+ * 3. Not in the scope of dram1, return the size of dram1.
+ */
+ if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
+ return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+ }
+
+ return sdram_b1_size;
+ } else {
+ return PHYS_SDRAM_SIZE;
+ }
+}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ u32 val[2] = {};
+ int ret, num_of_macs;
+
+ ret = fuse_read(40, 5, &val[0]);
+ if (ret)
+ goto err;
+
+ ret = fuse_read(40, 6, &val[1]);
+ if (ret)
+ goto err;
+
+ num_of_macs = (val[1] >> 24) & 0xff;
+ if (num_of_macs <= (dev_id * 3)) {
+ printf("WARNING: no MAC address assigned for MAC%d\n", dev_id);
+ goto err;
+ }
+
+ mac[0] = val[0] & 0xff;
+ mac[1] = (val[0] >> 8) & 0xff;
+ mac[2] = (val[0] >> 16) & 0xff;
+ mac[3] = (val[0] >> 24) & 0xff;
+ mac[4] = val[1] & 0xff;
+ mac[5] = (val[1] >> 8) & 0xff;
+ if (dev_id == 1)
+ mac[5] = mac[5] + 3;
+ if (dev_id == 2)
+ mac[5] = mac[5] + 6;
+
+ debug("%s: MAC%d: %pM\n", __func__, dev_id, mac);
+ return;
+err:
+ memset(mac, 0, 6);
+ printf("%s: fuse read err: %d\n", __func__, ret);
+}
+
+const char *get_imx_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_IMX95:
+ return "95";/* iMX95 FULL */
+ default:
+ return "??";
+ }
+}
+
+void build_info(void)
+{
+ u32 fw_version, sha1, res = 0, status;
+ int ret;
+
+ printf("\nBuildInfo:\n");
+
+ ret = ele_get_fw_status(&status, &res);
+ if (ret) {
+ printf(" - ELE firmware status failed %d, 0x%x\n", ret, res);
+ } else if ((status & 0xff) == 1) {
+ ret = ele_get_fw_version(&fw_version, &sha1, &res);
+ if (ret) {
+ printf(" - ELE firmware version failed %d, 0x%x\n", ret, res);
+ } else {
+ printf(" - ELE firmware version %u.%u.%u-%x",
+ (fw_version & (0x00ff0000)) >> 16,
+ (fw_version & (0x0000fff0)) >> 4,
+ (fw_version & (0x0000000f)), sha1);
+ ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n");
+ }
+ } else {
+ printf(" - ELE firmware not included\n");
+ }
+ puts("\n");
+}
+
+int arch_misc_init(void)
+{
+ build_info();
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_SPL_BUILD)
+int board_fix_fdt(void *fdt)
+{
+ return 0;
+}
+#endif
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ printf("UID: %08x%08x%08x%08x\n", __be32_to_cpu(gd->arch.uid[0]),
+ __be32_to_cpu(gd->arch.uid[1]), __be32_to_cpu(gd->arch.uid[2]),
+ __be32_to_cpu(gd->arch.uid[3]));
+
+ serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
+ serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
+}
+#endif
+
+static void gpio_reset(ulong gpio_base)
+{
+ writel(0, gpio_base + 0x10);
+ writel(0, gpio_base + 0x14);
+ writel(0, gpio_base + 0x18);
+ writel(0, gpio_base + 0x1c);
+}
+
+int arch_cpu_init(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ disable_wdog((void __iomem *)WDG3_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+
+ gpio_reset(GPIO2_BASE_ADDR);
+ gpio_reset(GPIO3_BASE_ADDR);
+ gpio_reset(GPIO4_BASE_ADDR);
+ gpio_reset(GPIO5_BASE_ADDR);
+ }
+
+ return 0;
+}
+
+int imx9_probe_mu(void)
+{
+ struct udevice *dev;
+ int ret;
+ u32 res;
+ struct ele_get_info_data info;
+
+ ret = uclass_get_device_by_driver(UCLASS_SCMI_AGENT, DM_DRIVER_GET(scmi_mbox), &dev);
+ if (ret)
+ return ret;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ ret = devm_scmi_of_get_channel(dev);
+ if (ret)
+ return ret;
+
+ ret = uclass_get_device_by_name(UCLASS_PINCTRL, "protocol@19", &dev);
+ if (ret)
+ return ret;
+
+#if defined(CONFIG_SPL_BUILD)
+ ret = uclass_get_device_by_name(UCLASS_MISC, "mailbox@47530000", &dev);
+#else
+ ret = uclass_get_device_by_name(UCLASS_MISC, "mailbox@47550000", &dev);
+#endif
+ if (ret)
+ return ret;
+
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
+ ret = ele_get_info(&info, &res);
+ if (ret)
+ return ret;
+
+ set_cpu_info(&info);
+
+ return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu);
+
+int timer_init(void)
+{
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ unsigned long freq = 24000000;
+
+ asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+ /* Clear the compare frame interrupt */
+ unsigned long sctr_cmpcr_addr = SYSCNT_CMP_BASE_ADDR + 0x2c;
+ unsigned long sctr_cmpcr = readl(sctr_cmpcr_addr);
+
+ sctr_cmpcr &= ~0x1;
+ writel(sctr_cmpcr, sctr_cmpcr_addr);
+ }
+
+ return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ switch (dev) {
+ case QSPI_BOOT:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+ default:
+ env_loc = ENVL_NOWHERE;
+ break;
+ }
+
+ return env_loc;
+}
+
+enum imx9_soc_voltage_mode soc_target_voltage_mode(void)
+{
+ u32 speed = get_cpu_speed_grade_hz();
+ enum imx9_soc_voltage_mode voltage = VOLT_OVER_DRIVE;
+
+ if (is_imx95()) {
+ if (speed == 2000000000)
+ voltage = VOLT_SUPER_OVER_DRIVE;
+ else if (speed == 1800000000)
+ voltage = VOLT_OVER_DRIVE;
+ else if (speed == 1400000000)
+ voltage = VOLT_NOMINAL_DRIVE;
+ else /* boot not support low drive mode according to AS */
+ printf("Unexpected A55 freq %u, default to OD\n", speed);
+ }
+
+ return voltage;
+}
+
+#if IS_ENABLED(CONFIG_SCMI_FIRMWARE)
+enum boot_device get_boot_device(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u16 boot_type;
+ u8 boot_instance;
+ enum boot_device boot_dev = 0;
+ rom_passover_t *rdata;
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+ rdata = &rom_passover_data;
+#else
+ rom_passover_t rom_data = {0};
+
+ if (pgd->reloc_off == 0)
+ rdata = &rom_data;
+ else
+ rdata = &rom_passover_data;
+#endif
+ if (rdata->tag == 0) {
+ ret = scmi_get_rom_data(rdata);
+ if (ret != 0) {
+ puts("SCMI: failure at rom_boot_info\n");
+ return -1;
+ }
+ }
+ boot_type = rdata->boot_dev_type;
+ boot_instance = rdata->boot_dev_inst;
+
+ set_gd(pgd);
+
+ switch (boot_type) {
+ case BT_DEV_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BT_DEV_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BT_DEV_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BT_DEV_TYPE_FLEXSPINOR:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BT_DEV_TYPE_USB:
+ boot_dev = boot_instance + USB_BOOT;
+ if (IS_ENABLED(CONFIG_IMX95))
+ boot_dev -= 3; //iMX95 usb instance start at 3
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+#endif
+
+bool arch_check_dst_in_secure(void *start, ulong size)
+{
+ ulong ns_end = CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE;
+#ifdef PHYS_SDRAM_2_SIZE
+ ns_end += PHYS_SDRAM_2_SIZE;
+#endif
+
+ if ((ulong)start < CFG_SYS_SDRAM_BASE || (ulong)start + size > ns_end)
+ return true;
+
+ return false;
+}
+
+void *arch_get_container_trampoline(void)
+{
+ return (void *)((ulong)CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE - SZ_16M);
+}
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index fa8cd93..fc230f1 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -228,10 +228,6 @@
gd->arch.tlb_size = PGTABLE_SIZE;
gd->ram_top += get_effective_memsize();
- /* keep ram_top in the 32-bit address space */
- if (gd->ram_top >= 0x100000000)
- gd->ram_top = (phys_addr_t)0x100000000;
-
gd->relocaddr = gd->ram_top;
ret = spl_reserve_video_from_ram_top();
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 2ec60c7..02c7473 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -10,6 +10,9 @@
#include <asm/hardware.h>
#include <mach/security.h>
+/* keep ram_top in the 32-bit address space */
+#define CFG_MAX_MEM_MAPPED 0x100000000
+
#define K3_FIREWALL_BACKGROUND_BIT (8)
struct fwl_data {
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index a175e5c..b50b8a5 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -95,6 +95,7 @@
select OMAP3_GPIO_4
select OMAP3_GPIO_6
imply CMD_DM
+ imply VIDEO_DAMAGE
config TARGET_TAO3530
bool "TAO3530"
diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig
index aeb55da..d373ab5 100644
--- a/arch/arm/mach-renesas/Kconfig
+++ b/arch/arm/mach-renesas/Kconfig
@@ -76,6 +76,7 @@
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
imply PINCTRL_RZG2L
+ imply RENESAS_RAVB
imply RENESAS_SDHI
imply RZG2L_GPIO
imply SCIF_CONSOLE
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index deae4d3..3ab75f0 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -306,7 +306,6 @@
int board_init(void)
{
show_psci_version();
- qcom_of_fixup_nodes();
qcom_board_init();
return 0;
}
diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c
index 1ea0c18..b398c6b 100644
--- a/arch/arm/mach-snapdragon/of_fixup.c
+++ b/arch/arm/mach-snapdragon/of_fixup.c
@@ -4,8 +4,7 @@
*
* This file implements runtime fixups for Qualcomm DT to improve
* compatibility with U-Boot. This includes adjusting the USB nodes
- * to only use USB high-speed, as well as remapping volume buttons
- * to behave as up/down for navigating U-Boot.
+ * to only use USB high-speed.
*
* We use OF_LIVE for this rather than early FDT fixup for a couple
* of reasons: it has a much nicer API, is most likely more efficient,
@@ -22,6 +21,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dm/of_access.h>
#include <dm/of.h>
+#include <event.h>
#include <fdt_support.h>
#include <linux/errno.h>
#include <stdlib.h>
@@ -32,7 +32,7 @@
* DT here. This improves compatibility with upstream DT and simplifies the
* porting process for new devices.
*/
-static int fixup_qcom_dwc3(struct device_node *glue_np)
+static int fixup_qcom_dwc3(struct device_node *root, struct device_node *glue_np)
{
struct device_node *dwc3;
int ret, len, hsphy_idx = 1;
@@ -72,11 +72,12 @@
return ret;
}
- if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) {
- log_debug("Second phy isn't superspeed (is '%s') assuming first phy is SS\n",
- second_phy_name);
+ /*
+ * Determine which phy is the superspeed phy by checking the name of the second phy
+ * since it is typically the superspeed one.
+ */
+ if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy")))
hsphy_idx = 0;
- }
/* Overwrite the "phys" property to only contain the high-speed phy */
ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles + hsphy_idx);
@@ -98,30 +99,45 @@
return ret;
}
+ /*
+ * The RB1/2 boards only have a single USB controller and it's muxed between the type-C port
+ * and a USB hub. Since we can't do OTG in U-Boot properly we prefer to put it into host mode.
+ */
+ if (of_device_is_compatible(root, "qcom,qrb4210-rb2", NULL, NULL) ||
+ of_device_is_compatible(root, "qcom,qrb2210-rb1", NULL, NULL)) {
+ ret = of_write_prop(dwc3, "dr_mode", sizeof("host"), "host");
+ if (ret) {
+ log_err("Failed to set 'dr_mode' property: %d\n", ret);
+ return ret;
+ }
+ }
+
return 0;
}
-static void fixup_usb_nodes(void)
+static void fixup_usb_nodes(struct device_node *root)
{
- struct device_node *glue_np = NULL;
+ struct device_node *glue_np = root;
int ret;
while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3"))) {
- ret = fixup_qcom_dwc3(glue_np);
+ if (!of_device_is_available(glue_np))
+ continue;
+ ret = fixup_qcom_dwc3(root, glue_np);
if (ret)
log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret);
}
}
/* Remove all references to the rpmhpd device */
-static void fixup_power_domains(void)
+static void fixup_power_domains(struct device_node *root)
{
struct device_node *pd = NULL, *np = NULL;
struct property *prop;
const __be32 *val;
/* All Qualcomm platforms name the rpm(h)pd "power-controller" */
- for_each_of_allnodes(pd) {
+ for_each_of_allnodes_from(root, pd) {
if (pd->name && !strcmp("power-controller", pd->name))
break;
}
@@ -133,7 +149,7 @@
}
/* Remove all references to the power domain controller */
- for_each_of_allnodes(np) {
+ for_each_of_allnodes_from(root, np) {
if (!(prop = of_find_property(np, "power-domains", NULL)))
continue;
@@ -150,26 +166,19 @@
debug(#func " took %lluus\n", timer_get_us() - start); \
} while (0)
-void qcom_of_fixup_nodes(void)
+static int qcom_of_fixup_nodes(void * __maybe_unused ctx, struct event *event)
{
- time_call(fixup_usb_nodes);
- time_call(fixup_power_domains);
-}
+ struct device_node *root = event->data.of_live_built.root;
-int ft_board_setup(void *blob, struct bd_info __maybe_unused *bd)
-{
- struct fdt_header *fdt = blob;
- int node;
+ time_call(fixup_usb_nodes, root);
+ time_call(fixup_power_domains, root);
- /* On RB1/2 we need to fix-up the dr_mode */
- if (!fdt_node_check_compatible(fdt, 0, "qcom,qrb4210-rb2") ||
- !fdt_node_check_compatible(fdt, 0, "qcom,qrb2210-rb1")) {
- fdt_for_each_node_by_compatible(node, blob, 0, "snps,dwc3") {
- log_debug("%s: Setting 'dr_mode' to OTG\n", fdt_get_name(blob, node, NULL));
- fdt_setprop_string(fdt, node, "dr_mode", "otg");
- break;
- }
- }
+ return 0;
+}
+
+EVENT_SPY_FULL(EVT_OF_LIVE_BUILT, qcom_of_fixup_nodes);
+int ft_board_setup(void __maybe_unused *blob, struct bd_info __maybe_unused *bd)
+{
return 0;
}
diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h
index 74d3919..4f398e2 100644
--- a/arch/arm/mach-snapdragon/qcom-priv.h
+++ b/arch/arm/mach-snapdragon/qcom-priv.h
@@ -9,18 +9,4 @@
void qcom_configure_capsule_updates(void) {}
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
-#if CONFIG_IS_ENABLED(OF_LIVE)
-/**
- * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes
- *
- * Adjusts nodes in the live tree to improve compatibility with U-Boot.
- */
-void qcom_of_fixup_nodes(void);
-#else
-static inline void qcom_of_fixup_nodes(void)
-{
- log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n");
-}
-#endif /* OF_LIVE */
-
#endif /* __QCOM_PRIV_H__ */
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index a44ebf2..de9d854 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -15,6 +15,7 @@
select STM32_SERIAL
select STM32_TIMER
select TIMER
+ imply OF_UPSTREAM
config STM32F7
bool "stm32f7 family"
@@ -32,6 +33,7 @@
select STM32_TIMER
select SUPPORT_SPL
select TIMER
+ imply OF_UPSTREAM
imply SPL_OS_BOOT
config STM32H7
@@ -51,6 +53,7 @@
select STM32_TIMER
select SYSCON
select TIMER
+ imply OF_UPSTREAM
source "arch/arm/mach-stm32/stm32f4/Kconfig"
source "arch/arm/mach-stm32/stm32f7/Kconfig"
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 002da2e..5825090 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -52,6 +52,7 @@
select STM32_SERIAL
select SYS_ARCH_TIMER
imply CMD_NVEDIT_INFO
+ imply OF_UPSTREAM
help
support of STMicroelectronics SOC STM32MP13x family
STMicroelectronics MPU with core ARMv7
@@ -73,6 +74,7 @@
select SUPPORT_SPL
select SYS_ARCH_TIMER
imply CMD_NVEDIT_INFO
+ imply OF_UPSTREAM
help
support of STMicroelectronics SOC STM32MP15x family
STM32MP157, STM32MP153 or STM32MP151
@@ -94,6 +96,7 @@
imply CMD_NVEDIT_INFO
imply DM_REGULATOR
imply DM_REGULATOR_SCMI
+ imply OF_UPSTREAM
imply OPTEE
imply RESET_SCMI
imply SYSRESET_PSCI
@@ -127,14 +130,6 @@
Partition on the second MMC to load U-Boot from when the MMC is being
used in raw mode
-config STM32_ETZPC
- bool "STM32 Extended TrustZone Protection"
- depends on STM32MP15X || STM32MP13X
- default y
- imply BOOTP_SERVERIP
- help
- Say y to enable STM32 Extended TrustZone Protection
-
config STM32_ECDSA_VERIFY
bool "STM32 ECDSA verification via the ROM API"
depends on SPL_ECDSA_VERIFY
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
index 040a70f..6bfa678 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -14,12 +14,23 @@
/*
* Closed device: OTP0
- * STM32MP15x: bit 6 of OPT0
+ * STM32MP15x: bit 6 of OTP0
* STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device
+ * STM32MP25x: bit 0 of OTP18
*/
-#define STM32_OTP_CLOSE_ID 0
-#define STM32_OTP_STM32MP13X_CLOSE_MASK 0x3F
-#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6)
+#define STM32MP1_OTP_CLOSE_ID 0
+#define STM32_OTP_STM32MP13X_CLOSE_MASK GENMASK(5, 0)
+#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6)
+#define STM32MP25_OTP_WORD8 8
+#define STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK GENMASK(7, 0)
+#define STM32MP25_OTP_CLOSE_ID 18
+#define STM32_OTP_STM32MP25X_CLOSE_MASK GENMASK(3, 0)
+#define STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK GENMASK(7, 4)
+#define STM32MP25_OTP_HWCONFIG 124
+#define STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK BIT(20)
+
+#define STM32MP25_OTP_BOOTROM_CONF8 17
+#define STM32_OTP_STM32MP25X_OEM_KEY2_EN BIT(8)
/* PKH is the first element of the key list */
#define STM32KEY_PKH 0
@@ -27,8 +38,9 @@
struct stm32key {
char *name;
char *desc;
- u8 start;
+ u16 start;
u8 size;
+ int (*post_process)(struct udevice *dev);
};
const struct stm32key stm32mp13_list[] = {
@@ -52,9 +64,102 @@
.desc = "Hash of the ECC Public Key (ECDSA is the authentication algorithm)",
.start = 24,
.size = 8,
+ }
+};
+
+static int post_process_oem_key2(struct udevice *dev);
+
+const struct stm32key stm32mp25_list[] = {
+ [STM32KEY_PKH] = {
+ .name = "OEM-KEY1",
+ .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLA or M",
+ .start = 144,
+ .size = 8,
+ },
+ {
+ .name = "OEM-KEY2",
+ .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLM",
+ .start = 152,
+ .size = 8,
+ .post_process = post_process_oem_key2,
+ },
+ {
+ .name = "FIP-EDMK",
+ .desc = "Encryption/Decryption Master Key for FIP",
+ .start = 260,
+ .size = 8,
+ },
+ {
+ .name = "EDMK1",
+ .desc = "Encryption/Decryption Master Key for FSBLA or M",
+ .start = 364,
+ .size = 4,
+ },
+ {
+ .name = "EDMK2",
+ .desc = "Encryption/Decryption Master Key for FSBLM",
+ .start = 360,
+ .size = 4,
+ }
+};
+
+struct otp_close {
+ u32 word;
+ u32 mask_wr;
+ u32 mask_rd;
+ bool (*close_status_ops)(u32 value, u32 mask);
+};
+
+static bool compare_mask_exact(u32 value, u32 mask)
+{
+ return ((value & mask) == mask);
+}
+
+static bool compare_any_bits(u32 value, u32 mask)
+{
+ return ((value & mask) != 0);
+}
+
+const struct otp_close stm32mp13_close_state_otp[] = {
+ {
+ .word = STM32MP1_OTP_CLOSE_ID,
+ .mask_wr = STM32_OTP_STM32MP13X_CLOSE_MASK,
+ .mask_rd = STM32_OTP_STM32MP13X_CLOSE_MASK,
+ .close_status_ops = compare_mask_exact,
+ }
+};
+
+const struct otp_close stm32mp15_close_state_otp[] = {
+ {
+ .word = STM32MP1_OTP_CLOSE_ID,
+ .mask_wr = STM32_OTP_STM32MP15X_CLOSE_MASK,
+ .mask_rd = STM32_OTP_STM32MP15X_CLOSE_MASK,
+ .close_status_ops = compare_mask_exact,
}
};
+const struct otp_close stm32mp25_close_state_otp[] = {
+ {
+ .word = STM32MP25_OTP_WORD8,
+ .mask_wr = STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK,
+ .mask_rd = 0,
+ .close_status_ops = NULL
+ },
+ {
+ .word = STM32MP25_OTP_CLOSE_ID,
+ .mask_wr = STM32_OTP_STM32MP25X_CLOSE_MASK |
+ STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK,
+ .mask_rd = STM32_OTP_STM32MP25X_CLOSE_MASK,
+ .close_status_ops = compare_any_bits
+ },
+ {
+ .word = STM32MP25_OTP_HWCONFIG,
+ .mask_wr = STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK,
+ .mask_rd = 0,
+ .close_status_ops = NULL
+ },
+};
+
/* index of current selected key in stm32key list, 0 = PKH by default */
static u8 stm32key_index;
@@ -65,6 +170,9 @@
if (IS_ENABLED(CONFIG_STM32MP15X))
return ARRAY_SIZE(stm32mp15_list);
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return ARRAY_SIZE(stm32mp25_list);
}
static const struct stm32key *get_key(u8 index)
@@ -74,17 +182,35 @@
if (IS_ENABLED(CONFIG_STM32MP15X))
return &stm32mp15_list[index];
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return &stm32mp25_list[index];
}
-static u32 get_otp_close_mask(void)
+static u8 get_otp_close_state_nb(void)
{
if (IS_ENABLED(CONFIG_STM32MP13X))
- return STM32_OTP_STM32MP13X_CLOSE_MASK;
+ return ARRAY_SIZE(stm32mp13_close_state_otp);
if (IS_ENABLED(CONFIG_STM32MP15X))
- return STM32_OTP_STM32MP15X_CLOSE_MASK;
+ return ARRAY_SIZE(stm32mp15_close_state_otp);
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return ARRAY_SIZE(stm32mp25_close_state_otp);
}
+static const struct otp_close *get_otp_close_state(u8 index)
+{
+ if (IS_ENABLED(CONFIG_STM32MP13X))
+ return &stm32mp13_close_state_otp[index];
+
+ if (IS_ENABLED(CONFIG_STM32MP15X))
+ return &stm32mp15_close_state_otp[index];
+
+ if (IS_ENABLED(CONFIG_STM32MP25X))
+ return &stm32mp25_close_state_otp[index];
+}
+
static int get_misc_dev(struct udevice **dev)
{
int ret;
@@ -96,13 +222,13 @@
return ret;
}
-static void read_key_value(const struct stm32key *key, u32 addr)
+static void read_key_value(const struct stm32key *key, unsigned long addr)
{
int i;
for (i = 0; i < key->size; i++) {
printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i,
- addr, __be32_to_cpu(*(u32 *)addr));
+ (u32)addr, __be32_to_cpu(*(u32 *)addr));
addr += 4;
}
}
@@ -157,26 +283,42 @@
static int read_close_status(struct udevice *dev, bool print, bool *closed)
{
- int word, ret, result;
- u32 val, lock, mask;
- bool status;
+ int ret, result, i;
+ const struct otp_close *otp_close = NULL;
+ u32 otp_close_nb = get_otp_close_state_nb();
+ u32 val, lock, mask, word = 0;
+ bool status = true;
+ bool tested_once = false;
result = 0;
- word = STM32_OTP_CLOSE_ID;
- ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
- if (ret < 0)
- result = ret;
- if (ret != 4)
- val = 0x0;
+ for (i = 0; status && (i < otp_close_nb); i++) {
+ otp_close = get_otp_close_state(i);
- ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
- if (ret < 0)
- result = ret;
- if (ret != 4)
- lock = BSEC_LOCK_ERROR;
+ if (!otp_close->close_status_ops)
+ continue;
- mask = get_otp_close_mask();
- status = (val & mask) == mask;
+ mask = otp_close->mask_rd;
+ word = otp_close->word;
+
+ ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret < 0)
+ result = ret;
+ if (ret != 4)
+ val = 0x0;
+
+ ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ if (ret < 0)
+ result = ret;
+ if (ret != 4)
+ lock = BSEC_LOCK_ERROR;
+
+ status = otp_close->close_status_ops(val, mask);
+ tested_once = true;
+ }
+
+ if (!tested_once)
+ status = false;
+
if (closed)
*closed = status;
if (print)
@@ -185,7 +327,49 @@
return result;
}
+static int write_close_status(struct udevice *dev)
+{
+ int i;
+ u32 val, word, ret;
+ const struct otp_close *otp_close = NULL;
+ u32 otp_num = get_otp_close_state_nb();
+
+ for (i = 0; i < otp_num; i++) {
+ otp_close = get_otp_close_state(i);
+ val = otp_close->mask_wr;
+ word = otp_close->word;
+ ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4) {
+ log_err("Error: can't update OTP %d\n", word);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int post_process_oem_key2(struct udevice *dev)
+{
+ int ret;
+ u32 val;
+
+ ret = misc_read(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
+ if (ret != 4) {
+ log_err("Error %d failed to read STM32MP25_OTP_BOOTROM_CONF8\n", ret);
+ return -EIO;
+ }
+
+ val |= STM32_OTP_STM32MP25X_OEM_KEY2_EN;
+ ret = misc_write(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
+ if (ret != 4) {
+ log_err("Error %d failed to write OEM_KEY2_ENABLE\n", ret);
+ return -EIO;
+ }
+
+ return 0;
+}
+
-static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print)
+static int fuse_key_value(struct udevice *dev, const struct stm32key *key, unsigned long addr,
+ bool print)
{
u32 word, val;
int i, ret;
@@ -229,7 +413,7 @@
static void display_key_info(const struct stm32key *key)
{
printf("%s : %s\n", key->name, key->desc);
- printf("\tOTP%d..%d\n", key->start, key->start + key->size);
+ printf("\tOTP%d..%d\n", key->start, key->start + key->size - 1);
}
static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
@@ -272,7 +456,7 @@
{
const struct stm32key *key;
struct udevice *dev;
- u32 addr;
+ unsigned long addr;
int ret, i;
int result;
@@ -310,7 +494,7 @@
return CMD_RET_USAGE;
key = get_key(stm32key_index);
- printf("Read %s at 0x%08x\n", key->name, addr);
+ printf("Read %s at 0x%08x\n", key->name, (u32)addr);
read_key_value(key, addr);
return CMD_RET_SUCCESS;
@@ -320,7 +504,7 @@
{
const struct stm32key *key = get_key(stm32key_index);
struct udevice *dev;
- u32 addr;
+ unsigned long addr;
int ret;
bool yes = false, lock;
@@ -361,6 +545,13 @@
if (fuse_key_value(dev, key, addr, !yes))
return CMD_RET_FAILURE;
+ if (key->post_process) {
+ if (key->post_process(dev)) {
+ printf("Error: %s for post process\n", key->name);
+ return CMD_RET_FAILURE;
+ }
+ }
+
printf("%s updated !\n", key->name);
return CMD_RET_SUCCESS;
@@ -371,7 +562,6 @@
const struct stm32key *key;
bool yes, lock, closed;
struct udevice *dev;
- u32 val;
int ret;
yes = false;
@@ -407,12 +597,8 @@
if (!yes && !confirm_prog())
return CMD_RET_FAILURE;
- val = get_otp_close_mask();
- ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4);
- if (ret != 4) {
- printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID);
+ if (write_close_status(dev))
return CMD_RET_FAILURE;
- }
printf("Device is closed !\n");
@@ -432,3 +618,25 @@
U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read),
U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse),
U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close));
+
+/*
+ * Check the "closed" state in product life cycle, when product secrets have
+ * been provisioned into the device, by SSP tools for example.
+ * On closed devices, authentication is mandatory.
+ */
+bool stm32mp_is_closed(void)
+{
+ struct udevice *dev;
+ bool closed;
+ int ret;
+
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return false;
+
+ ret = read_close_status(dev, false, &closed);
+ if (ret)
+ return false;
+
+ return closed;
+}
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
index 5892762..490097e 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
@@ -27,6 +27,8 @@
config CMD_STM32PROG_SERIAL
bool "support stm32prog over UART"
depends on CMD_STM32PROG
+ imply DISABLE_CONSOLE
+ imply SILENT_CONSOLE
default y
help
activate the command "stm32prog serial" for STM32MP soc family
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index 353aecc..5b027fa 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -13,6 +13,7 @@
#include <part.h>
#include <tee.h>
#include <asm/arch/stm32mp1_smc.h>
+#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/uclass.h>
@@ -1156,7 +1157,8 @@
/* partition UUID */
uuid_bin = NULL;
- if (!rootfs_found && !strcmp(part->name, "rootfs")) {
+ if (!rootfs_found && (!strcmp(part->name, "rootfs") ||
+ !strcmp(part->name, "rootfs-a"))) {
mmc_id = part->dev_id;
rootfs_found = true;
if (mmc_id < ARRAY_SIZE(uuid_mmc))
@@ -1357,7 +1359,7 @@
alt_nb = 1; /* number of virtual = CMD*/
- if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && !stm32mp_is_closed()) {
/* OTP_SIZE_SMC = 0 if SMC is not supported */
otp_size = OTP_SIZE_SMC;
/* check if PTA BSEC is supported */
diff --git a/arch/arm/mach-stm32mp/include/mach/etzpc.h b/arch/arm/mach-stm32mp/include/mach/etzpc.h
new file mode 100644
index 0000000..fd697c3
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/etzpc.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef MACH_ETZPC_H
+#define MACH_ETZPC_H
+
+#include <linux/types.h>
+
+/**
+ * stm32_etzpc_check_access - Check ETZPC accesses for given device node
+ *
+ * @device_node Node of the device for which the accesses are checked
+ *
+ * @returns 0 on success (if access is granted), -EINVAL if access is denied.
+ * Else, returns an appropriate negative ERRNO value
+ */
+int stm32_etzpc_check_access(ofnode device_node);
+
+/**
+ * stm32_etzpc_check_access_by_id - Check ETZPC accesses for given id
+ *
+ * @device_node Node of the device to get a reference on ETZPC
+ * @id ID of the resource to check
+ *
+ * @returns 0 on success (if access is granted), -EINVAL if access is denied.
+ * Else, returns an appropriate negative ERRNO value
+ */
+int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id);
+
+#endif /* MACH_ETZPC_H*/
diff --git a/arch/arm/mach-stm32mp/include/mach/rif.h b/arch/arm/mach-stm32mp/include/mach/rif.h
new file mode 100644
index 0000000..10b2210
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/rif.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef MACH_RIF_H
+#define MACH_RIF_H
+
+#include <linux/types.h>
+
+/**
+ * stm32_rifsc_check_access - Check RIF accesses for given device node
+ *
+ * @device_node Node of the device for which the accesses are checked
+ */
+int stm32_rifsc_check_access(ofnode device_node);
+
+/**
+ * stm32_rifsc_check_access - Check RIF accesses for given id
+ *
+ * @device_node Node of the device to get a reference on RIFSC
+ * @id ID of the resource to check
+ */
+int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id);
+
+#endif /* MACH_RIF_H*/
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 6eb85ba..a9ac49b 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -42,6 +42,9 @@
BOOT_FLASH_SPINAND = 0x70,
BOOT_FLASH_SPINAND_1 = 0x71,
+
+ BOOT_FLASH_HYPERFLASH = 0x80,
+ BOOT_FLASH_HYPERFLASH_1 = 0x81
};
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
@@ -158,8 +161,20 @@
#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
#ifdef CONFIG_STM32MP25X
+#define STM32_USART2_BASE 0x400E0000
+#define STM32_USART3_BASE 0x400F0000
+#define STM32_UART4_BASE 0x40100000
+#define STM32_UART5_BASE 0x40110000
+#define STM32_USART6_BASE 0x40220000
+#define STM32_UART9_BASE 0x402C0000
+#define STM32_USART1_BASE 0x40330000
+#define STM32_UART7_BASE 0x40370000
+#define STM32_UART8_BASE 0x40380000
#define STM32_RCC_BASE 0x44200000
#define STM32_TAMP_BASE 0x46010000
+#define STM32_SDMMC1_BASE 0x48220000
+#define STM32_SDMMC2_BASE 0x48230000
+#define STM32_SDMMC3_BASE 0x48240000
#define STM32_DDR_BASE 0x80000000
@@ -197,6 +212,7 @@
#ifdef CONFIG_STM32MP25X
#define BSEC_OTP_SERIAL 5
#define BSEC_OTP_RPN 9
+#define BSEC_OTP_REVID 102
#define BSEC_OTP_PKG 122
#define BSEC_OTP_BOARD 246
#define BSEC_OTP_MAC 247
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 2a65efc..1907366 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -58,6 +58,7 @@
/* return CPU_DEV constants */
u32 get_cpu_dev(void);
+/* Silicon revision = REV_ID[15:0] of Device Version */
#define CPU_REV1 0x1000
#define CPU_REV1_1 0x1001
#define CPU_REV1_2 0x1003
@@ -65,7 +66,15 @@
#define CPU_REV2_1 0x2001
#define CPU_REV2_2 0x2003
-/* return Silicon revision = REV_ID[15:0] of Device Version */
+/* OTP revision ID = 6 bits : 3 for Major / 3 for Minor */
+#define OTP_REVID_1 0b001000
+#define OTP_REVID_1_1 0b001001
+#define OTP_REVID_1_2 0b001010
+#define OTP_REVID_2 0b010000
+#define OTP_REVID_2_1 0b010001
+#define OTP_REVID_2_2 0b010010
+
+/* return SoC revision = Silicon revision (STM32MP1) or OTP revision ID (STM32MP2)*/
u32 get_cpu_rev(void);
/* Get Package options from OTP */
@@ -80,9 +89,9 @@
/* package used for STM32MP25x */
#define STM32MP25_PKG_CUSTOM 0
-#define STM32MP25_PKG_AL_TBGA361 3
-#define STM32MP25_PKG_AK_TBGA424 4
-#define STM32MP25_PKG_AI_TBGA436 5
+#define STM32MP25_PKG_AL_VFBGA361 1
+#define STM32MP25_PKG_AK_VFBGA424 3
+#define STM32MP25_PKG_AI_TFBGA436 5
#define STM32MP25_PKG_UNKNOWN 7
/* Get SOC name */
@@ -111,3 +120,10 @@
uintptr_t get_stm32mp_rom_api_table(void);
uintptr_t get_stm32mp_bl2_dtb(void);
+
+/* helper function: check "closed" state in product "Life Cycle" */
+#ifdef CONFIG_CMD_STM32KEY
+bool stm32mp_is_closed(void);
+#else
+static inline bool stm32mp_is_closed(void) { return false; }
+#endif
diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile
index 0df6dab..1f4ada3 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/Makefile
+++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile
@@ -4,6 +4,7 @@
#
obj-y += cpu.o
+obj-y += etzpc.o
obj-$(CONFIG_STM32MP13X) += stm32mp13x.o
obj-$(CONFIG_STM32MP15X) += stm32mp15x.o
diff --git a/arch/arm/mach-stm32mp/stm32mp1/etzpc.c b/arch/arm/mach-stm32mp/stm32mp1/etzpc.c
new file mode 100644
index 0000000..7013bf9
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp1/etzpc.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY UCLASS_NOP
+
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/bitfield.h>
+#include <mach/etzpc.h>
+
+/* ETZPC peripheral as firewall bus */
+/* ETZPC registers */
+#define ETZPC_DECPROT 0x10
+#define ETZPC_HWCFGR 0x3F0
+
+/* ETZPC miscellaneous */
+#define ETZPC_PROT_MASK GENMASK(1, 0)
+#define ETZPC_PROT_A7NS 0x3
+#define ETZPC_DECPROT_SHIFT 1
+
+#define IDS_PER_DECPROT_REGS 16
+
+#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8)
+#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16)
+
+/*
+ * struct stm32_etzpc_plat: Information about ETZPC device
+ *
+ * @base: Base address of ETZPC
+ * @max_entries: Number of securable peripherals in ETZPC
+ */
+struct stm32_etzpc_plat {
+ void *base;
+ unsigned int max_entries;
+};
+
+static int etzpc_parse_feature_domain(ofnode node, struct ofnode_phandle_args *args)
+{
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "access-controllers",
+ "#access-controller-cells", 0,
+ 0, args);
+ if (ret) {
+ log_debug("failed to parse access-controller (%d)\n", ret);
+ return ret;
+ }
+
+ if (args->args_count != 1) {
+ log_debug("invalid domain args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int etzpc_check_access(void *base, u32 id)
+{
+ u32 reg_offset, offset, sec_val;
+
+ /* Check access configuration, 16 peripherals per register */
+ reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+ offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
+
+ /* Verify peripheral is non-secure and attributed to cortex A7 */
+ sec_val = (readl(base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+ if (sec_val != ETZPC_PROT_A7NS) {
+ log_debug("Invalid bus configuration: reg_offset %#x, value %d\n",
+ reg_offset, sec_val);
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id)
+{
+ struct stm32_etzpc_plat *plat;
+ struct ofnode_phandle_args args;
+ struct udevice *dev;
+ int err;
+
+ err = etzpc_parse_feature_domain(device_node, &args);
+ if (err)
+ return err;
+
+ if (id == -1U)
+ id = args.args[0];
+
+ err = uclass_get_device_by_ofnode(UCLASS_NOP, args.node, &dev);
+ if (err || dev->driver != DM_DRIVER_GET(stm32_etzpc)) {
+ log_err("No device found\n");
+ return -EINVAL;
+ }
+
+ plat = dev_get_plat(dev);
+
+ if (id >= plat->max_entries) {
+ dev_err(dev, "Invalid sys bus ID for %s\n", ofnode_get_name(device_node));
+ return -EINVAL;
+ }
+
+ return etzpc_check_access(plat->base, id);
+}
+
+int stm32_etzpc_check_access(ofnode device_node)
+{
+ return stm32_etzpc_check_access_by_id(device_node, -1U);
+}
+
+static int stm32_etzpc_bind(struct udevice *dev)
+{
+ struct stm32_etzpc_plat *plat = dev_get_plat(dev);
+ struct ofnode_phandle_args args;
+ u32 nb_per, nb_master;
+ int ret = 0, err = 0;
+ ofnode node, parent;
+
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base) {
+ dev_err(dev, "can't get registers base address\n");
+ return -ENOENT;
+ }
+
+ /* Get number of etzpc entries*/
+ nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC,
+ readl(plat->base + ETZPC_HWCFGR));
+ nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC,
+ readl(plat->base + ETZPC_HWCFGR));
+ plat->max_entries = nb_per + nb_master;
+
+ parent = dev_ofnode(dev);
+ for (node = ofnode_first_subnode(parent);
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ const char *node_name = ofnode_get_name(node);
+
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ err = etzpc_parse_feature_domain(node, &args);
+ if (err) {
+ dev_err(dev, "%s failed to parse child on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ if (!ofnode_equal(args.node, parent)) {
+ dev_err(dev, "%s phandle to %s\n",
+ node_name, ofnode_get_name(args.node));
+ continue;
+ }
+
+ if (args.args[0] >= plat->max_entries) {
+ dev_err(dev, "Invalid sys bus ID for %s\n", node_name);
+ return -EINVAL;
+ }
+
+ err = etzpc_check_access(plat->base, args.args[0]);
+ if (err) {
+ dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ err = lists_bind_fdt(dev, node, NULL, NULL,
+ gd->flags & GD_FLG_RELOC ? false : true);
+ if (err) {
+ ret = err;
+ dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret);
+ }
+ }
+
+ if (ret)
+ dev_err(dev, "Some child failed to bind (%d)\n", ret);
+
+ return ret;
+}
+
+static const struct udevice_id stm32_etzpc_ids[] = {
+ { .compatible = "st,stm32-etzpc" },
+ {},
+};
+
+U_BOOT_DRIVER(stm32_etzpc) = {
+ .name = "stm32_etzpc",
+ .id = UCLASS_NOP,
+ .of_match = stm32_etzpc_ids,
+ .bind = stm32_etzpc_bind,
+ .plat_auto = sizeof(struct stm32_etzpc_plat),
+};
diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c
index e1e4dc0..72474fa 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/fdt.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c
@@ -14,20 +14,6 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <linux/io.h>
-#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n))
-#define ETZPC_DECPROT_NB 6
-
-#define DECPROT_MASK 0x03
-#define NB_PROT_PER_REG 0x10
-#define DECPROT_NB_BITS 2
-
-#define DECPROT_SECURED 0x00
-#define DECPROT_WRITE_SECURE 0x01
-#define DECPROT_MCU_ISOLATION 0x02
-#define DECPROT_NON_SECURED 0x03
-
-#define ETZPC_RESERVED 0xffffffff
-
#define STM32MP13_FDCAN_BASE 0x4400F000
#define STM32MP13_ADC1_BASE 0x48003000
#define STM32MP13_TSC_BASE 0x5000B000
@@ -42,204 +28,6 @@
#define STM32MP15_GPU_BASE 0x59000000
#define STM32MP15_DSI_BASE 0x5a000000
-static const u32 stm32mp13_ip_addr[] = {
- 0x50025000, /* 0 VREFBUF APB3 */
- 0x50021000, /* 1 LPTIM2 APB3 */
- 0x50022000, /* 2 LPTIM3 APB3 */
- STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
- STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
- 0x5A006000, /* 5 USBPHYCTRL APB4 */
- 0x5A003000, /* 6 DDRCTRLPHY APB4 */
- ETZPC_RESERVED, /* 7 Reserved*/
- ETZPC_RESERVED, /* 8 Reserved*/
- ETZPC_RESERVED, /* 9 Reserved*/
- 0x5C006000, /* 10 TZC APB5 */
- 0x58001000, /* 11 MCE APB5 */
- 0x5C000000, /* 12 IWDG1 APB5 */
- 0x5C008000, /* 13 STGENC APB5 */
- ETZPC_RESERVED, /* 14 Reserved*/
- ETZPC_RESERVED, /* 15 Reserved*/
- 0x4C000000, /* 16 USART1 APB6 */
- 0x4C001000, /* 17 USART2 APB6 */
- 0x4C002000, /* 18 SPI4 APB6 */
- 0x4C003000, /* 19 SPI5 APB6 */
- 0x4C004000, /* 20 I2C3 APB6 */
- 0x4C005000, /* 21 I2C4 APB6 */
- 0x4C006000, /* 22 I2C5 APB6 */
- 0x4C007000, /* 23 TIM12 APB6 */
- 0x4C008000, /* 24 TIM13 APB6 */
- 0x4C009000, /* 25 TIM14 APB6 */
- 0x4C00A000, /* 26 TIM15 APB6 */
- 0x4C00B000, /* 27 TIM16 APB6 */
- 0x4C00C000, /* 28 TIM17 APB6 */
- ETZPC_RESERVED, /* 29 Reserved*/
- ETZPC_RESERVED, /* 30 Reserved*/
- ETZPC_RESERVED, /* 31 Reserved*/
- STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
- 0x48004000, /* 33 ADC2 AHB2 */
- 0x49000000, /* 34 OTG AHB2 */
- ETZPC_RESERVED, /* 35 Reserved*/
- ETZPC_RESERVED, /* 36 Reserved*/
- STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
- ETZPC_RESERVED, /* 38 Reserved*/
- ETZPC_RESERVED, /* 39 Reserved*/
- 0x54004000, /* 40 RNG AHB5 */
- 0x54003000, /* 41 HASH AHB5 */
- STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
- 0x54005000, /* 43 SAES AHB5 */
- 0x54006000, /* 44 PKA AHB5 */
- 0x54000000, /* 45 BKPSRAM AHB5 */
- ETZPC_RESERVED, /* 46 Reserved*/
- ETZPC_RESERVED, /* 47 Reserved*/
- 0x5800A000, /* 48 ETH1 AHB6 */
- STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
- 0x58005000, /* 50 SDMMC1 AHB6 */
- 0x58007000, /* 51 SDMMC2 AHB6 */
- ETZPC_RESERVED, /* 52 Reserved*/
- ETZPC_RESERVED, /* 53 Reserved*/
- 0x58002000, /* 54 FMC AHB6 */
- 0x58003000, /* 55 QSPI AHB6 */
- ETZPC_RESERVED, /* 56 Reserved*/
- ETZPC_RESERVED, /* 57 Reserved*/
- ETZPC_RESERVED, /* 58 Reserved*/
- ETZPC_RESERVED, /* 59 Reserved*/
- 0x30000000, /* 60 SRAM1 MLAHB */
- 0x30004000, /* 61 SRAM2 MLAHB */
- 0x30006000, /* 62 SRAM3 MLAHB */
- ETZPC_RESERVED, /* 63 Reserved*/
- ETZPC_RESERVED, /* 64 Reserved*/
- ETZPC_RESERVED, /* 65 Reserved*/
- ETZPC_RESERVED, /* 66 Reserved*/
- ETZPC_RESERVED, /* 67 Reserved*/
- ETZPC_RESERVED, /* 68 Reserved*/
- ETZPC_RESERVED, /* 69 Reserved*/
- ETZPC_RESERVED, /* 70 Reserved*/
- ETZPC_RESERVED, /* 71 Reserved*/
- ETZPC_RESERVED, /* 72 Reserved*/
- ETZPC_RESERVED, /* 73 Reserved*/
- ETZPC_RESERVED, /* 74 Reserved*/
- ETZPC_RESERVED, /* 75 Reserved*/
- ETZPC_RESERVED, /* 76 Reserved*/
- ETZPC_RESERVED, /* 77 Reserved*/
- ETZPC_RESERVED, /* 78 Reserved*/
- ETZPC_RESERVED, /* 79 Reserved*/
- ETZPC_RESERVED, /* 80 Reserved*/
- ETZPC_RESERVED, /* 81 Reserved*/
- ETZPC_RESERVED, /* 82 Reserved*/
- ETZPC_RESERVED, /* 83 Reserved*/
- ETZPC_RESERVED, /* 84 Reserved*/
- ETZPC_RESERVED, /* 85 Reserved*/
- ETZPC_RESERVED, /* 86 Reserved*/
- ETZPC_RESERVED, /* 87 Reserved*/
- ETZPC_RESERVED, /* 88 Reserved*/
- ETZPC_RESERVED, /* 89 Reserved*/
- ETZPC_RESERVED, /* 90 Reserved*/
- ETZPC_RESERVED, /* 91 Reserved*/
- ETZPC_RESERVED, /* 92 Reserved*/
- ETZPC_RESERVED, /* 93 Reserved*/
- ETZPC_RESERVED, /* 94 Reserved*/
- ETZPC_RESERVED, /* 95 Reserved*/
-};
-
-static const u32 stm32mp15_ip_addr[] = {
- 0x5c008000, /* 00 stgenc */
- 0x54000000, /* 01 bkpsram */
- 0x5c003000, /* 02 iwdg1 */
- 0x5c000000, /* 03 usart1 */
- 0x5c001000, /* 04 spi6 */
- 0x5c002000, /* 05 i2c4 */
- ETZPC_RESERVED, /* 06 reserved */
- 0x54003000, /* 07 rng1 */
- 0x54002000, /* 08 hash1 */
- STM32MP15_CRYP1_BASE, /* 09 cryp1 */
- 0x5a003000, /* 0A ddrctrl */
- 0x5a004000, /* 0B ddrphyc */
- 0x5c009000, /* 0C i2c6 */
- ETZPC_RESERVED, /* 0D reserved */
- ETZPC_RESERVED, /* 0E reserved */
- ETZPC_RESERVED, /* 0F reserved */
- 0x40000000, /* 10 tim2 */
- 0x40001000, /* 11 tim3 */
- 0x40002000, /* 12 tim4 */
- 0x40003000, /* 13 tim5 */
- 0x40004000, /* 14 tim6 */
- 0x40005000, /* 15 tim7 */
- 0x40006000, /* 16 tim12 */
- 0x40007000, /* 17 tim13 */
- 0x40008000, /* 18 tim14 */
- 0x40009000, /* 19 lptim1 */
- 0x4000a000, /* 1A wwdg1 */
- 0x4000b000, /* 1B spi2 */
- 0x4000c000, /* 1C spi3 */
- 0x4000d000, /* 1D spdifrx */
- 0x4000e000, /* 1E usart2 */
- 0x4000f000, /* 1F usart3 */
- 0x40010000, /* 20 uart4 */
- 0x40011000, /* 21 uart5 */
- 0x40012000, /* 22 i2c1 */
- 0x40013000, /* 23 i2c2 */
- 0x40014000, /* 24 i2c3 */
- 0x40015000, /* 25 i2c5 */
- 0x40016000, /* 26 cec */
- 0x40017000, /* 27 dac */
- 0x40018000, /* 28 uart7 */
- 0x40019000, /* 29 uart8 */
- ETZPC_RESERVED, /* 2A reserved */
- ETZPC_RESERVED, /* 2B reserved */
- 0x4001c000, /* 2C mdios */
- ETZPC_RESERVED, /* 2D reserved */
- ETZPC_RESERVED, /* 2E reserved */
- ETZPC_RESERVED, /* 2F reserved */
- 0x44000000, /* 30 tim1 */
- 0x44001000, /* 31 tim8 */
- ETZPC_RESERVED, /* 32 reserved */
- 0x44003000, /* 33 usart6 */
- 0x44004000, /* 34 spi1 */
- 0x44005000, /* 35 spi4 */
- 0x44006000, /* 36 tim15 */
- 0x44007000, /* 37 tim16 */
- 0x44008000, /* 38 tim17 */
- 0x44009000, /* 39 spi5 */
- 0x4400a000, /* 3A sai1 */
- 0x4400b000, /* 3B sai2 */
- 0x4400c000, /* 3C sai3 */
- 0x4400d000, /* 3D dfsdm */
- STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
- ETZPC_RESERVED, /* 3F reserved */
- 0x50021000, /* 40 lptim2 */
- 0x50022000, /* 41 lptim3 */
- 0x50023000, /* 42 lptim4 */
- 0x50024000, /* 43 lptim5 */
- 0x50027000, /* 44 sai4 */
- 0x50025000, /* 45 vrefbuf */
- 0x4c006000, /* 46 dcmi */
- 0x4c004000, /* 47 crc2 */
- 0x48003000, /* 48 adc */
- 0x4c002000, /* 49 hash2 */
- 0x4c003000, /* 4A rng2 */
- STM32MP15_CRYP2_BASE, /* 4B cryp2 */
- ETZPC_RESERVED, /* 4C reserved */
- ETZPC_RESERVED, /* 4D reserved */
- ETZPC_RESERVED, /* 4E reserved */
- ETZPC_RESERVED, /* 4F reserved */
- ETZPC_RESERVED, /* 50 sram1 */
- ETZPC_RESERVED, /* 51 sram2 */
- ETZPC_RESERVED, /* 52 sram3 */
- ETZPC_RESERVED, /* 53 sram4 */
- ETZPC_RESERVED, /* 54 retram */
- 0x49000000, /* 55 otg */
- 0x48004000, /* 56 sdmmc3 */
- 0x48005000, /* 57 dlybsd3 */
- 0x48000000, /* 58 dma1 */
- 0x48001000, /* 59 dma2 */
- 0x48002000, /* 5A dmamux */
- 0x58002000, /* 5B fmc */
- 0x58003000, /* 5C qspi */
- 0x58004000, /* 5D dlybq */
- 0x5800a000, /* 5E eth */
- ETZPC_RESERVED, /* 5F reserved */
-};
-
/* fdt helper */
static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
{
@@ -263,46 +51,6 @@
return false;
}
-static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
-{
- const u32 *array;
- int array_size, i;
- int offset, shift;
- u32 addr, status, decprot[ETZPC_DECPROT_NB];
-
- if (IS_ENABLED(CONFIG_STM32MP13X)) {
- array = stm32mp13_ip_addr;
- array_size = ARRAY_SIZE(stm32mp13_ip_addr);
- }
-
- if (IS_ENABLED(CONFIG_STM32MP15X)) {
- array = stm32mp15_ip_addr;
- array_size = ARRAY_SIZE(stm32mp15_ip_addr);
- }
-
- for (i = 0; i < ETZPC_DECPROT_NB; i++)
- decprot[i] = readl(ETZPC_DECPROT(i));
-
- for (i = 0; i < array_size; i++) {
- offset = i / NB_PROT_PER_REG;
- shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
- status = (decprot[offset] >> shift) & DECPROT_MASK;
- addr = array[i];
-
- log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
-
- if (addr == ETZPC_RESERVED ||
- status == DECPROT_NON_SECURED)
- continue;
-
- if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
- log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
- addr, i, status);
- }
-
- return 0;
-}
-
/* deactivate all the cpu except core 0 */
static void stm32_fdt_fixup_cpu(void *blob, char *name)
{
@@ -481,12 +229,6 @@
if (soc < 0)
return soc;
- if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
- ret = stm32_fdt_fixup_etzpc(blob, soc);
- if (ret)
- return ret;
- }
-
/* MPUs Part Numbers and name*/
cpu = get_cpu_type();
get_soc_name(name);
diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile
index b579ce5..5dbf75d 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/Makefile
+++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile
@@ -5,5 +5,6 @@
obj-y += cpu.o
obj-y += arm64-mmu.o
+obj-y += rifsc.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
index 9530aa8..c3b87d7 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c
@@ -24,7 +24,7 @@
* early TLB into the .data section so that it not get cleared
* with 16kB alignment
*/
-#define EARLY_TLB_SIZE 0xA000
+#define EARLY_TLB_SIZE 0x10000
u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
/*
@@ -55,6 +55,19 @@
return 0;
}
+int mach_cpu_init(void)
+{
+ u32 boot_mode;
+
+ boot_mode = get_bootmode();
+
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
+ (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+
+ return 0;
+}
+
void enable_caches(void)
{
/* deactivate the data cache, early enabled in arch_cpu_init() */
@@ -67,14 +80,6 @@
dcache_enable();
}
-int arch_misc_init(void)
-{
- setup_serial_number();
- setup_mac_address();
-
- return 0;
-}
-
/*
* Force data-section, as .bss will not be valid
* when save_boot_params is invoked.
@@ -97,3 +102,150 @@
save_boot_params_ret();
}
+
+u32 get_bootmode(void)
+{
+ /* read bootmode from TAMP backup register */
+ return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
+ TAMP_BOOT_MODE_SHIFT;
+}
+
+static void setup_boot_mode(void)
+{
+ const u32 serial_addr[] = {
+ STM32_USART1_BASE,
+ STM32_USART2_BASE,
+ STM32_USART3_BASE,
+ STM32_UART4_BASE,
+ STM32_UART5_BASE,
+ STM32_USART6_BASE,
+ STM32_UART7_BASE,
+ STM32_UART8_BASE,
+ STM32_UART9_BASE
+ };
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
+ char cmd[60];
+ u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
+ u32 boot_mode =
+ (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
+ unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
+ struct udevice *dev;
+
+ log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
+ __func__, boot_ctx, boot_mode, instance, forced_mode);
+ switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
+ case BOOT_SERIAL_UART:
+ if (instance > ARRAY_SIZE(serial_addr))
+ break;
+ /* serial : search associated node in devicetree */
+ sprintf(cmd, "serial@%x", serial_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
+ /* restore console on error */
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
+ gd->flags &= ~(GD_FLG_SILENT |
+ GD_FLG_DISABLE_CONSOLE);
+ log_err("uart%d = %s not found in device tree!\n",
+ instance + 1, cmd);
+ break;
+ }
+ sprintf(cmd, "%d", dev_seq(dev));
+ env_set("boot_device", "serial");
+ env_set("boot_instance", cmd);
+
+ /* restore console on uart when not used */
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
+ gd->flags &= ~(GD_FLG_SILENT |
+ GD_FLG_DISABLE_CONSOLE);
+ log_info("serial boot with console enabled!\n");
+ }
+ break;
+ case BOOT_SERIAL_USB:
+ env_set("boot_device", "usb");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_SD:
+ case BOOT_FLASH_EMMC:
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ break;
+ /* search associated sdmmc node in devicetree */
+ sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ printf("mmc%d = %s not found in device tree!\n",
+ instance, cmd);
+ break;
+ }
+ sprintf(cmd, "%d", dev_seq(dev));
+ env_set("boot_device", "mmc");
+ env_set("boot_instance", cmd);
+ break;
+ case BOOT_FLASH_NAND:
+ env_set("boot_device", "nand");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_SPINAND:
+ env_set("boot_device", "spi-nand");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_NOR:
+ env_set("boot_device", "nor");
+ if (IS_ENABLED(CONFIG_SYS_MAX_FLASH_BANKS))
+ sprintf(cmd, "%d", CONFIG_SYS_MAX_FLASH_BANKS);
+ else
+ sprintf(cmd, "%d", 0);
+ env_set("boot_instance", cmd);
+ break;
+ case BOOT_FLASH_HYPERFLASH:
+ env_set("boot_device", "nor");
+ env_set("boot_instance", "0");
+ break;
+ default:
+ env_set("boot_device", "invalid");
+ env_set("boot_instance", "");
+ log_err("unexpected boot mode = %x\n", boot_mode);
+ break;
+ }
+
+ switch (forced_mode) {
+ case BOOT_FASTBOOT:
+ log_info("Enter fastboot!\n");
+ env_set("preboot", "env set preboot; fastboot 0");
+ break;
+ case BOOT_STM32PROG:
+ env_set("boot_device", "usb");
+ env_set("boot_instance", "0");
+ break;
+ case BOOT_UMS_MMC0:
+ case BOOT_UMS_MMC1:
+ case BOOT_UMS_MMC2:
+ log_info("Enter UMS!\n");
+ instance = forced_mode - BOOT_UMS_MMC0;
+ sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
+ env_set("preboot", cmd);
+ break;
+ case BOOT_RECOVERY:
+ env_set("preboot", "env set preboot; run altbootcmd");
+ break;
+ case BOOT_NORMAL:
+ break;
+ default:
+ log_debug("unexpected forced boot mode = %x\n", forced_mode);
+ break;
+ }
+
+ /* clear TAMP for next reboot */
+ clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
+}
+
+int arch_misc_init(void)
+{
+ setup_boot_mode();
+ setup_serial_number();
+ setup_mac_address();
+
+ return 0;
+}
diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c
new file mode 100644
index 0000000..50decec
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY UCLASS_NOP
+
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/bitfield.h>
+#include <mach/rif.h>
+
+/* RIFSC offset register */
+#define RIFSC_RISC_SECCFGR0(id) (0x10 + 0x4 * (id))
+#define RIFSC_RISC_PER0_CIDCFGR(id) (0x100 + 0x8 * (id))
+#define RIFSC_RISC_PER0_SEMCR(id) (0x104 + 0x8 * (id))
+
+/*
+ * SEMCR register
+ */
+#define SEMCR_MUTEX BIT(0)
+
+/* RIFSC miscellaneous */
+#define RIFSC_RISC_SCID_MASK GENMASK(6, 4)
+#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16)
+
+#define IDS_PER_RISC_SEC_PRIV_REGS 32
+
+/*
+ * CIDCFGR register fields
+ */
+#define CIDCFGR_CFEN BIT(0)
+#define CIDCFGR_SEMEN BIT(1)
+
+#define SEMWL_SHIFT 16
+
+#define STM32MP25_RIFSC_ENTRIES 178
+
+/* Compartiment IDs */
+#define RIF_CID0 0x0
+#define RIF_CID1 0x1
+
+/*
+ * struct stm32_rifsc_plat: Information about RIFSC device
+ *
+ * @base: Base address of RIFSC
+ */
+struct stm32_rifsc_plat {
+ void *base;
+};
+
+/*
+ * struct stm32_rifsc_child_plat: Information about each child
+ *
+ * @domain_id: Domain id
+ */
+struct stm32_rifsc_child_plat {
+ u32 domain_id;
+};
+
+static bool stm32_rif_is_semaphore_available(void *base, u32 id)
+{
+ void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
+
+ return !(readl(addr) & SEMCR_MUTEX);
+}
+
+static int stm32_rif_acquire_semaphore(void *base, u32 id)
+{
+ void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
+
+ /* Check that the semaphore is available */
+ if (!stm32_rif_is_semaphore_available(base, id))
+ return -EACCES;
+
+ setbits_le32(addr, SEMCR_MUTEX);
+
+ /* Check that CID1 has the semaphore */
+ if (stm32_rif_is_semaphore_available(base, id) ||
+ FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1))
+ return -EACCES;
+
+ return 0;
+}
+
+static int stm32_rif_release_semaphore(void *base, u32 id)
+{
+ void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
+
+ if (stm32_rif_is_semaphore_available(base, id))
+ return 0;
+
+ clrbits_le32(addr, SEMCR_MUTEX);
+
+ /* Ok if another compartment takes the semaphore before the check */
+ if (!stm32_rif_is_semaphore_available(base, id) &&
+ FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1))
+ return -EACCES;
+
+ return 0;
+}
+
+static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args)
+{
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "access-controllers",
+ "#access-controller-cells", 0,
+ 0, args);
+ if (ret) {
+ log_debug("failed to parse access-controller (%d)\n", ret);
+ return ret;
+ }
+
+ if (args->args_count != 1) {
+ log_debug("invalid domain args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args[0] >= STM32MP25_RIFSC_ENTRIES) {
+ log_err("Invalid sys bus ID for %s\n", ofnode_get_name(node));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rifsc_check_access(void *base, u32 id)
+{
+ u32 reg_offset, reg_id, sec_reg_value, cid_reg_value, sem_reg_value;
+
+ /*
+ * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for
+ * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register
+ * per peripheral
+ */
+ reg_id = id / IDS_PER_RISC_SEC_PRIV_REGS;
+ reg_offset = id % IDS_PER_RISC_SEC_PRIV_REGS;
+ sec_reg_value = readl(base + RIFSC_RISC_SECCFGR0(reg_id));
+ cid_reg_value = readl(base + RIFSC_RISC_PER0_CIDCFGR(id));
+ sem_reg_value = readl(base + RIFSC_RISC_PER0_SEMCR(id));
+
+ /*
+ * First check conditions for semaphore mode, which doesn't take into
+ * account static CID.
+ */
+ if (cid_reg_value & CIDCFGR_SEMEN)
+ goto skip_cid_check;
+
+ /*
+ * Skip cid check if CID filtering isn't enabled or filtering is enabled on CID0, which
+ * corresponds to whatever CID.
+ */
+ if (!(cid_reg_value & CIDCFGR_CFEN) ||
+ FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0)
+ goto skip_cid_check;
+
+ /* Coherency check with the CID configuration */
+ if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
+ log_debug("Invalid CID configuration for peripheral %d\n", id);
+ return -EACCES;
+ }
+
+ /* Check semaphore accesses */
+ if (cid_reg_value & CIDCFGR_SEMEN) {
+ if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
+ log_debug("Not in semaphore whitelist for peripheral %d\n", id);
+ return -EACCES;
+ }
+ if (!stm32_rif_is_semaphore_available(base, id) &&
+ !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) {
+ log_debug("Semaphore unavailable for peripheral %d\n", id);
+ return -EACCES;
+ }
+ }
+
+skip_cid_check:
+ /* Check security configuration */
+ if (sec_reg_value & BIT(reg_offset)) {
+ log_debug("Invalid security configuration for peripheral %d\n", id);
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id)
+{
+ struct ofnode_phandle_args args;
+ int err;
+
+ if (id >= STM32MP25_RIFSC_ENTRIES)
+ return -EINVAL;
+
+ err = rifsc_parse_access_controller(device_node, &args);
+ if (err)
+ return err;
+
+ return rifsc_check_access((void *)ofnode_get_addr(args.node), id);
+}
+
+int stm32_rifsc_check_access(ofnode device_node)
+{
+ struct ofnode_phandle_args args;
+ int err;
+
+ err = rifsc_parse_access_controller(device_node, &args);
+ if (err)
+ return err;
+
+ return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]);
+}
+
+static int stm32_rifsc_child_pre_probe(struct udevice *dev)
+{
+ struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
+ struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+ u32 cid_reg_value;
+ int err;
+ u32 id = child_plat->domain_id;
+
+ cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
+
+ /*
+ * If the peripheral is in semaphore mode, take the semaphore so that
+ * the CID1 has the ownership.
+ */
+ if (cid_reg_value & CIDCFGR_SEMEN &&
+ (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
+ err = stm32_rif_acquire_semaphore(plat->base, id);
+ if (err) {
+ dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n",
+ id, err);
+ return err;
+ }
+ dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id);
+ }
+
+ return 0;
+}
+
+static int stm32_rifsc_child_post_remove(struct udevice *dev)
+{
+ struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
+ struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+ u32 cid_reg_value;
+ int err;
+ u32 id = child_plat->domain_id;
+
+ cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
+
+ /*
+ * If the peripheral is in semaphore mode, release the semaphore so that
+ * there's no ownership.
+ */
+ if (cid_reg_value & CIDCFGR_SEMEN &&
+ (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
+ err = stm32_rif_release_semaphore(plat->base, id);
+ if (err)
+ dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n",
+ id, err);
+ }
+
+ return 0;
+}
+
+static int stm32_rifsc_child_post_bind(struct udevice *dev)
+{
+ struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+ struct ofnode_phandle_args args;
+ int ret;
+
+ if (!dev_has_ofnode(dev))
+ return -EPERM;
+
+ ret = rifsc_parse_access_controller(dev_ofnode(dev), &args);
+ if (ret)
+ return ret;
+
+ child_plat->domain_id = args.args[0];
+
+ return 0;
+}
+
+static int stm32_rifsc_bind(struct udevice *dev)
+{
+ struct stm32_rifsc_plat *plat = dev_get_plat(dev);
+ struct ofnode_phandle_args args;
+ int ret = 0, err = 0;
+ ofnode node;
+
+ plat->base = dev_read_addr_ptr(dev);
+ if (!plat->base) {
+ dev_err(dev, "can't get registers base address\n");
+ return -ENOENT;
+ }
+
+ for (node = ofnode_first_subnode(dev_ofnode(dev));
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ const char *node_name = ofnode_get_name(node);
+
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ err = rifsc_parse_access_controller(node, &args);
+ if (err) {
+ dev_dbg(dev, "%s failed to parse child on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ err = rifsc_check_access(plat->base, args.args[0]);
+ if (err) {
+ dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err);
+ continue;
+ }
+
+ err = lists_bind_fdt(dev, node, NULL, NULL,
+ gd->flags & GD_FLG_RELOC ? false : true);
+ if (err && !ret) {
+ ret = err;
+ dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret);
+ }
+ }
+
+ if (ret)
+ dev_err(dev, "Some child failed to bind (%d)\n", ret);
+
+ return ret;
+}
+
+static int stm32_rifsc_remove(struct udevice *bus)
+{
+ struct udevice *dev;
+
+ /* Deactivate all child devices not yet removed */
+ for (device_find_first_child(bus, &dev); dev; device_find_next_child(&dev))
+ if (device_active(dev))
+ stm32_rifsc_child_post_remove(dev);
+
+ return 0;
+}
+
+static const struct udevice_id stm32_rifsc_ids[] = {
+ { .compatible = "st,stm32mp25-rifsc" },
+ {},
+};
+
+U_BOOT_DRIVER(stm32_rifsc) = {
+ .name = "stm32_rifsc",
+ .id = UCLASS_NOP,
+ .of_match = stm32_rifsc_ids,
+ .bind = stm32_rifsc_bind,
+ .remove = stm32_rifsc_remove,
+ .child_post_bind = stm32_rifsc_child_post_bind,
+ .child_pre_probe = stm32_rifsc_child_pre_probe,
+ .child_post_remove = stm32_rifsc_child_post_remove,
+ .plat_auto = sizeof(struct stm32_rifsc_plat),
+ .per_child_plat_auto = sizeof(struct stm32_rifsc_child_plat),
+ .flags = DM_FLAG_OS_PREPARE,
+};
diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
index 7f896a0..12b43ea 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
+++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c
@@ -15,8 +15,10 @@
#define SYSCFG_DEVICEID_OFFSET 0x6400
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
-#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
-#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
+
+/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
+#define REVID_SHIFT 0
+#define REVID_MASK GENMASK(5, 0)
/* Device Part Number (RPN) = OTP9 */
#define RPN_SHIFT 0
@@ -24,8 +26,8 @@
/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
* - 000: Custom package
- * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
- * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
+ * - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm
+ * - 011: VFBGA424 => AK = 14x14, 424 balls pith 0.5mm
* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
* - others: Reserved
*/
@@ -46,7 +48,7 @@
u32 get_cpu_rev(void)
{
- return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
+ return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
}
/* Get Device Part Number (RPN) from OTP */
@@ -164,12 +166,21 @@
}
/* REVISION */
switch (get_cpu_rev()) {
- case CPU_REV1:
+ case OTP_REVID_1:
cpu_r = "A";
break;
+ case OTP_REVID_1_1:
+ cpu_r = "Z";
+ break;
- case CPU_REV2:
+ case OTP_REVID_2:
cpu_r = "B";
break;
+ case OTP_REVID_2_1:
+ cpu_r = "Y";
+ break;
+ case OTP_REVID_2_2:
+ cpu_r = "X";
+ break;
default:
break;
}
@@ -178,13 +189,13 @@
case STM32MP25_PKG_CUSTOM:
package = "XX";
break;
- case STM32MP25_PKG_AL_TBGA361:
+ case STM32MP25_PKG_AL_VFBGA361:
package = "AL";
break;
- case STM32MP25_PKG_AK_TBGA424:
+ case STM32MP25_PKG_AK_VFBGA424:
package = "AK";
break;
- case STM32MP25_PKG_AI_TBGA436:
+ case STM32MP25_PKG_AI_TFBGA436:
package = "AI";
break;
default:
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ab43239..1717959 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -782,49 +782,6 @@
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
-config USB0_VBUS_PIN
- string "Vbus enable pin for usb0 (otg)"
- default ""
- ---help---
- Set the Vbus enable pin for usb0 (otg). This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_VBUS_DET
- string "Vbus detect pin for usb0 (otg)"
- default ""
- ---help---
- Set the Vbus detect pin for usb0 (otg). This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_ID_DET
- string "ID detect pin for usb0 (otg)"
- default ""
- ---help---
- Set the ID detect pin for usb0 (otg). This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB1_VBUS_PIN
- string "Vbus enable pin for usb1 (ehci0)"
- default "PH6" if MACH_SUN4I || MACH_SUN7I
- default "PH27" if MACH_SUN6I
- ---help---
- Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
- a string in the format understood by sunxi_name_to_gpio, e.g.
- PH1 for pin 1 of port H.
-
-config USB2_VBUS_PIN
- string "Vbus enable pin for usb2 (ehci1)"
- default "PH3" if MACH_SUN4I || MACH_SUN7I
- default "PH24" if MACH_SUN6I
- ---help---
- See USB1_VBUS_PIN help text.
-
-config USB3_VBUS_PIN
- string "Vbus enable pin for usb3 (ehci2)"
- default ""
- ---help---
- See USB1_VBUS_PIN help text.
-
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
@@ -879,6 +836,7 @@
depends on !SUNXI_GEN_NCAT2
select VIDEO
select DISPLAY
+ imply VIDEO_DAMAGE
imply VIDEO_DT_SIMPLEFB
default y
---help---
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index eb6a491..a33cd5b 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -41,8 +41,8 @@
obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
-obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o
+obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o dram_dw_helpers.o
obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/
-obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o
+obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o dram_dw_helpers.o
obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/
endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 701899e..b1bf51f 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -35,6 +35,9 @@
uint32_t cpsr;
uint32_t sctlr;
uint32_t vbar;
+ uint32_t sp_irq;
+ uint32_t icc_pmr;
+ uint32_t icc_igrpen1;
};
struct fel_stash fel_stash __section(".data");
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 359513d..4c522f6 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -6,86 +6,83 @@
#ifdef CONFIG_XPL_BUILD
void clock_init_safe(void)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
/* this seems to enable PLLs on H616 */
- setbits_le32(&prcm->sys_pwroff_gating, 0x10);
- setbits_le32(&prcm->res_cal_ctrl, 2);
+ setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x10);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 2);
}
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
- clrbits_le32(&prcm->res_cal_ctrl, 1);
- setbits_le32(&prcm->res_cal_ctrl, 1);
+ clrbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1);
}
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
/* set key field for ldo enable */
- setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000);
+ setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0xA7000000);
/* set PLL VDD LDO output to 1.14 V */
- setbits_le32(&prcm->pll_ldo_cfg, 0x60000);
+ setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0x60000);
}
clock_set_pll1(408000000);
- writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
- while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
+ writel(CCM_PLL6_DEFAULT, ccm + CCU_H6_PLL6_CFG);
+ while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL6_LOCK))
;
- clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
+ clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG,
+ CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
CCM_CPU_AXI_DEFAULT_FACTORS);
- writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+ writel(CCM_PSI_AHB1_AHB2_DEFAULT, ccm + CCU_H6_PSI_AHB1_AHB2_CFG);
#ifdef CCM_AHB3_DEFAULT
- writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+ writel(CCM_AHB3_DEFAULT, ccm + CCU_H6_AHB3_CFG);
#endif
- writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
+ writel(CCM_APB1_DEFAULT, ccm + CCU_H6_APB1_CFG);
/*
* The mux and factor are set, but the clock will be enabled in
* DRAM initialization code.
*/
- writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
+ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), ccm + CCU_H6_MBUS_CFG);
}
void clock_init_uart(void)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
APB2_CLK_RATE_M(1),
- &ccm->apb2_cfg);
+ ccm + CCU_H6_APB2_CFG);
/* open the clock for uart */
- setbits_le32(&ccm->uart_gate_reset,
+ setbits_le32(ccm + CCU_H6_UART_GATE_RESET,
1 << (CONFIG_CONS_INDEX - 1));
/* deassert uart reset */
- setbits_le32(&ccm->uart_gate_reset,
+ setbits_le32(ccm + CCU_H6_UART_GATE_RESET,
1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
}
void clock_set_pll1(unsigned int clk)
{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
u32 val;
/* Do not support clocks < 288MHz as they need factor P */
if (clk < 288000000) clk = 288000000;
/* Switch to 24MHz clock while changing PLL1 */
- val = readl(&ccm->cpu_axi_cfg);
+ val = readl(ccm + CCU_H6_CPU_AXI_CFG);
val &= ~CCM_CPU_AXI_MUX_MASK;
val |= CCM_CPU_AXI_MUX_OSC24M;
- writel(val, &ccm->cpu_axi_cfg);
+ writel(val, ccm + CCU_H6_CPU_AXI_CFG);
/* clk = 24*n/p, p is ignored if clock is >288MHz */
val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
@@ -94,22 +91,20 @@
val |= CCM_PLL1_OUT_EN;
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
- writel(val, &ccm->pll1_cfg);
- while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
+ writel(val, ccm + CCU_H6_PLL1_CFG);
+ while (!(readl(ccm + CCU_H6_PLL1_CFG) & CCM_PLL1_LOCK)) {}
/* Switch CPU to PLL1 */
- val = readl(&ccm->cpu_axi_cfg);
+ val = readl(ccm + CCU_H6_CPU_AXI_CFG);
val &= ~CCM_CPU_AXI_MUX_MASK;
val |= CCM_CPU_AXI_MUX_PLL_CPUX;
- writel(val, &ccm->cpu_axi_cfg);
+ writel(val, ccm + CCU_H6_CPU_AXI_CFG);
}
int clock_twi_onoff(int port, int state)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const ccm = (void *)SUNXI_CCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
u32 value, *ptr;
int shift;
@@ -117,10 +112,10 @@
if (port == 5) {
shift = 0;
- ptr = &prcm->twi_gate_reset;
+ ptr = prcm + CCU_PRCM_I2C_GATE_RESET;
} else {
shift = port;
- ptr = &ccm->twi_gate_reset;
+ ptr = ccm + CCU_H6_I2C_GATE_RESET;
}
/* set the apb clock gate and reset for twi */
@@ -136,9 +131,8 @@
/* PLL_PERIPH0 clock, used by the MMC driver */
unsigned int clock_get_pll6(void)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- uint32_t rval = readl(&ccm->pll6_cfg);
+ void *const ccm = (void *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(ccm + CCU_H6_PLL6_CFG);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c
new file mode 100644
index 0000000..2476735
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_dw_helpers.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Helpers that are commonly used with DW memory controller.
+ *
+ * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com>
+ *
+ */
+
+#include <init.h>
+#include <asm/arch/dram_dw_helpers.h>
+
+void mctl_auto_detect_rank_width(const struct dram_para *para,
+ struct dram_config *config)
+{
+ /* this is minimum size that it's supported */
+ config->cols = 8;
+ config->rows = 13;
+
+ /*
+ * Strategy here is to test most demanding combination first and least
+ * demanding last, otherwise HW might not be fully utilized. For
+ * example, half bus width and rank = 1 combination would also work
+ * on HW with full bus width and rank = 2, but only 1/4 RAM would be
+ * visible.
+ */
+
+ debug("testing 32-bit width, rank = 2\n");
+ config->bus_full_width = 1;
+ config->ranks = 2;
+ if (mctl_core_init(para, config))
+ return;
+
+ debug("testing 32-bit width, rank = 1\n");
+ config->bus_full_width = 1;
+ config->ranks = 1;
+ if (mctl_core_init(para, config))
+ return;
+
+ debug("testing 16-bit width, rank = 2\n");
+ config->bus_full_width = 0;
+ config->ranks = 2;
+ if (mctl_core_init(para, config))
+ return;
+
+ debug("testing 16-bit width, rank = 1\n");
+ config->bus_full_width = 0;
+ config->ranks = 1;
+ if (mctl_core_init(para, config))
+ return;
+
+ panic("This DRAM setup is currently not supported.\n");
+}
+
+static void mctl_write_pattern(void)
+{
+ unsigned int i;
+ u32 *ptr, val;
+
+ ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i < 16; ptr++, i++) {
+ if (i & 1)
+ val = ~(ulong)ptr;
+ else
+ val = (ulong)ptr;
+ writel(val, ptr);
+ }
+}
+
+static bool mctl_check_pattern(ulong offset)
+{
+ unsigned int i;
+ u32 *ptr, val;
+
+ ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i < 16; ptr++, i++) {
+ if (i & 1)
+ val = ~(ulong)ptr;
+ else
+ val = (ulong)ptr;
+ if (val != *(ptr + offset / 4))
+ return false;
+ }
+
+ return true;
+}
+
+void mctl_auto_detect_dram_size(const struct dram_para *para,
+ struct dram_config *config)
+{
+ unsigned int shift, cols, rows;
+ u32 buffer[16];
+
+ /* max. config for columns, but not rows */
+ config->cols = 11;
+ config->rows = 13;
+ mctl_core_init(para, config);
+
+ /*
+ * Store content so it can be restored later. This is important
+ * if controller was already initialized and holds any data
+ * which is important for restoring system.
+ */
+ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+ mctl_write_pattern();
+
+ shift = config->bus_full_width + 1;
+
+ /* detect column address bits */
+ for (cols = 8; cols < 11; cols++) {
+ if (mctl_check_pattern(1ULL << (cols + shift)))
+ break;
+ }
+ debug("detected %u columns\n", cols);
+
+ /* restore data */
+ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
+
+ /* reconfigure to make sure that all active rows are accessible */
+ config->cols = 8;
+ config->rows = 17;
+ mctl_core_init(para, config);
+
+ /* store data again as it might be moved */
+ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+ mctl_write_pattern();
+
+ /* detect row address bits */
+ shift = config->bus_full_width + 4 + config->cols;
+ for (rows = 13; rows < 17; rows++) {
+ if (mctl_check_pattern(1ULL << (rows + shift)))
+ break;
+ }
+ debug("detected %u rows\n", rows);
+
+ /* restore data again */
+ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
+
+ config->cols = cols;
+ config->rows = rows;
+}
+
+unsigned long mctl_calc_size(const struct dram_config *config)
+{
+ u8 width = config->bus_full_width ? 4 : 2;
+
+ /* 8 banks */
+ return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks;
+}
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index e7862bd..84fd64a 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
+#include <asm/arch/dram_dw_helpers.h>
#include <asm/arch/cpu.h>
#include <asm/arch/prcm.h>
#include <linux/bitops.h>
@@ -34,23 +35,26 @@
* similar PHY is ZynqMP.
*/
-static void mctl_sys_init(struct dram_para *para);
-static void mctl_com_init(struct dram_para *para);
-static bool mctl_channel_init(struct dram_para *para);
+static void mctl_sys_init(u32 clk_rate);
+static void mctl_com_init(const struct dram_para *para,
+ const struct dram_config *config);
+static bool mctl_channel_init(const struct dram_para *para,
+ const struct dram_config *config);
-static bool mctl_core_init(struct dram_para *para)
+bool mctl_core_init(const struct dram_para *para,
+ const struct dram_config *config)
{
- mctl_sys_init(para);
- mctl_com_init(para);
+ mctl_sys_init(para->clk);
+ mctl_com_init(para, config);
switch (para->type) {
case SUNXI_DRAM_TYPE_LPDDR3:
case SUNXI_DRAM_TYPE_DDR3:
- mctl_set_timing_params(para);
+ mctl_set_timing_params();
break;
default:
panic("Unsupported DRAM type!");
};
- return mctl_channel_init(para);
+ return mctl_channel_init(para, config);
}
/* PHY initialisation */
@@ -150,36 +154,36 @@
MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
}
-static void mctl_sys_init(struct dram_para *para)
+static void mctl_sys_init(u32 clk_rate)
{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void * const ccm = (void *)SUNXI_CCM_BASE;
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
/* Put all DRAM-related blocks to reset state */
- clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
- clrbits_le32(&ccm->dram_gate_reset, BIT(0));
+ clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE | MBUS_RESET);
+ clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0));
udelay(5);
- writel(0, &ccm->dram_gate_reset);
- clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
- clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ writel(0, ccm + CCU_H6_DRAM_GATE_RESET);
+ clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN);
+ clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Set PLL5 rate to doubled DRAM clock rate */
writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
- CCM_PLL5_CTRL_N(para->clk * 2 / 24), &ccm->pll5_cfg);
- mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+ CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG);
+ mctl_await_completion(ccm + CCU_H6_PLL5_CFG,
+ CCM_PLL5_LOCK, CCM_PLL5_LOCK);
/* Configure DRAM mod clock */
- writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
- setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
- writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
+ writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG);
+ setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_CLK_UPDATE);
+ writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET);
udelay(5);
- setbits_le32(&ccm->dram_gate_reset, BIT(0));
+ setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0));
/* Disable all channels */
writel(0, &mctl_com->maer0);
@@ -187,24 +191,24 @@
writel(0, &mctl_com->maer2);
/* Configure MBUS and enable DRAM mod reset */
- setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
- setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
- setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE);
+ setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Unknown hack from the BSP, which enables access of mctl_ctl regs */
writel(0x8000, &mctl_ctl->unk_0x00c);
}
-static void mctl_set_addrmap(struct dram_para *para)
+static void mctl_set_addrmap(const struct dram_config *config)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- u8 cols = para->cols;
- u8 rows = para->rows;
- u8 ranks = para->ranks;
+ u8 cols = config->cols;
+ u8 rows = config->rows;
+ u8 ranks = config->ranks;
- if (!para->bus_full_width)
+ if (!config->bus_full_width)
cols -= 1;
/* Ranks */
@@ -282,7 +286,8 @@
mctl_ctl->addrmap[8] = 0x3F3F;
}
-static void mctl_com_init(struct dram_para *para)
+static void mctl_com_init(const struct dram_para *para,
+ const struct dram_config *config)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -292,7 +297,7 @@
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
u32 reg_val, tmp;
- mctl_set_addrmap(para);
+ mctl_set_addrmap(config);
setbits_le32(&mctl_com->cr, BIT(31));
@@ -311,12 +316,12 @@
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
/* TODO: DDR4 */
- reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
+ reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(config->ranks);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
reg_val |= MSTR_DEVICETYPE_LPDDR3;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
- if (para->bus_full_width)
+ if (config->bus_full_width)
reg_val |= MSTR_BUSWIDTH_FULL;
else
reg_val |= MSTR_BUSWIDTH_HALF;
@@ -328,7 +333,7 @@
reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
writel(reg_val | 0x400, &mctl_phy->dcr);
- if (para->ranks == 2)
+ if (config->ranks == 2)
writel(0x0303, &mctl_ctl->odtmap);
else
writel(0x0201, &mctl_ctl->odtmap);
@@ -346,13 +351,13 @@
}
writel(reg_val, &mctl_ctl->odtcfg);
- if (!para->bus_full_width) {
+ if (!config->bus_full_width) {
writel(0x0, &mctl_phy->dx[2].gcr[0]);
writel(0x0, &mctl_phy->dx[3].gcr[0]);
}
}
-static void mctl_bit_delay_set(struct dram_para *para)
+static void mctl_bit_delay_set(const struct dram_para *para)
{
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
@@ -411,7 +416,8 @@
}
}
-static bool mctl_channel_init(struct dram_para *para)
+static bool mctl_channel_init(const struct dram_para *para,
+ const struct dram_config *config)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -446,14 +452,14 @@
udelay(100);
- if (para->ranks == 2)
+ if (config->ranks == 2)
setbits_le32(&mctl_phy->dtcr[1], 0x30000);
else
clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
if (sunxi_dram_is_lpddr(para->type))
clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
- if (para->ranks == 2) {
+ if (config->ranks == 2) {
writel(0x00010001, &mctl_phy->rankidr);
writel(0x20000, &mctl_phy->odtcr);
} else {
@@ -555,90 +561,6 @@
return true;
}
-static void mctl_auto_detect_rank_width(struct dram_para *para)
-{
- /* this is minimum size that it's supported */
- para->cols = 8;
- para->rows = 13;
-
- /*
- * Previous versions of this driver tried to auto detect the rank
- * and width by looking at controller registers. However this proved
- * to be not reliable, so this approach here is the more robust
- * solution. Check the git history for details.
- *
- * Strategy here is to test most demanding combination first and least
- * demanding last, otherwise HW might not be fully utilized. For
- * example, half bus width and rank = 1 combination would also work
- * on HW with full bus width and rank = 2, but only 1/4 RAM would be
- * visible.
- */
-
- debug("testing 32-bit width, rank = 2\n");
- para->bus_full_width = 1;
- para->ranks = 2;
- if (mctl_core_init(para))
- return;
-
- debug("testing 32-bit width, rank = 1\n");
- para->bus_full_width = 1;
- para->ranks = 1;
- if (mctl_core_init(para))
- return;
-
- debug("testing 16-bit width, rank = 2\n");
- para->bus_full_width = 0;
- para->ranks = 2;
- if (mctl_core_init(para))
- return;
-
- debug("testing 16-bit width, rank = 1\n");
- para->bus_full_width = 0;
- para->ranks = 1;
- if (mctl_core_init(para))
- return;
-
- panic("This DRAM setup is currently not supported.\n");
-}
-
-static void mctl_auto_detect_dram_size(struct dram_para *para)
-{
- /* TODO: non-(LP)DDR3 */
-
- /* detect row address bits */
- para->cols = 8;
- para->rows = 18;
- mctl_core_init(para);
-
- for (para->rows = 13; para->rows < 18; para->rows++) {
- /* 8 banks, 8 bit per byte and 16/32 bit width */
- if (mctl_mem_matches((1 << (para->rows + para->cols +
- 4 + para->bus_full_width))))
- break;
- }
-
- /* detect column address bits */
- para->cols = 11;
- mctl_core_init(para);
-
- for (para->cols = 8; para->cols < 11; para->cols++) {
- /* 8 bits per byte and 16/32 bit width */
- if (mctl_mem_matches(1 << (para->cols + 1 +
- para->bus_full_width)))
- break;
- }
-}
-
-unsigned long mctl_calc_size(struct dram_para *para)
-{
- u8 width = para->bus_full_width ? 4 : 2;
-
- /* TODO: non-(LP)DDR3 */
-
- /* 8 banks */
- return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
-}
-
#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
@@ -661,36 +583,36 @@
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- struct dram_para para = {
- .clk = CONFIG_DRAM_CLK,
+static const struct dram_para para = {
+ .clk = CONFIG_DRAM_CLK,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
- .type = SUNXI_DRAM_TYPE_LPDDR3,
- .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
+ .type = SUNXI_DRAM_TYPE_LPDDR3,
+ .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
#elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
- .type = SUNXI_DRAM_TYPE_DDR3,
- .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
+ .type = SUNXI_DRAM_TYPE_DDR3,
+ .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
#endif
- };
+};
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
+ struct dram_config config;
unsigned long size;
- setbits_le32(&prcm->res_cal_ctrl, BIT(8));
- clrbits_le32(&prcm->ohms240, 0x3f);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8));
+ clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f);
- mctl_auto_detect_rank_width(¶);
- mctl_auto_detect_dram_size(¶);
+ mctl_auto_detect_rank_width(¶, &config);
+ mctl_auto_detect_dram_size(¶, &config);
- mctl_core_init(¶);
+ mctl_core_init(¶, &config);
- size = mctl_calc_size(¶);
+ size = mctl_calc_size(&config);
clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index cd9d321..5a59f82 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
+#include <asm/arch/dram_dw_helpers.h>
#include <asm/arch/cpu.h>
#include <asm/arch/prcm.h>
#include <linux/bitops.h>
@@ -93,34 +94,34 @@
static void mctl_sys_init(u32 clk_rate)
{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void * const ccm = (void *)SUNXI_CCM_BASE;
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
/* Put all DRAM-related blocks to reset state */
- clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
- clrbits_le32(&ccm->mbus_cfg, MBUS_RESET);
- clrbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT));
+ clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE);
+ clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET);
+ clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT));
udelay(5);
- clrbits_le32(&ccm->dram_gate_reset, BIT(RESET_SHIFT));
- clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
- clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT));
+ clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN);
+ clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Set PLL5 rate to doubled DRAM clock rate */
writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN |
- CCM_PLL5_CTRL_N(clk_rate * 2 / 24), &ccm->pll5_cfg);
- mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+ CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG);
+ mctl_await_completion(ccm + CCU_H6_PLL5_CFG,
+ CCM_PLL5_LOCK, CCM_PLL5_LOCK);
/* Configure DRAM mod clock */
- writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
- writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
+ writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG);
+ writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET);
udelay(5);
- setbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT));
+ setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT));
/* Disable all channels */
writel(0, &mctl_com->maer0);
@@ -128,12 +129,12 @@
writel(0, &mctl_com->maer2);
/* Configure MBUS and enable DRAM mod reset */
- setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
- setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET);
+ setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE);
clrbits_le32(&mctl_com->unk_0x500, BIT(25));
- setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
udelay(5);
/* Unknown hack, which enables access of mctl_ctl regs */
@@ -1310,154 +1311,14 @@
return true;
}
-static bool mctl_core_init(const struct dram_para *para,
- const struct dram_config *config)
+bool mctl_core_init(const struct dram_para *para,
+ const struct dram_config *config)
{
mctl_sys_init(para->clk);
return mctl_ctrl_init(para, config);
}
-static void mctl_auto_detect_rank_width(const struct dram_para *para,
- struct dram_config *config)
-{
- /* this is minimum size that it's supported */
- config->cols = 8;
- config->rows = 13;
-
- /*
- * Strategy here is to test most demanding combination first and least
- * demanding last, otherwise HW might not be fully utilized. For
- * example, half bus width and rank = 1 combination would also work
- * on HW with full bus width and rank = 2, but only 1/4 RAM would be
- * visible.
- */
-
- debug("testing 32-bit width, rank = 2\n");
- config->bus_full_width = 1;
- config->ranks = 2;
- if (mctl_core_init(para, config))
- return;
-
- debug("testing 32-bit width, rank = 1\n");
- config->bus_full_width = 1;
- config->ranks = 1;
- if (mctl_core_init(para, config))
- return;
-
- debug("testing 16-bit width, rank = 2\n");
- config->bus_full_width = 0;
- config->ranks = 2;
- if (mctl_core_init(para, config))
- return;
-
- debug("testing 16-bit width, rank = 1\n");
- config->bus_full_width = 0;
- config->ranks = 1;
- if (mctl_core_init(para, config))
- return;
-
- panic("This DRAM setup is currently not supported.\n");
-}
-
-static void mctl_write_pattern(void)
-{
- unsigned int i;
- u32 *ptr, val;
-
- ptr = (u32 *)CFG_SYS_SDRAM_BASE;
- for (i = 0; i < 16; ptr++, i++) {
- if (i & 1)
- val = ~(ulong)ptr;
- else
- val = (ulong)ptr;
- writel(val, ptr);
- }
-}
-
-static bool mctl_check_pattern(ulong offset)
-{
- unsigned int i;
- u32 *ptr, val;
-
- ptr = (u32 *)CFG_SYS_SDRAM_BASE;
- for (i = 0; i < 16; ptr++, i++) {
- if (i & 1)
- val = ~(ulong)ptr;
- else
- val = (ulong)ptr;
- if (val != *(ptr + offset / 4))
- return false;
- }
-
- return true;
-}
-
-static void mctl_auto_detect_dram_size(const struct dram_para *para,
- struct dram_config *config)
-{
- unsigned int shift, cols, rows;
- u32 buffer[16];
-
- /* max. config for columns, but not rows */
- config->cols = 11;
- config->rows = 13;
- mctl_core_init(para, config);
-
- /*
- * Store content so it can be restored later. This is important
- * if controller was already initialized and holds any data
- * which is important for restoring system.
- */
- memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
-
- mctl_write_pattern();
-
- shift = config->bus_full_width + 1;
-
- /* detect column address bits */
- for (cols = 8; cols < 11; cols++) {
- if (mctl_check_pattern(1ULL << (cols + shift)))
- break;
- }
- debug("detected %u columns\n", cols);
-
- /* restore data */
- memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
-
- /* reconfigure to make sure that all active rows are accessible */
- config->cols = 8;
- config->rows = 17;
- mctl_core_init(para, config);
-
- /* store data again as it might be moved */
- memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
-
- mctl_write_pattern();
-
- /* detect row address bits */
- shift = config->bus_full_width + 4 + config->cols;
- for (rows = 13; rows < 17; rows++) {
- if (mctl_check_pattern(1ULL << (rows + shift)))
- break;
- }
- debug("detected %u rows\n", rows);
-
- /* restore data again */
- memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
-
- config->cols = cols;
- config->rows = rows;
-}
-
-static unsigned long mctl_calc_size(const struct dram_config *config)
-{
- u8 width = config->bus_full_width ? 4 : 2;
-
- /* 8 banks */
- return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks;
-}
-
static const struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
@@ -1481,13 +1342,12 @@
unsigned long sunxi_dram_init(void)
{
- struct sunxi_prcm_reg *const prcm =
- (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ void *const prcm = (void *)SUNXI_PRCM_BASE;
struct dram_config config;
unsigned long size;
- setbits_le32(&prcm->res_cal_ctrl, BIT(8));
- clrbits_le32(&prcm->ohms240, 0x3f);
+ setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8));
+ clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f);
mctl_auto_detect_rank_width(¶, &config);
mctl_auto_detect_dram_size(¶, &config);
diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
index afe8e25..1ed46fe 100644
--- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
+++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
@@ -37,7 +37,7 @@
};
/* TODO: flexible timing */
-void mctl_set_timing_params(struct dram_para *para)
+void mctl_set_timing_params(void)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
index c243b57..c02f542 100644
--- a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
+++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
@@ -16,7 +16,7 @@
};
/* TODO: flexible timing */
-void mctl_set_timing_params(struct dram_para *para)
+void mctl_set_timing_params(void)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
index 422007c..a6d75c3 100644
--- a/arch/arm/mach-sunxi/rmr_switch.S
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -49,10 +49,22 @@
str lr, [r0, #4]
mrs lr, CPSR
str lr, [r0, #8]
+ mrs lr, SP_irq
+ str lr, [r0, #20]
mrc p15, 0, lr, cr1, cr0, 0 // SCTLR
str lr, [r0, #12]
mrc p15, 0, lr, cr12, cr0, 0 // VBAR
str lr, [r0, #16]
+//#ifdef CONFIG_MACH_SUN55I_A523
+ mrc p15, 0, lr, cr12, cr12, 5 // ICC_SRE
+ tst lr, #1
+ beq 1f
+ mrc p15, 0, lr, c4, c6, 0 // ICC_PMR
+ str lr, [r0, #24]
+ mrc p15, 0, lr, c12, c12, 7 // ICC_IGRPEN1
+ str lr, [r0, #28]
+1:
+//#endif
ldr r1, =CONFIG_SUNXI_RVBAR_ADDRESS
ldr r0, =SUNXI_SRAMC_BASE
diff --git a/arch/mips/mach-octeon/cvmx-helper-board.c b/arch/mips/mach-octeon/cvmx-helper-board.c
index 6dcc4e5..8d93889 100644
--- a/arch/mips/mach-octeon/cvmx-helper-board.c
+++ b/arch/mips/mach-octeon/cvmx-helper-board.c
@@ -386,8 +386,7 @@
/* If the link is down or the link is up but we still register
* the module as being absent, re-check mod_abs.
*/
- if (!result.s.link_up ||
- (result.s.link_up && sfp_info->last_mod_abs))
+ if (!result.s.link_up || sfp_info->last_mod_abs)
__cvmx_helper_update_sfp(ipd_port, sfp_info, result);
sfp_info = sfp_info->next_iface_sfp;
}
diff --git a/arch/mips/mach-octeon/cvmx-helper.c b/arch/mips/mach-octeon/cvmx-helper.c
index ccec57e..7dcaa1a 100644
--- a/arch/mips/mach-octeon/cvmx-helper.c
+++ b/arch/mips/mach-octeon/cvmx-helper.c
@@ -1729,7 +1729,7 @@
sfp_info = cvmx_helper_cfg_get_sfp_info(xiface, index);
while (sfp_info) {
- if ((!result.s.link_up || (result.s.link_up && sfp_info->last_mod_abs)))
+ if (!result.s.link_up || sfp_info->last_mod_abs)
cvmx_sfp_check_mod_abs(sfp_info, sfp_info->mod_abs_data);
sfp_info = sfp_info->next_iface_sfp;
}
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 9070946..0717833 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -16,6 +16,7 @@
SECTIONS
{
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text : {
arch/riscv/cpu/start.o (.text)
*(.text*)
@@ -46,6 +47,7 @@
_end = .;
_image_binary_end = .;
+ __image_copy_end = .;
.bss : {
__bss_start = .;
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 2ffe6ba..b11ea8b 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -10,6 +10,7 @@
SECTIONS
{
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text : {
arch/riscv/cpu/start.o (.text)
}
@@ -57,6 +58,8 @@
__efi_runtime_rel_stop = .;
}
+ __image_copy_end = .;
+
/DISCARD/ : { *(.rela.plt*) }
.rela.dyn : {
__rel_dyn_start = .;
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index ceb916b..5aeeedd 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -35,7 +35,7 @@
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
- uboot_blob: blob-ext {
+ uboot_blob: u-boot-nodtb {
filename = "u-boot-nodtb.bin";
};
};
diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
new file mode 100644
index 0000000..ab882d0
--- /dev/null
+++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#include "jh7110-common-u-boot.dtsi"
+#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts
index d2486f7..6b5b83b 100644
--- a/arch/riscv/dts/k1-bananapi-f3.dts
+++ b/arch/riscv/dts/k1-bananapi-f3.dts
@@ -5,6 +5,7 @@
#include "k1.dtsi"
#include "binman.dtsi"
+#include "k1-pinctrl.dtsi"
/ {
model = "Banana Pi BPI-F3";
@@ -21,5 +22,7 @@
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi
new file mode 100644
index 0000000..14e7096
--- /dev/null
+++ b/arch/riscv/dts/k1-pinctrl.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Yixun Lan <dlan@gentoo.org>
+ */
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
+
+&pinctrl {
+ uart0_2_cfg: uart0-2-cfg {
+ uart0-2-pins {
+ pinmux = <K1_PADCONF(68, 2)>,
+ <K1_PADCONF(69, 2)>;
+
+ bias-pull-up = <0>;
+ drive-strength = <32>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 7c0f1b9..a633e43 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -470,5 +470,11 @@
#reset-cells = <1>;
status = "disabled";
};
+
+ pinctrl: pinctrl@d401e000 {
+ compatible = "spacemit,k1-pinctrl", "pinctrl-single";
+ reg = <0x0 0xd401e000 0x0 0x400>;
+ pinctrl-single,register-width = <32>;
+ };
};
-};
\ No newline at end of file
+};
diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
index 05787bd..6e083bf 100644
--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
@@ -20,6 +20,7 @@
args = "-T sfspl";
u-boot-spl {
+ no-write-symbols;
};
};
};
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 22b675f..189b35c 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -27,6 +27,7 @@
obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += fdt_fixup.o
obj-$(CONFIG_$(SPL)CMD_BDI) += bdinfo.o
+obj-$(CONFIG_OF_BOARD) += board.o
# For building EFI apps
CFLAGS_NON_EFI := -fstack-protector-strong
diff --git a/arch/riscv/lib/board.c b/arch/riscv/lib/board.c
new file mode 100644
index 0000000..624c4ea
--- /dev/null
+++ b/arch/riscv/lib/board.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * RISC-V-specific handling of firmware FDT
+ */
+
+#include <asm/global_data.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int board_fdt_blob_setup(void **fdtp)
+{
+ if (!gd->arch.firmware_fdt_addr)
+ return -EEXIST;
+
+ *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+
+ return 0;
+}
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 52e9ddb..7026c73 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -131,6 +131,7 @@
font-size = <30>;
menu-inset = <3>;
menuitem-gap-y = <1>;
+ white-on-black;
};
cedit-theme {
diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h
index 619f8f5..c971711 100644
--- a/arch/sandbox/include/asm/scmi_test.h
+++ b/arch/sandbox/include/asm/scmi_test.h
@@ -27,10 +27,12 @@
* @id: Identifier of the clock used in the SCMI protocol
* @enabled: Clock state: true if enabled, false if disabled
* @rate: Clock rate in Hertz
+ * @perm: Indicating state/parent/rate permission
*/
struct sandbox_scmi_clk {
bool enabled;
ulong rate;
+ u32 perm;
};
/**
@@ -108,7 +110,7 @@
size_t regul_count;
};
-#ifdef CONFIG_SCMI_FIRMWARE
+#if IS_ENABLED(CONFIG_SCMI_FIRMWARE)
/**
* sandbox_scmi_channel_id - Get the channel id
* @dev: Reference to the SCMI protocol device
diff --git a/board/beagle/beagley-ai/MAINTAINERS b/board/beagle/beagley-ai/MAINTAINERS
index 1623329..04d5f67 100644
--- a/board/beagle/beagley-ai/MAINTAINERS
+++ b/board/beagle/beagley-ai/MAINTAINERS
@@ -3,6 +3,4 @@
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/beagle/beagley-ai/
-F: include/configs/beagley_ai.h
-F: configs/am67a_beagley_ai_r5_defconfig
-F: configs/am67a_beagley_ai_a53_defconfig
+N: beagley_ai
diff --git a/board/beagle/beagley-ai/beagley-ai.env b/board/beagle/beagley-ai/beagley-ai.env
index 10d6203..70afbf9 100644
--- a/board/beagle/beagley-ai/beagley-ai.env
+++ b/board/beagle/beagley-ai/beagley-ai.env
@@ -1,5 +1,6 @@
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
#include <env/ti/k3_rproc.env>
@@ -10,8 +11,11 @@
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+set_led_state_fail_load=led led-0 off
+set_led_state_start_load=led led-0 on
-boot_targets=mmc1 mmc0 pxe dhcp
+boot_targets=mmc1
+bootmeths=script extlinux efi pxe
boot=mmc
mmcdev=1
bootpart=1:2
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index a90222e..70190eb 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -63,11 +63,3 @@
return 0;
}
#endif
-
-int board_fdt_blob_setup(void **fdtp)
-{
- /* Stored the DTB address there during our init */
- *fdtp = (void *)(ulong)gd->arch.firmware_fdt_addr;
-
- return 0;
-}
diff --git a/board/freescale/imx95_evk/Kconfig b/board/freescale/imx95_evk/Kconfig
new file mode 100644
index 0000000..f9a6735
--- /dev/null
+++ b/board/freescale/imx95_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX95_19X19_EVK
+
+config SYS_BOARD
+ default "imx95_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx95_evk"
+
+endif
diff --git a/board/freescale/imx95_evk/MAINTAINERS b/board/freescale/imx95_evk/MAINTAINERS
new file mode 100644
index 0000000..5caf763
--- /dev/null
+++ b/board/freescale/imx95_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX95 EVK BOARD
+M: Alice Guo <alice.guo@nxp.com>
+S: Maintained
+F: board/freescale/imx95_evk/
+F: include/configs/imx95_evk.h
+F: configs/imx95_19x19_evk_defconfig
diff --git a/board/freescale/imx95_evk/Makefile b/board/freescale/imx95_evk/Makefile
new file mode 100644
index 0000000..0f5cec3
--- /dev/null
+++ b/board/freescale/imx95_evk/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx95_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/freescale/imx95_evk/imx95_19x19_evk.env b/board/freescale/imx95_evk/imx95_19x19_evk.env
new file mode 100644
index 0000000..a002767
--- /dev/null
+++ b/board/freescale/imx95_evk/imx95_19x19_evk.env
@@ -0,0 +1,91 @@
+sec_boot=no
+initrd_addr=0x93800000
+emmc_dev=0
+sd_dev=1
+scriptaddr=0x93500000
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+image=Image
+splashimage=0xA0000000
+console=ttyLP0,115200 earlycon
+fdt_addr_r=0x93000000
+fdt_addr=0x93000000
+cntr_addr=0xA8000000
+cntr_file=os_cntr_signed.bin
+boot_fit=no
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+bootm_size=0x10000000
+mmcdev=CONFIG_SYS_MMC_ENV_DEV
+mmcautodetect=yes
+mmcargs=setenv bootargs console=${console} root=${mmcroot}
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=auth_cntr ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r};
+mmcboot=echo Booting from mmc ...;
+ run mmcargs;
+ if test ${sec_boot} = yes; then
+ if run auth_os; then
+ run boot_os;
+ else
+ echo ERR: failed to authenticate;
+ fi;
+ else
+ if test ${boot_fit} = yes || test ${boot_fit} = try; then
+ bootm ${loadaddr};
+ else
+ if run loadfdt; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+ fi;
+netargs=setenv bootargs console=${console} root=/dev/nfs
+ ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=echo Booting from net ...;
+ run netargs;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ if test ${sec_boot} = yes; then
+ ${get_cmd} ${cntr_addr} ${cntr_file};
+ if run auth_os; then
+ run boot_os;
+ else
+ echo ERR: failed to authenticate;
+ fi;
+ else
+ ${get_cmd} ${loadaddr} ${image};
+ if test ${boot_fit} = yes || test ${boot_fit} = try; then
+ bootm ${loadaddr};
+ else
+ if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+ fi;
+bsp_bootcmd=echo Running BSP bootcmd ...;
+ mmc dev ${mmcdev}; if mmc rescan; then
+ if run loadbootscript; then
+ run bootscript;
+ else
+ if test ${sec_boot} = yes; then
+ if run loadcntr; then
+ run mmcboot;
+ else run netboot;
+ fi;
+ else
+ if run loadimage; then
+ run mmcboot;
+ else run netboot;
+ fi;
+ fi;
+ fi;
+ fi;
diff --git a/board/freescale/imx95_evk/imx95_evk.c b/board/freescale/imx95_evk/imx95_evk.c
new file mode 100644
index 0000000..d5f5e31
--- /dev/null
+++ b/board/freescale/imx95_evk/imx95_evk.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/sys_proto.h>
+
+int board_early_init_f(void)
+{
+ /* UART1: A55, UART2: M33, UART3: M7 */
+ init_uart_clk(0);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+ board_late_mmc_env_init();
+
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE;
+
+ return 0;
+}
diff --git a/board/freescale/imx95_evk/spl.c b/board/freescale/imx95_evk/spl.c
new file mode 100644
index 0000000..08f4da0
--- /dev/null
+++ b/board/freescale/imx95_evk/spl.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/mu.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/sections.h>
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_SPL_RECOVER_DATA_SECTION
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ spl_save_restore_data();
+#endif
+
+ timer_init();
+
+ /* Need dm_init() to run before any SCMI calls can be made. */
+ spl_early_init();
+
+ /* Need enable SCMI drivers and ELE driver before enabling console */
+ ret = imx9_probe_mu();
+ if (ret)
+ hang(); /* if MU not probed, nothing can output, just hang here */
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ preloader_console_init();
+
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c
index c1c3746..f5da289 100644
--- a/board/sifive/unleashed/unleashed.c
+++ b/board/sifive/unleashed/unleashed.c
@@ -114,17 +114,6 @@
#endif
-int board_fdt_blob_setup(void **fdtp)
-{
- if (gd->arch.firmware_fdt_addr) {
- *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
-
- return 0;
- }
-
- return -EEXIST;
-}
-
int board_init(void)
{
/* enable all cache ways */
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index 23e03e1..a57ce1f 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -10,16 +10,6 @@
#include <dm.h>
#include <asm/sections.h>
-int board_fdt_blob_setup(void **fdtp)
-{
- if (gd->arch.firmware_fdt_addr) {
- *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
- return 0;
- }
-
- return -EEXIST;
-}
-
int board_init(void)
{
/* enable all cache ways */
diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c
index 1db8e45..8c1f80b 100644
--- a/board/st/common/stm32mp_dfu.c
+++ b/board/st/common/stm32mp_dfu.c
@@ -105,7 +105,7 @@
if (env_get("dfu_alt_info"))
return;
- memset(buf, 0, sizeof(buf));
+ memset(buf, 0, DFU_ALT_BUF_LEN);
snprintf(buf, DFU_ALT_BUF_LEN,
"ram 0=%s", CONFIG_DFU_ALT_RAM0);
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
index d5a09cd..f924e61 100644
--- a/board/st/stm32mp1/MAINTAINERS
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -1,5 +1,6 @@
STM32MP1 BOARD
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
+M: Patrice Chotard <patrice.chotard@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
@@ -10,6 +11,7 @@
F: configs/stm32mp15_defconfig
F: configs/stm32mp15_basic_defconfig
F: configs/stm32mp15_trusted_defconfig
+F: configs/stm32mp15-odyssey_defconfig
F: include/configs/stm32mp13_common.h
F: include/configs/stm32mp13_st_common.h
F: include/configs/stm32mp15_common.h
diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig
index 89039f0..f91e25f 100644
--- a/board/st/stm32mp2/Kconfig
+++ b/board/st/stm32mp2/Kconfig
@@ -7,7 +7,7 @@
default "st"
config SYS_CONFIG_NAME
- default "stm32mp25_common"
+ default "stm32mp25_st_common"
source "board/st/common/Kconfig"
endif
diff --git a/board/st/stm32mp2/MAINTAINERS b/board/st/stm32mp2/MAINTAINERS
index e6bea91..8f62481 100644
--- a/board/st/stm32mp2/MAINTAINERS
+++ b/board/st/stm32mp2/MAINTAINERS
@@ -7,3 +7,4 @@
F: board/st/stm32mp2/
F: configs/stm32mp25_defconfig
F: include/configs/stm32mp25_common.h
+F: include/configs/stm32mp25_st_common.h
diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c
index aa7dd31..2547f2e 100644
--- a/board/st/stm32mp2/stm32mp2.c
+++ b/board/st/stm32mp2/stm32mp2.c
@@ -5,16 +5,21 @@
#define LOG_CATEGORY LOGC_BOARD
+#include <button.h>
#include <config.h>
-#include <env.h>
+#include <env_internal.h>
#include <fdt_support.h>
+#include <led.h>
#include <log.h>
#include <misc.h>
+#include <mmc.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/ofnode.h>
#include <dm/uclass.h>
+#include <linux/delay.h>
/*
* Get a global data pointer
@@ -53,12 +58,140 @@
return 0;
}
+static int get_led(struct udevice **dev, char *led_string)
+{
+ const char *led_name;
+ int ret;
+
+ led_name = ofnode_conf_read_str(led_string);
+ if (!led_name) {
+ log_debug("could not find %s config string\n", led_string);
+ return -ENOENT;
+ }
+ ret = led_get_by_label(led_name, dev);
+ if (ret) {
+ log_debug("get=%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int setup_led(enum led_state_t cmd)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(LED))
+ return 0;
+
+ ret = get_led(&dev, "u-boot,boot-led");
+ if (ret)
+ return ret;
+
+ ret = led_set_state(dev, cmd);
+ return ret;
+}
+
+static void check_user_button(void)
+{
+ struct udevice *button;
+ int i;
+
+ if (!IS_ENABLED(CONFIG_CMD_STM32PROG) || !IS_ENABLED(CONFIG_BUTTON))
+ return;
+
+ if (button_get_by_label("User-2", &button))
+ return;
+
+ for (i = 0; i < 21; ++i) {
+ if (button_get_state(button) != BUTTON_ON)
+ return;
+ if (i < 20)
+ mdelay(50);
+ }
+
+ log_notice("entering download mode...\n");
+ clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_STM32PROG);
+}
+
/* board dependent setup after realloc */
int board_init(void)
{
+ setup_led(LEDST_ON);
+ check_user_button();
+
return 0;
}
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 bootmode = get_bootmode();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
+ case BOOT_FLASH_SD:
+ case BOOT_FLASH_EMMC:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+ return ENVL_MMC;
+ else
+ return ENVL_NOWHERE;
+
+ case BOOT_FLASH_NAND:
+ case BOOT_FLASH_SPINAND:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI))
+ return ENVL_UBI;
+ else
+ return ENVL_NOWHERE;
+
+ case BOOT_FLASH_NOR:
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ else
+ return ENVL_NOWHERE;
+ default:
+ return ENVL_NOWHERE;
+ }
+}
+
+int mmc_get_boot(void)
+{
+ struct udevice *dev;
+ u32 boot_mode = get_bootmode();
+ unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ char cmd[20];
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
+
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ return 0;
+
+ /* search associated sdmmc node in devicetree */
+ snprintf(cmd, sizeof(cmd), "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ log_err("mmc%d = %s not found in device tree!\n", instance, cmd);
+ return 0;
+ }
+
+ return dev_seq(dev);
+};
+
+int mmc_get_env_dev(void)
+{
+ const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1));
+
+ if (mmc_env_dev >= 0)
+ return mmc_env_dev;
+
+ /* use boot instance to select the correct mmc device identifier */
+ return mmc_get_boot();
+}
+
int board_late_init(void)
{
const void *fdt_compat;
@@ -86,3 +219,8 @@
return 0;
}
+
+void board_quiesce_devices(void)
+{
+ setup_led(LEDST_OFF);
+}
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
index 898e284..9d348c4 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -2,6 +2,6 @@
M: Minda Chen <minda.chen@starfivetech.com>
M: Hal Feng <hal.feng@starfivetech.com>
S: Maintained
-F: drivers/ram/starfive/
+N: starfive
N: jh7110
N: visionfive2
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 3e4d3e2..3dfa931 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -116,30 +116,29 @@
#if CONFIG_IS_ENABLED(LOAD_FIT)
int board_fit_config_name_match(const char *name)
{
- const char *product_id;
- u8 version;
-
- product_id = get_product_id_from_eeprom();
-
- /* Strip off prefix */
- if (strncmp(name, "starfive/", 9))
- return -EINVAL;
- name += 9;
- if (!strncmp(product_id, "VF7110", 6)) {
- version = get_pcb_revision_from_eeprom();
- if ((version == 'b' || version == 'B') &&
- !strcmp(name, "jh7110-starfive-visionfive-2-v1.3b"))
- return 0;
-
- if ((version == 'a' || version == 'A') &&
- !strcmp(name, "jh7110-starfive-visionfive-2-v1.2a"))
- return 0;
- } else if (!strncmp(product_id, "MARS", 4) &&
- !strcmp(name, "jh7110-milkv-mars")) {
+ if (!strcmp(name, "starfive/jh7110-deepcomputing-fml13v01") &&
+ !strncmp(get_product_id_from_eeprom(), "FML13V01", 8)) {
return 0;
- } else if (!strncmp(product_id, "STAR64", 6) &&
- !strcmp(name, "jh7110-pine64-star64")) {
+ } else if (!strcmp(name, "starfive/jh7110-milkv-mars") &&
+ !strncmp(get_product_id_from_eeprom(), "MARS", 4)) {
return 0;
+ } else if (!strcmp(name, "starfive/jh7110-pine64-star64") &&
+ !strncmp(get_product_id_from_eeprom(), "STAR64", 6)) {
+ return 0;
+ } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.2a") &&
+ !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) {
+ switch (get_pcb_revision_from_eeprom()) {
+ case 'a':
+ case 'A':
+ return 0;
+ }
+ } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") &&
+ !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) {
+ switch (get_pcb_revision_from_eeprom()) {
+ case 'b':
+ case 'B':
+ return 0;
+ }
}
return -EINVAL;
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index b8cd509..bfbb11a 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -17,14 +17,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
-#define FDTFILE_MILK_V_MARS \
- "starfive/jh7110-milkv-mars.dtb"
-#define FDTFILE_VISIONFIVE2_1_2A \
- "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
-#define FDTFILE_VISIONFIVE2_1_3B \
- "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
-#define FDTFILE_PINE64_STAR64 \
- "starfive/jh7110-pine64-star64.dtb"
/* enable U74-mc hart1~hart4 prefetcher */
static void enable_prefetcher(void)
@@ -46,42 +38,41 @@
}
/**
- * set_fdtfile() - set the $fdtfile variable based on the board revision
+ * set_fdtfile() - set the $fdtfile variable based on product data in EEPROM
*/
static void set_fdtfile(void)
{
- u8 version;
const char *fdtfile;
- const char *product_id;
fdtfile = env_get("fdtfile");
if (fdtfile)
return;
- product_id = get_product_id_from_eeprom();
- if (!product_id) {
+ if (!get_product_id_from_eeprom()) {
log_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
- fdtfile = FDTFILE_MILK_V_MARS;
- } else if (!strncmp(product_id, "VF7110", 6)) {
- version = get_pcb_revision_from_eeprom();
- switch (version) {
+ if (!strncmp(get_product_id_from_eeprom(), "FML13V01", 8)) {
+ fdtfile = "starfive/jh7110-deepcomputing-fml13v01.dtb";
+ } else if (!strncmp(get_product_id_from_eeprom(), "MARS", 4)) {
+ fdtfile = "starfive/jh7110-milkv-mars.dtb";
+ } else if (!strncmp(get_product_id_from_eeprom(), "STAR64", 6)) {
+ fdtfile = "starfive/jh7110-pine64-star64.dtb";
+ } else if (!strncmp(get_product_id_from_eeprom(), "VF7110", 6)) {
+ switch (get_pcb_revision_from_eeprom()) {
case 'a':
case 'A':
- fdtfile = FDTFILE_VISIONFIVE2_1_2A;
+ fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
break;
-
case 'b':
case 'B':
- default:
- fdtfile = FDTFILE_VISIONFIVE2_1_3B;
+ fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
break;
+ default:
+ log_err("Unknown revision\n");
+ return;
}
- } else if (!strncmp(product_id, "STAR64", 6)) {
- fdtfile = FDTFILE_PINE64_STAR64;
} else {
log_err("Unknown product\n");
return;
@@ -106,16 +97,6 @@
return 0;
}
-int board_fdt_blob_setup(void **fdtp)
-{
- if (gd->arch.firmware_fdt_addr) {
- *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
- return 0;
- }
-
- return -EEXIST;
-}
-
int ft_board_setup(void *blob, struct bd_info *bd)
{
return fdt_fixup_memory(blob, 0x40000000, gd->ram_size);
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index f738cba..4ada8b5 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -307,6 +307,9 @@
if (board_is_pb() || board_is_bone_lt())
freq = MPUPLL_M_1000;
+ if (board_is_bbge())
+ freq = MPUPLL_M_600;
+
switch (freq) {
case MPUPLL_M_1000:
return &dpll_mpu_opp[ind][5];
@@ -823,6 +826,8 @@
if (board_is_bbg1())
name = "BBG1";
+ if (board_is_bbge())
+ name = "BBGE";
if (board_is_bben()) {
char subtype_id = board_ti_get_config()[1];
@@ -955,7 +960,7 @@
return 0;
else if (board_is_bone() && !strcmp(name, "am335x-bone"))
return 0;
- else if (board_is_bone_lt() && !board_is_bbg1() &&
+ else if (board_is_bone_lt() && !board_is_bbg1() && !board_is_bbge() &&
!strcmp(name, "am335x-boneblack"))
return 0;
else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
@@ -964,6 +969,8 @@
return 0;
else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
return 0;
+ else if (board_is_bbge() && !strcmp(name, "am335x-bonegreen-eco"))
+ return 0;
else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
return 0;
else if (board_is_bben()) {
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index b0a3842..2fe88d3 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -45,6 +45,11 @@
return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
}
+static inline int board_is_bbge(void)
+{
+ return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBGE", 4);
+}
+
static inline int board_is_bben(void)
{
return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "SE", 2);
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index c6e46b7..c8d01bf 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -7,6 +7,7 @@
*
*/
+#include <dm.h>
#include <efi_loader.h>
#include <init.h>
#include <spl.h>
@@ -67,4 +68,27 @@
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ESM_K3)) {
+ const char * const esms[] = {"esm@700000", "esm@40800000", "esm@42080000"};
+
+ for (int i = 0; i < ARRAY_SIZE(esms); ++i) {
+ ret = uclass_get_device_by_name(UCLASS_MISC, esms[i],
+ &dev);
+ if (ret) {
+ printf("MISC init for %s failed: %d\n", esms[i], ret);
+ break;
+ }
+ }
+ }
+
+ if (IS_ENABLED(CONFIG_ESM_PMIC) && ret == 0) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(pmic_esm),
+ &dev);
+ if (ret)
+ printf("ESM PMIC init failed: %d\n", ret);
+ }
}
diff --git a/boot/Kconfig b/boot/Kconfig
index fb37d91..30eb5b3 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -427,8 +427,8 @@
menuconfig BOOTSTD
bool "Standard boot"
- default y
- depends on DM && OF_CONTROL && BLK
+ default y if BLK
+ depends on DM && OF_CONTROL
help
U-Boot supports a standard way of locating something to boot,
typically an Operating System such as Linux, provided by a distro such
@@ -1170,7 +1170,7 @@
config BOOTSTAGE_RECORD_COUNT
int "Number of boot stage records to store"
depends on BOOTSTAGE
- default 30
+ default 50
help
This is the size of the bootstage record list and is the maximum
number of bootstage records that can be recorded.
diff --git a/boot/bootm.c b/boot/bootm.c
index f5cbb10..f6aa327 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -34,6 +34,7 @@
#include <bootm.h>
#include <image.h>
+#include <u-boot/zlib.h>
#define MAX_CMDLINE_SIZE SZ_4K
@@ -578,7 +579,8 @@
if (ret == -ENOSYS)
return BOOTM_ERR_UNIMPLEMENTED;
- if (uncomp_size >= buf_size)
+ if ((comp_type == IH_COMP_GZIP && ret == Z_BUF_ERROR) ||
+ uncomp_size >= buf_size)
printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n");
else
printf("%s: uncompress error %d\n", name, ret);
diff --git a/boot/bootm_os.c b/boot/bootm_os.c
index dc9d3e6..a3c7cb5 100644
--- a/boot/bootm_os.c
+++ b/boot/bootm_os.c
@@ -498,11 +498,11 @@
/* We expect to return */
images->os.type = IH_TYPE_STANDALONE;
- image_buf = map_sysmem(images->ep, images->os.image_len);
+ image_buf = map_sysmem(images->os.image_start, images->os.image_len);
/* Run EFI image */
printf("## Transferring control to EFI (at address %08lx) ...\n",
- images->ep);
+ images->os.image_start);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
ret = efi_binary_run(image_buf, images->os.image_len,
diff --git a/boot/expo.c b/boot/expo.c
index 786f665..8ce645e 100644
--- a/boot/expo.c
+++ b/boot/expo.c
@@ -194,7 +194,7 @@
u32 colour;
int ret;
- back = CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK) ? VID_BLACK : VID_WHITE;
+ back = vid_priv->white_on_black ? VID_BLACK : VID_WHITE;
colour = video_index_to_colour(vid_priv, back);
ret = video_fill(dev, colour);
if (ret)
diff --git a/boot/scene.c b/boot/scene.c
index 3290a40..fb82ffe 100644
--- a/boot/scene.c
+++ b/boot/scene.c
@@ -298,7 +298,7 @@
}
ret = vidconsole_measure(scn->expo->cons, txt->font_name,
- txt->font_size, str, &bbox);
+ txt->font_size, str, -1, &bbox, NULL);
if (ret)
return log_msg_ret("mea", ret);
if (widthp)
@@ -330,8 +330,9 @@
enum colour_idx fore, back;
uint inset = theme->menu_inset;
+ vid_priv = dev_get_uclass_priv(dev);
/* draw a background for the object */
- if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
+ if (vid_priv->white_on_black) {
fore = VID_DARK_GREY;
back = VID_WHITE;
} else {
@@ -344,7 +345,6 @@
return;
vidconsole_push_colour(cons, fore, back, &old);
- vid_priv = dev_get_uclass_priv(dev);
video_fill_part(dev, label_bbox.x0 - inset, label_bbox.y0 - inset,
label_bbox.x1 + inset, label_bbox.y1 + inset,
vid_priv->colour_fg);
@@ -408,7 +408,8 @@
struct vidconsole_colour old;
enum colour_idx fore, back;
- if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
+ vid_priv = dev_get_uclass_priv(dev);
+ if (vid_priv->white_on_black) {
fore = VID_BLACK;
back = VID_WHITE;
} else {
@@ -416,7 +417,6 @@
back = VID_BLACK;
}
- vid_priv = dev_get_uclass_priv(dev);
if (obj->flags & SCENEOF_POINT) {
vidconsole_push_colour(cons, fore, back, &old);
video_fill_part(dev, x - theme->menu_inset, y,
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2d31abc..f21d27c 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -5,7 +5,7 @@
Enable U-Boot's command-line functions. This provides a means
to enter commands into U-Boot for a wide variety of purposes. It
also allows scripts (containing commands) to be executed.
- Various commands and command categorys can be indivdually enabled.
+ Various commands and command categories can be individually enabled.
Depending on the number of commands enabled, this can add
substantially to the size of U-Boot.
diff --git a/cmd/spawn.c b/cmd/spawn.c
index eddbcb7..37737b8 100644
--- a/cmd/spawn.c
+++ b/cmd/spawn.c
@@ -169,7 +169,7 @@
} else {
for (i = 1; i < argc; i++) {
id = dectoul(argv[i], NULL);
- if (id < 0 || id > CONFIG_CMD_SPAWN_NUM_JOBS)
+ if (id < 1 || id > CONFIG_CMD_SPAWN_NUM_JOBS)
return CMD_RET_USAGE;
idx = (int)id - 1;
ret = wait_job(idx);
diff --git a/common/board_r.c b/common/board_r.c
index bc6fd64..b90a4d9 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -639,7 +639,7 @@
#if CONFIG_IS_ENABLED(CONSOLE_RECORD)
INITCALL(console_record_init);
#endif
-#if CONFIG_IS_ENABLED(SYS_NONCACHED_MEMORY)
+#if CONFIG_IS_ENABLED(SYS_HAS_NONCACHED_MEMORY)
INITCALL(noncached_init);
#endif
INITCALL(initr_of_live);
diff --git a/common/console.c b/common/console.c
index 275da2f..48586fd 100644
--- a/common/console.c
+++ b/common/console.c
@@ -359,6 +359,24 @@
console_puts_select(stderr, serial_only, s);
}
+int console_printf_select_stderr(bool serial_only, const char *fmt, ...)
+{
+ char buf[CONFIG_SYS_PBSIZE];
+ va_list args;
+ int ret;
+
+ va_start(args, fmt);
+
+ /* For this to work, buf must be larger than anything we ever want to
+ * print.
+ */
+ ret = vscnprintf(buf, sizeof(buf), fmt, args);
+ va_end(args);
+ console_puts_select_stderr(serial_only, buf);
+
+ return ret;
+}
+
static void console_puts(int file, const char *s)
{
int i;
diff --git a/common/event.c b/common/event.c
index dda569d..8d7513e 100644
--- a/common/event.c
+++ b/common/event.c
@@ -48,6 +48,9 @@
/* main loop events */
"main_loop",
+
+ /* livetree has been built */
+ "of_live_init",
};
_Static_assert(ARRAY_SIZE(type_name) == EVT_COUNT, "event type_name size");
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b076f49..0bc96d0 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -363,6 +363,12 @@
Support booting U-Boot from an i.MX8 container image. If you are not
using i.MX8, say 'n'.
+config SPL_IMX_CONTAINER_USE_TRAMPOLINE
+ bool
+ depends on SPL
+ help
+ Enable SPL load reader to load data to a trampoline buffer.
+
config IMX_CONTAINER_CFG
string "i.MX8 Container config file"
depends on SPL && SPL_LOAD_IMX_CONTAINER
diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c
index 2c31777..b3565ef 100644
--- a/common/spl/spl_imx_container.c
+++ b/common/spl/spl_imx_container.c
@@ -14,6 +14,16 @@
#include <asm/mach-imx/ahab.h>
#endif
+__weak bool arch_check_dst_in_secure(void *start, ulong size)
+{
+ return false;
+}
+
+__weak void *arch_get_container_trampoline(void)
+{
+ return NULL;
+}
+
static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
struct spl_load_info *info,
struct container_hdr *container,
@@ -22,6 +32,7 @@
{
struct boot_img_t *images;
ulong offset, overhead, size;
+ void *buf, *trampoline;
if (image_index > container->num_images) {
debug("Invalid image number\n");
@@ -42,12 +53,27 @@
debug("%s: container: %p offset: %lu size: %lu\n", __func__,
container, offset, size);
- if (info->read(info, offset, size,
- map_sysmem(images[image_index].dst - overhead,
- images[image_index].size)) <
- images[image_index].size) {
- printf("%s wrong\n", __func__);
- return NULL;
+
+ buf = map_sysmem(images[image_index].dst - overhead, images[image_index].size);
+ if (IS_ENABLED(CONFIG_SPL_IMX_CONTAINER_USE_TRAMPOLINE) &&
+ arch_check_dst_in_secure(buf, size)) {
+ trampoline = arch_get_container_trampoline();
+ if (!trampoline) {
+ printf("%s: trampoline size is zero\n", __func__);
+ return NULL;
+ }
+
+ if (info->read(info, offset, size, trampoline) < images[image_index].size) {
+ printf("%s: failed to load image to a trampoline buffer\n", __func__);
+ return NULL;
+ }
+
+ memcpy(buf, trampoline, images[image_index].size);
+ } else {
+ if (info->read(info, offset, size, buf) < images[image_index].size) {
+ printf("%s: failed to load image to a non-secure region\n", __func__);
+ return NULL;
+ }
}
#ifdef CONFIG_AHAB_BOOT
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 5a10fce..20fa977 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
-CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 5001ce9..4bb34d0 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PG11"
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index bc0fc0e..5183ece 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB1_VBUS_PIN="PG11"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_VGA_VIA_LCD=y
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 22d80ca..73b2845 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index e10660c..f885fc0 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index ac90047..34c1f5f 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index 00a9814..5f44d3d 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
index f4ae3ae..271d911 100644
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig
index df4acaf..e90cdda 100644
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -6,14 +6,13 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PB3"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 51f26f4..eda0c95 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=123
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index 0f8e571..32775a3 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 5209395..92e3016 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 8b3a9ea..2290a44 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 2cc7bbb..b1195af 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PH23"
-CONFIG_USB2_VBUS_PIN="PH23"
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig
index d26aa0b..1e793f1 100644
--- a/configs/Bananapi_m2m_defconfig
+++ b/configs/Bananapi_m2m_defconfig
@@ -7,7 +7,6 @@
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 02be897..46025e9 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PH0"
-CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index c220d26..70d2cfa 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_CHIP_DIP_SCAN=y
CONFIG_SPL_I2C=y
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index 0587412..17737d8 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_SPL_I2C=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index 1cd39d4..61fcb61 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 40f52d1..4713fbe 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 270bd7d..368919d 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=240
CONFIG_DRAM_ZQ=251
-CONFIG_USB1_VBUS_PIN=""
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0"
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index d3678ad..5b8428f 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -5,11 +5,8 @@
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH16"
-CONFIG_USB1_VBUS_PIN="PH14"
-CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 184143d..5f117f3 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PH17"
-CONFIG_USB0_VBUS_DET="PH22"
-CONFIG_USB0_ID_DET="PH19"
CONFIG_VIDEO_VGA=y
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 29f4df2..e02e70f 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -7,10 +7,6 @@
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH11"
-CONFIG_USB1_VBUS_PIN="PD29"
-CONFIG_USB2_VBUS_PIN="PL6"
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -21,6 +17,7 @@
CONFIG_SYS_I2C_SPEED=400000
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_DLDO4_VOLT=3300
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 18b1cfa..5130f27 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig
index abaf386..7d33a53 100644
--- a/configs/Empire_electronix_m712_defconfig
+++ b/configs/Empire_electronix_m712_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 24e8b5b..2bc9a09 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
-CONFIG_USB1_VBUS_PIN="PH24"
-CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 541f98d..6789e6b 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -4,10 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB09"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN="PH6"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH2"
CONFIG_VIDEO_LCD_BL_EN="PH9"
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 9eb9a918..3e6c280 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
-CONFIG_USB1_VBUS_PIN="PH11"
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 0e1a778..4b0b0e3 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -3,8 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-pcduino"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index d60eedb..9a7d80f 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -5,13 +5,13 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=122
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0"
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index c697d28..1f4739e 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 2b9bca1..be2e4d1 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index be6dd41..9b1bb97 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index a26677e..c47dc59 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -5,11 +5,8 @@
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH3"
-CONFIG_USB1_VBUS_PIN="PH4"
-CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index e64352b..b1d8cdb 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -3,7 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mini-xplus"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 53edf52..2ca40fd 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PH26"
-CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index ccf3267..6b6e402 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB1_VBUS_PIN="PH26"
-CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 59869b7..1c4c851 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index cfb4329..a230599 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PH8"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PH6"
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index aba9527..d7ef265 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index ad41dbd..98c533b 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -8,15 +8,13 @@
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH11"
-CONFIG_USB1_VBUS_PIN="PD24"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_INITIAL_USB_SCAN_DELAY=500
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_AXP_DLDO3_VOLT=3300
diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
index 348140d..0d78a13 100644
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -7,7 +7,4 @@
CONFIG_DRAM_ZQ=3881915
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PH15"
-CONFIG_USB1_VBUS_PIN="PL7"
-CONFIG_USB3_VBUS_PIN="PL8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index d74ef21..fb2b20b 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -6,9 +6,6 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PB04"
-CONFIG_USB0_VBUS_DET="PG01"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index 40aeb66..649e95b 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 9f6d2a7..49c87c3 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PG12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 9b13659..d798861 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=408
CONFIG_MMC1_PINS_PH=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index de69ebe..ae31b7f 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=420
CONFIG_DRAM_ZQ=251
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PA15"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 6d1da0c..674ad6c 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -52,7 +52,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-sancloud-bbe am335x-sancloud-bbe-lite am335x-sancloud-bbe-extended-wifi am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-sancloud-bbe am335x-sancloud-bbe-lite am335x-sancloud-bbe-extended-wifi am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle am335x-bonegreen-eco"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 221b2f2..d53d1b6 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -41,7 +41,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle am335x-bonegreen-eco"
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 396e743..55f1519 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -39,7 +39,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle am335x-bonegreen-eco"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index 4be0b2f..1bf7b5f 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -41,7 +41,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle am335x-bonegreen-eco"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 59e8c51..8f7d098 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -114,8 +114,12 @@
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
@@ -152,6 +156,9 @@
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65219=y
CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_TPS65219=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_RESET_TI_SCI=y
diff --git a/configs/am67a_beagley_ai_a53_defconfig b/configs/am67a_beagley_ai_a53_defconfig
index b0903b6..9a5172c 100644
--- a/configs/am67a_beagley_ai_a53_defconfig
+++ b/configs/am67a_beagley_ai_a53_defconfig
@@ -1,37 +1,146 @@
-#include <configs/j722s_evm_a53_defconfig>
-
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J722S=y
CONFIG_TARGET_J722S_A53_BEAGLEY_AI=y
-
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am67a-beagley-ai"
-CONFIG_SPL_OF_LIST="ti/k3-am67a-beagley-ai"
-CONFIG_OF_LIST="ti/k3-am67a-beagley-ai"
-
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run distro_bootcmd"
-CONFIG_EXT4_WRITE=y
-CONFIG_LZO=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_TI_I2C_BOARD_DETECT=n
-CONFIG_SPL_SPI=n
-CONFIG_SPL_SPI_FLASH_SUPPORT=n
-CONFIG_SPL_DM_SPI_FLASH=n
-CONFIG_SPL_MTD_SUPPORT=n
-CONFIG_SPL_MTD_SUPPORT=n
-CONFIG_DM_SPI_FLASH=n
-CONFIG_SPI_FLASH=n
-CONFIG_MTD=n
-CONFIG_MTD_PARTITIONS=n
-CONFIG_DM_MTD=n
-CONFIG_MTD_UBI=n
-CONFIG_CMD_UBIFS=n
-CONFIG_CMD_UBI=n
-CONFIG_DFU_SF=n
-CONFIG_DM_SPI=n
-CONFIG_SPL_SPI_LOAD=n
-CONFIG_SPL_MTD=n
-CONFIG_CMD_SPI=n
+CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb; run set_led_state_fail_load"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_SPL_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_FS_LOADER=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65219=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_TPS65219=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_DWC3_AM62=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_SPL_DFU=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_LZO=y
diff --git a/configs/am67a_beagley_ai_r5_defconfig b/configs/am67a_beagley_ai_r5_defconfig
index 5380747..0a7e1c8 100644
--- a/configs/am67a_beagley_ai_r5_defconfig
+++ b/configs/am67a_beagley_ai_r5_defconfig
@@ -1,14 +1,105 @@
-#include <configs/j722s_evm_r5_defconfig>
-
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J722S=y
+CONFIG_K3_QOS=y
CONFIG_TARGET_J722S_R5_BEAGLEY_AI=y
-
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am67a-r5-beagley-ai"
-CONFIG_SPL_OF_LIST="k3-am67a-r5-beagley-ai"
-CONFIG_OF_LIST="k3-am67a-r5-beagley-ai"
-
-CONFIG_TI_I2C_BOARD_DETECT=n
-CONFIG_SPL_DM_SPI_FLASH=n
-CONFIG_SPL_MTD_SUPPORT=n
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c7b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SIZE_LIMIT=0x3C000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x6ce00
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NO_NET=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+# CONFIG_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_ESM_K3=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index c76f36e..60b678a 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig
index 7483f12..30c4f8a 100644
--- a/configs/bananapi-f3_defconfig
+++ b/configs/bananapi-f3_defconfig
@@ -19,3 +19,5 @@
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
CONFIG_RESET_SPACEMIT_K1=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index f4edcf4..94d29a4 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
-CONFIG_USB1_VBUS_PIN="PH23"
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 07bda04..bdabca2 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PA15"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO2_VOLT=1800
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index b060430..3b59091 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index 06a79c9..9060db4 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -3,9 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-dserve-dsrv9703c"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:80000,le:479,ri:544,up:5,lo:26,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 935071d..a3fc34f 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -16,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index 205eab2..ba22a3e 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=32767
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:55000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 29f9652..2fcae46 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_PIN="PL5"
-CONFIG_USB1_VBUS_PIN="PL6"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index c96336f..6893b4a 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 76228f0..6cb55b6 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index afa530d..2acf11d 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index ed6a603..00ed5d4 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:120,ri:180,up:22,lo:13,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -15,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index 30c28f7..3812eed 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -9,9 +9,6 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
-CONFIG_USB0_VBUS_PIN="PG11"
-CONFIG_USB0_VBUS_DET="PH7"
-CONFIG_USB1_VBUS_PIN="PG10"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH22"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index e4eca19..27007bd 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -24,6 +24,7 @@
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index c605567..115288a 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -29,6 +29,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
+CONFIG_IMX_BOOTAUX=y
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 288626c..9f6fabc 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -33,6 +33,7 @@
CONFIG_ARMV8_EA_EL3_FIRST=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_PCI=y
+CONFIG_IMX_BOOTAUX=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig
new file mode 100644
index 0000000..fe968d5
--- /dev/null
+++ b/configs/imx95_19x19_evk_defconfig
@@ -0,0 +1,152 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x90200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ENV_SOURCE_FILE="imx95_19x19_evk"
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/scmi/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx95-19x19-evk"
+CONFIG_TARGET_IMX95_19X19_EVK=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x204d6000
+CONFIG_SPL_TEXT_BASE=0x20480000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x204d6000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x90400000
+CONFIG_SPL=y
+CONFIG_SPL_RECOVER_DATA_SECTION=y
+CONFIG_PCI=y
+CONFIG_SYS_MEMTEST_START=0x90000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx95-19x19-evk.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_RX_ETH_BUFFER=8
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SPL_FIRMWARE=y
+# CONFIG_SCMI_AGENT_SMCCC is not set
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_ADP5585_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_IMX_MU_MBOX=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_MII=y
+CONFIG_FSL_ENETC=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX_SCMI=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index 68a6df5..0a50992 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:52000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index d215a83..da0fb74 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index a5414e2..826141a 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index 48b20c0..7da2963 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 5b0cda1..ffc3548 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig
index 24ff6c0..5a48bd0 100644
--- a/configs/inet_q972_defconfig
+++ b/configs/inet_q972_defconfig
@@ -5,14 +5,13 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_ZQ=251
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PA15"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:280,ri:20,up:22,lo:8,hs:20,vs:8,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 5a5b045..8e5b777 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -125,6 +125,11 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
+CONFIG_ESM_K3=y
+CONFIG_ESM_PMIC=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR_TPS65941=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_TPS6287X=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index b41c2cf..f8c38aa 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index ec5df0b..d1211b0 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -46,3 +46,4 @@
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_PORT_MAPPED=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index ca017c4..dfa37d1 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -45,3 +45,4 @@
CONFIG_RTC_MC146818=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_PORT_MAPPED=y
+CONFIG_UNIT_TEST=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 2f92228..11e7a3d 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PH24"
-CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index d3d7402..f1812d6 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 8ebd5e9..edf64f8 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -3,7 +3,6 @@
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mk802"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
-CONFIG_USB2_VBUS_PIN="PH12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 7aaa519..50047d9 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -5,7 +5,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
-CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index adffe38..008c09d 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PG13"
-CONFIG_USB3_VBUS_PIN="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index f2265ea..831bfe6 100644
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -8,7 +8,6 @@
CONFIG_DRAM_SUNXI_TPR10=0xf83438
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
-CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig
index 63f9a73..8594924 100644
--- a/configs/orangepi_zero3_defconfig
+++ b/configs/orangepi_zero3_defconfig
@@ -13,7 +13,6 @@
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_LPDDR4=y
CONFIG_DRAM_CLK=792
-CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index 72235cc..631cfd8 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -6,8 +6,6 @@
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PD10"
-CONFIG_USB1_VBUS_PIN="PD12"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index 4ad3998..c52a2f7 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -28,7 +28,6 @@
CONFIG_SPL_BSS_START_ADDR=0x80c80000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SPL_SIZE_LIMIT=0x80000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
CONFIG_ENV_OFFSET_REDUND=0x6c0000
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index 20a4a0a..3eaa9c8 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -5,7 +5,6 @@
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB3_VBUS_PIN="PL5"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index 6ec7c83..6c0d4f1 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 1aefc50..7b64c8b 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 330c97f..21da05f 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:480,ri:260,up:6,lo:16,hs:320,vs:10,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH8"
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 93a2578..2c7bc20 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -4,9 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 0f8c30e..fcf13f6 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63306
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index b3b5cc7..22e27ab 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 37ee08f..1d9d6fc 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -5,8 +5,6 @@
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH8"
CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,6 +12,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index b9f2887..b9cb780 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index cd89571..8a09d80 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index 8d5f9d9..c4b6d57 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index c67fb9a..6b2fed4 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index d28e9fb..95f24ac 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 18b7e04..d2b0aec 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -1,6 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x20000
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 0c9f619..e90773f 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -4,7 +4,6 @@
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
-CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig
index b1d970b..6ec1512 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -27,6 +27,9 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -41,6 +44,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
@@ -50,6 +54,8 @@
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RAA215300=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 6a5b247..e145ced 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -80,7 +80,7 @@
CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
-CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index 1e5190d..582b5f3 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -8,7 +8,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7bdfff10
CONFIG_ENV_SIZE=0x4000
-CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
+CONFIG_DEFAULT_DEVICE_TREE="st/stih410-b2260"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_SYS_LOAD_ADDR=0x40000000
@@ -31,6 +31,7 @@
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig
index bd3a48b..5ffe1c1 100644
--- a/configs/stm32746g-eval_defconfig
+++ b/configs/stm32746g-eval_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32746g-eval"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -18,8 +18,9 @@
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglevel"
CONFIG_SYS_PBSIZE=1050
+CONFIG_DEFAULT_FDT_FILE="stm32746g-eval"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index d47d059..4706a72 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -9,7 +9,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32746g-eval"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
@@ -27,7 +27,8 @@
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32746g-eval"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_PAD_TO=0x9000
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 7788933..36e57ed 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f429-disco"
CONFIG_SYS_LOAD_ADDR=0x90400000
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
@@ -15,7 +15,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglevel"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig
index 2fa8dc9..5747187 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32429i-eval"
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_EVALUATION=y
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
index b014476..80e15c4 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10010000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f469-disco"
CONFIG_SYS_LOAD_ADDR=0x400000
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F469_DISCOVERY=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index f6fbf83..24bf6e6 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f746-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -18,7 +18,8 @@
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f746-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index dcf077d..f1761e5 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -9,7 +9,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f746-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
@@ -27,7 +27,8 @@
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f746-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_PAD_TO=0x9000
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 9edda0e..e539fce 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f769-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SYS_LOAD_ADDR=0x8008000
@@ -19,6 +19,7 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySTM0,115200n8 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f769-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CYCLIC_MAX_CPU_TIME_US=8000
@@ -52,12 +53,14 @@
CONFIG_MII=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_NOVATEK_NT35510=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_DSI=y
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index 7d4bda4..93c6c90 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -9,7 +9,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32f769-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
@@ -27,7 +27,8 @@
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_DEFAULT_FDT_FILE="stm32f769-disco"
CONFIG_SYS_PBSIZE=1050
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CYCLIC_MAX_CPU_TIME_US=8000
@@ -75,6 +76,7 @@
# CONFIG_PINCTRL_FULL is not set
CONFIG_SPL_PINCTRL=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_RAM=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SPI=y
@@ -84,6 +86,7 @@
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_NOVATEK_NT35510=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_DSI=y
diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig
index 40fc938..a674a20 100644
--- a/configs/stm32h743-disco_defconfig
+++ b/configs/stm32h743-disco_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32h743i-disco"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0xd0400000
CONFIG_STM32H7=y
diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig
index 953e67e..d63e721 100644
--- a/configs/stm32h743-eval_defconfig
+++ b/configs/stm32h743-eval_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32h743i-eval"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0xd0400000
CONFIG_STM32H7=y
diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig
index 4ca2d30..a92a57d 100644
--- a/configs/stm32h750-art-pi_defconfig
+++ b/configs/stm32h750-art-pi_defconfig
@@ -6,7 +6,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000
CONFIG_ENV_SIZE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32h750i-art-pi"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0xc1800000
CONFIG_STM32H7=y
diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index 4c6a7f8..530f6aa 100644
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x180000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000
CONFIG_ENV_OFFSET=0x900000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp135f-dk"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_STM32MP13X=y
diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
index 28a5d93..fc095ac 100644
--- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-ctouch2"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-icore-stm32mp1-ctouch2"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
index efac476..b243c45 100644
--- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-edimm2.2"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-icore-stm32mp1-edimm2.2"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
index f9f55d1..e635c726 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0-of7"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
index d573235..9e7849f 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
@@ -4,7 +4,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-microgea-stm32mp1-microdev2.0"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
diff --git a/configs/stm32mp15-odyssey_defconfig b/configs/stm32mp15-odyssey_defconfig
new file mode 100644
index 0000000..be8d9ae
--- /dev/null
+++ b/configs/stm32mp15-odyssey_defconfig
@@ -0,0 +1,172 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
+CONFIG_ENV_OFFSET=0x900000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-odyssey"
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
+CONFIG_CMD_STM32KEY=y
+CONFIG_TYPEC_STUSB160X=y
+CONFIG_TARGET_ST_STM32MP15X=y
+CONFIG_ENV_OFFSET_REDUND=0x940000
+CONFIG_CMD_STM32PROG=y
+# CONFIG_ARMV7_NONSEC is not set
+CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_SYS_MEMTEST_START=0xc0000000
+CONFIG_SYS_MEMTEST_END=0xc4000000
+CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_FDT_SIMPLEFB=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PBSIZE=1050
+CONFIG_SYS_PROMPT="STM32MP> "
+CONFIG_CMD_ADTIMG=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LOG=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=-1
+CONFIG_ENV_MMC_USE_DT=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.1"
+CONFIG_STM32_ADC=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK_SCMI=y
+CONFIG_SET_DFU_ALT_INFO=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x02000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
+CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
+CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
+CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
+CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
+CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_STM32=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_STM32_FMC2_EBI=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_STM32_FMC2=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_STMFX=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_DM_REGULATOR_SCMI=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_RESET_SCMI=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_STM32=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_ONBOARD_HUB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=1280
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_ERRNO_STR=y
+# CONFIG_LMB_USE_MAX_REGIONS is not set
+CONFIG_LMB_MEMORY_REGIONS=2
+CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index cda17e5..e3090ec 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -6,7 +6,7 @@
CONFIG_ENV_OFFSET=0x280000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-ev1"
CONFIG_SPL_MMC=y
CONFIG_SPL_STACK=0x30000000
CONFIG_SPL_TEXT_BASE=0x2FFC2500
@@ -81,6 +81,8 @@
CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="st"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index d31349e..5ddec18 100644
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -5,7 +5,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x900000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-ev1"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_DDR_CACHEABLE_SIZE=0x8000000
@@ -54,6 +54,8 @@
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="st"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config
index 7e5b5aa..c841164 100644
--- a/configs/stm32mp15_dhsom.config
+++ b/configs/stm32mp15_dhsom.config
@@ -10,6 +10,9 @@
CONFIG_BOARD_SIZE_LIMIT=1441792
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BOOTDELAY=1
+CONFIG_BOOTRETRY=y
+CONFIG_RESET_TO_RETRY=y
+CONFIG_BOOT_RETRY_TIME=-1
CONFIG_CMD_ADC=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_STBOARD=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 1f807f3..f0e6b64 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -5,7 +5,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x280000
CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-ev1"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
@@ -55,6 +55,8 @@
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="st"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 4538ff0..317a6d5 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -2,17 +2,23 @@
CONFIG_ARCH_STM32MP=y
CONFIG_SYS_MALLOC_F_LEN=0x400000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000
-CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1"
+CONFIG_ENV_OFFSET=0x900000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp257f-ev1"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x84000000
CONFIG_STM32MP25X=y
CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_ENV_OFFSET_REDUND=0x940000
CONFIG_TARGET_ST_STM32MP25X=y
CONFIG_SYS_MEMTEST_START=0x84000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_API=y
+CONFIG_SYS_MMC_MAX_DEVICE=3
CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
-CONFIG_LAST_STAGE_INIT=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
@@ -24,19 +30,38 @@
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
+CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
+CONFIG_CMD_UBI=y
CONFIG_OF_LIVE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
+CONFIG_SYS_MMC_ENV_DEV=-1
CONFIG_NO_NET=y
CONFIG_SYS_64BIT_LBA=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
-# CONFIG_MMC is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_USE_SYS_MAX_FLASH_BANKS=y
+CONFIG_SPI_FLASH=y
CONFIG_PINCONF=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
@@ -44,8 +69,11 @@
# CONFIG_STM32MP1_DDR is not set
CONFIG_DM_RNG=y
CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_WDT_ARM_SMC=y
+# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
CONFIG_ERRNO_STR=y
diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig
index a3b1d76..3bafc4d 100644
--- a/configs/sun8i_a23_evb_defconfig
+++ b/configs/sun8i_a23_evb_defconfig
@@ -5,9 +5,6 @@
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
-CONFIG_USB0_VBUS_PIN="axp_drivebus"
-CONFIG_USB0_VBUS_DET="axp_vbus_detect"
-CONFIG_USB1_VBUS_PIN="PH7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig
index 28cf951..00e34dc 100644
--- a/configs/tanix_tx1_defconfig
+++ b/configs/tanix_tx1_defconfig
@@ -14,11 +14,13 @@
CONFIG_SUNXI_DRAM_H616_LPDDR3=y
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_AXP313_POWER=y
CONFIG_AXP_DCDC3_VOLT=1200
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig
index 9a70b6b..e56bbab 100644
--- a/configs/tbs_a711_defconfig
+++ b/configs/tbs_a711_defconfig
@@ -8,11 +8,10 @@
CONFIG_DRAM_ZQ=15355
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_ID_DET="PH11"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_REGULATOR_AXP_DRIVEVBUS=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig
index b9b22e7..6a9261e 100644
--- a/configs/teres_i_defconfig
+++ b/configs/teres_i_defconfig
@@ -6,7 +6,6 @@
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_I2C0_ENABLE=y
CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start"
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index bd9b611..c062837 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -11,6 +11,7 @@
CONFIG_DRAM_SUNXI_TPR12=0xfedf7557
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst
index 19662be..d72200f 100644
--- a/doc/arch/arm64.rst
+++ b/doc/arch/arm64.rst
@@ -14,11 +14,11 @@
-----
1. U-Boot can run at any exception level it is entered in, it is
- recommened to enter it in EL3 if U-Boot takes some responsibilities of a
+ recommended to enter it in EL3 if U-Boot takes some responsibilities of a
classical firmware (like initial hardware setup, CPU errata workarounds
or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
that of a boot loader. It can drop to lower exception levels before
- entering the OS. For ARMv8-R it is recommened to enter at S-EL1, as for this
+ entering the OS. For ARMv8-R it is recommended to enter at S-EL1, as for this
architecture there is no S-EL3.
2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
diff --git a/doc/board/beagle/am67a_beagley_ai.rst b/doc/board/beagle/am67a_beagley_ai.rst
new file mode 100644
index 0000000..3d2fc4a
--- /dev/null
+++ b/doc/board/beagle/am67a_beagley_ai.rst
@@ -0,0 +1,244 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Nishanth Menon <nm@ti.com>
+
+AM67A Beagleboard.org BeagleY-AI
+================================
+
+Introduction:
+-------------
+
+BeagleBoard.org BeagleY-AI is an easy to use, affordable open source
+hardware single board computer based on the Texas Instruments AM67A,
+which features a quad-core 64-bit Arm CPU subsystem, 2 general-purpose
+digital-signal-processors (DSP) and matrix-multiply-accelerators (MMA),
+GPU, vision and deep learning accelerators, and multiple Arm Cortex-R5
+cores for low-power, low-latency GPIO control.
+
+Further information can be found at:
+
+* Product Page: https://beagley-ai.org/
+* Hardware documentation: https://openbeagle.org/beagley-ai/beagley-ai
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: ../ti/img/boot_diagram_k3_current.svg
+ :alt: Boot flow diagram
+
+- On this platform, 'TI Foundational Security' (TIFS) functions as the
+ security enclave master while 'Device Manager' (DM), also known as the
+ 'TISCI server' in "TI terminology", offers all the essential services.
+ The A53 or R5F (Aux core) sends requests to TIFS/DM to accomplish these
+ services, as illustrated in the diagram above.
+
+Sources:
+--------
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_firmwares
+ :end-before: .. k3_rst_include_end_tifsstub
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. prompt:: bash $
+
+ export UBOOT_CFG_CORTEXR=am67a_beagley_ai_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am67a_beagley_ai_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62x
+
+.. include:: ../ti/j722s_evm.rst
+ :start-after: .. j722s_evm_rst_include_start_build_steps
+ :end-before: .. j722s_evm_rst_include_end_build_steps
+
+Target Images
+-------------
+Copy these images to an SD card and boot:
+
+* tiboot3-j722s-hs-fs-evm.bin from Cortex-R5 build as tiboot3.bin.
+* tispl.bin and u-boot.img from Cortex-A build.
+
+Image formats
+-------------
+
+- tiboot3.bin
+
+.. image:: ../ti/img/multi_cert_tiboot3.bin.svg
+ :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: ../ti/img/tifsstub_dm_tispl.bin.svg
+ :alt: tispl.bin image format
+
+Additional hardware for U-Boot development
+------------------------------------------
+
+* Serial Console is critical for U-Boot development on BeagleY-AI. See
+ `BeagleY-AI serial console documentation
+ <https://docs.beagleboard.org/boards/beagley/ai/02-quick-start.html#beagley-ai-headless>`_.
+* The only onboard storage option is uSD.
+* (optionally) JTAG is useful when working with very early stages of boot.
+
+Flash to uSD card or how to deal with "bricked" Board
+-----------------------------------------------------
+
+The only storage option on the platform is uSD card. However, if you
+choose to hand format your own bootable uSD card, be aware that it can
+be difficult. The following information may be helpful, but remember
+that it is only sometimes reliable, and partition options can cause
+issues. These can potentially help:
+
+* https://git.ti.com/cgit/arago-project/tisdk-setup-scripts/tree/create-sdcard.sh
+* https://elinux.org/Beagleboard:Expanding_File_System_Partition_On_A_microSD
+* Or manually as follows (may not take into distro needs such as EFI or swap):
+
+.. prompt:: bash #
+
+ # Create image with partition table
+ parted --script <SD CARD DEVICE> \
+ mklabel msdos \
+ mkpart primary fat16 4MiB 20MiB \
+ mkpart primary ext4 20MiB 100% \
+ set 1 boot on \
+ set 1 bls_boot off \
+ set 1 lba on
+ # Create boot partition
+ mkfs.vfat <SD CARD DEVICE>1
+ # Create root partition
+ mkfs.ext4 <SD CARD DEVICE>2
+
+The simplest option is to start with a standard distribution
+image like those in `BeagleBoard.org Distros Page
+<https://www.beagleboard.org/distros>`_ and download a disk image for
+BeagleY-AI. Pick a 16GB+ uSD card to be on the safer side.
+
+With an SD/MMC Card reader and `Balena Etcher
+<https://etcher.balena.io/>`_, having a functional setup in minutes is
+a trivial matter, and it works on almost all Host Operating Systems.
+Yes Windows users, Windows Subsystem for Linux(WSL) based development
+with U-Boot and update uSD card is practical.
+
+Updating U-Boot is a matter of copying the tiboot3.bin, tispl.bin and
+u-boot.img to the "BOOT" partition of the uSD card. Remember to sync
+and unmount (or Eject - depending on the Operating System) the uSD
+card prior to physically removing from SD card reader.
+
+.. note::
+ Great news! If the board has not been damaged physically, there's no
+ need to worry about it being "bricked" on this platform. You only have
+ to flash an uSD card, plug it in. This means that even if you make a
+ mistake, you can quickly fix it and rest easy.
+
+ If you are frequently working with uSD cards, you might find the
+ following useful:
+
+ * `USB-SD-Mux <https://www.linux-automation.com/en/products/usb-sd-mux.html>`_
+ * `SD-Wire <https://wiki.tizen.org/SDWire>`_
+
+LED patterns during boot
+------------------------
+
+.. list-table:: LED status indication as system boots up
+ :widths: 16 16
+ :header-rows: 1
+
+ * - LED Color
+ - Indicates
+
+ * - Only RED at startup
+ - Boot failure or R5 image not started up
+
+ * - Steady Green
+ - A53 U-boot has started up
+
+ * - Red/Orange
+ - OS boot process has been initiated
+
+ * - Steady Green
+ - OS boot process failed and drops to U-Boot shell
+
+.. warning ::
+
+ If the "red" power LED is not glowing, the system power supply is not
+ functional. Please refer to `BeagleY-AI documentation
+ <https://beagley-ai.org/>`_ for further information.
+
+A53 SPL DDR Memory Layout
+-------------------------
+
+.. include:: ../ti/j722s_evm.rst
+ :start-after: .. j722s_evm_rst_include_start_ddr_mem_layout
+ :end-before: .. j722s_evm_rst_include_end_ddr_mem_layout
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup and debugging information.
+
+.. warning::
+
+ **OpenOCD support since**: commit 33749a7fbeb5
+
+ If the default package version of OpenOCD in your development
+ environment's distribution needs to be updated, it might be necessary to
+ build OpenOCD from the source.
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_tag_connect
+ :end-before: .. k3_rst_include_end_openocd_connect_tag_connect
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_openocd_cfg_external_intro
+ :end-before: .. k3_rst_include_end_openocd_cfg_external_intro
+
+For example, with BeagleY-AI (J722S/AM67A platform), the openocd_connect.cfg:
+
+.. code-block:: tcl
+
+ # TUMPA example:
+ # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
+ source [find interface/ftdi/tumpa.cfg]
+
+ transport select jtag
+
+ # default JTAG configuration has only SRST and no TRST
+ reset_config srst_only srst_push_pull
+
+ # delay after SRST goes inactive
+ adapter srst delay 20
+
+ if { ![info exists SOC] } {
+ # Set the SoC of interest
+ set SOC j722s
+ }
+
+ source [find target/ti_k3.cfg]
+
+ ftdi tdo_sample_edge falling
+
+ # Speeds for FT2232H are in multiples of 2, and 32MHz is tops
+ # max speed we seem to achieve is ~20MHz.. so we pick 16MHz
+ adapter speed 16000
diff --git a/doc/board/beagle/index.rst b/doc/board/beagle/index.rst
index 9124546..e33d39f 100644
--- a/doc/board/beagle/index.rst
+++ b/doc/board/beagle/index.rst
@@ -11,4 +11,5 @@
:maxdepth: 2
am62x_beagleplay
+ am67a_beagley_ai.rst
j721e_beagleboneai64
diff --git a/doc/board/nxp/imx95_evk.rst b/doc/board/nxp/imx95_evk.rst
new file mode 100644
index 0000000..9121f75
--- /dev/null
+++ b/doc/board/nxp/imx95_evk.rst
@@ -0,0 +1,114 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx95_evk
+=======================
+
+U-Boot for the NXP i.MX95 19x19 EVK board
+
+Quick Start
+-----------
+
+- Get ahab-container.img
+- Get DDR PHY Firmware Images
+- Get and Build OEI Images
+- Get and Build System Manager Image
+- Get and Build the ARM Trusted Firmware
+- Build the Bootloader Image
+- Boot
+
+Get ahab-container.img
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin
+ $ sh firmware-ele-imx-1.3.0-17945fc.bin --auto-accept
+ $ cp firmware-ele-imx-1.3.0-17945fc/mx95a0-ahab-container.img $(srctree)
+
+Get DDR PHY Firmware Images
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.26-d4c33ab.bin
+ $ sh firmware-imx-8.26-d4c33ab.bin --auto-accept
+ $ cp firmware-imx-8.26-d4c33ab/firmware/ddr/synopsys/lpddr5*v202311.bin $(srctree)
+
+Get and Build OEI Images
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get OEI from: https://github.com/nxp-imx/imx-oei
+branch: master
+
+.. code-block:: bash
+
+ $ sudo apt -y install make gcc g++-multilib srecord
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+ $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+ $ export TOOLS=$PWD
+ $ git clone -b master https://github.com/nxp-imx/imx-oei.git
+ $ cd imx-oei
+ $ make board=mx95lp5 oei=ddr DEBUG=1
+ $ cp build/mx95lp5/ddr/oei-m33-ddr.bin $(srctree)
+
+ $ make board=mx95lp5 oei=tcm DEBUG=1
+ $ cp build/mx95lp5/tcm/oei-m33-tcm.bin $(srctree)
+
+Get and Build System Manager Image
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get System Manager from: https://github.com/nxp-imx/imx-sm
+branch: master
+
+.. code-block:: bash
+
+ $ sudo apt -y install make gcc g++-multilib srecord
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+ $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+ $ export TOOLS=$PWD
+ $ git clone -b master https://github.com/nxp-imx/imx-sm.git
+ $ cd imx-sm
+ $ make config=mx95evk all
+ $ cp build/mx95evk/m33_image.bin $(srctree)
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.10
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ unset LDFLAGS
+ $ git clone -b lf_v2.10 https://github.com/nxp-imx/imx-atf.git
+ $ cd imx-atf
+ $ make PLAT=imx95 bl31
+ $ cp build/imx95/release/bl31.bin $(srctree)
+
+Build the Bootloader Image
+--------------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx95_19x19_evk_defconfig
+ $ make
+
+Copy imx-boot-imx95.bin to the MicroSD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
+
+Boot
+----
+
+Set i.MX95 boot device to MicroSD card
diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst
index 8ca4b56..e7ec725 100644
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -15,6 +15,7 @@
imx91_11x11_evk
imx93_9x9_qsb
imx93_11x11_evk
+ imx95_evk
imxrt1020-evk
imxrt1050-evk
imxrt1170-evk
diff --git a/doc/board/starfive/deepcomputing_fml13v01.rst b/doc/board/starfive/deepcomputing_fml13v01.rst
new file mode 100644
index 0000000..5d96124
--- /dev/null
+++ b/doc/board/starfive/deepcomputing_fml13v01.rst
@@ -0,0 +1,80 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+DeepComputing Framework Motherboard (FLM13V01)
+==============================================
+
+The DeepComputing Framework motherboard (FLM13V01) can be combined with a
+13 inch Framework laptop chassis to provide a complete laptop.
+
+U-Boot for the board uses the same binaries as the VisionFive 2 board.
+Currently only serial console output is supported by mainline U-Boot.
+
+Building
+--------
+
+Setup the cross compilation environment variable:
+
+.. code-block:: bash
+
+ export CROSS_COMPILE=riscv64-linux-gnu-
+
+The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
+is responsible for the switch to S-Mode. It is a prerequisite for building
+U-Boot. Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended
+to use a current release.
+
+.. code-block:: bash
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0
+ export OPENSBI="$(pwd)/build/platform/generic/firmware/fw_dynamic.bin"
+
+Now build U-Boot SPL and main U-Boot.
+
+.. code-block:: bash
+
+ cd <U-Boot-dir>
+ make starfive_visionfive2_defconfig
+ make
+
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI, U-Boot, and device-trees.
+
+Device-tree selection
+---------------------
+
+The product ID stored in the board EEPROM is used by U-Boot SPL to select the
+right configuration and device-tree from the u-boot.itb FIT image.
+
+Furthermore if variable $fdtfile has not been saved in the environment it is
+set based on the product ID to *starfive/jh7110-deepcomputing-fml13v01.dtb*.
+
+To overrule this default the variable can be set manually and saved in the
+environment
+
+.. code-block:: console
+
+ setenv fdtfile my_device-tree.dtb
+ env save
+
+Power switch
+------------
+
+A tiny power switch is located in right upper corner of the board.
+
+Open case detection
+-------------------
+
+The board has an open case detection switch. Red lights will flash and the
+board will not boot if the switch is not held down.
+
+UART
+----
+
+UART 0 is exposed via the side channel contacts SBU1 and SBU2 of the lower,
+right USB C connector. A USB C cable and a breakout board are needed for
+physical access. It depends on the cable orientation on which of SBU1 and SBU2
+you will find RX and TX. The signal voltage is 3.3 V. The baud rate is 115200.
+
+.. include:: jh7110_common.rst
diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst
index 2cba1b6..66abc6f 100644
--- a/doc/board/starfive/index.rst
+++ b/doc/board/starfive/index.rst
@@ -6,6 +6,7 @@
.. toctree::
:maxdepth: 1
+ deepcomputing_fml13v01
milk-v_mars
pine64_star64
visionfive2
diff --git a/doc/board/starfive/jh7110_common.rst b/doc/board/starfive/jh7110_common.rst
new file mode 100644
index 0000000..4a8058e
--- /dev/null
+++ b/doc/board/starfive/jh7110_common.rst
@@ -0,0 +1,103 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Boot source selection
+---------------------
+
+The board provides DIP switches to select the device for loading the boot
+firmware.
+
+=========== === ===
+Boot source SW1 SW2
+=========== === ===
+UART OFF OFF
+SD-card ON OFF
+eMMC OFF ON
+SPI flash ON ON
+=========== === ===
+
+Flashing a new U-Boot version
+-----------------------------
+
+U-Boot SPL is provided as file spl/u-boot-spl.bin.normal.out. Main U-Boot is
+in file u-boot.itb.
+
+Assuming your new U-Boot version is on partition 1 of an SD-card you could
+install it to the SPI flash with:
+
+.. code-block:: console
+
+ sf probe
+ load mmc 1:1 $kernel_addr_r u-boot-spl.bin.normal.out
+ sf update $kernel_addr_r 0 $filesize
+ load mmc 1:1 $kernel_addr_r u-boot.itb
+ sf update $kernel_addr_r 0x100000 $filesize
+
+For loading the files from a TFTP server refer to the dhcp and tftpboot
+commands.
+
+After updating U-Boot you may want to erase a saved environment and reboot.
+
+.. code-block:: console
+
+ env erase
+ reset
+
+Booting from SD-Card
+--------------------
+
+The device boot ROM loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
+to choose any partition number.
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+Booting from eMMC
+-----------------
+
+The device boot ROM tries to load U-Boot SPL (u-boot-spl.bin.normal.out) from
+sector 0 of the eMMC's main hardware partition. But this conflicts with GPT
+partitioning. Fortunately eMMC can alternatively load U-Boot SPL from a backup
+position.
+
+For U-Boot SPL (u-boot-spl.bin.normal.out) starting at sector 2048 (position
+0x100000) write the following bytes to the eMMC device after GPT partitioning:
+
+======= ========================
+Address Bytes
+======= ========================
+0x0000 40 02 00 00 00 00 10 00
+0x0290 40 02 00 00 00 00 10 00
+======= ========================
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+Booting from UART
+-----------------
+
+The boot ROM supports the X-modem protocol to upload
+spl/u-boot-spl.bin.normal.out. U-Boot SPL support loading the FIT image
+u-boot.itb via the Y-modem protocol.
+
+Due to restrictions of the boot ROM not all X-modem implementations are
+compatible. The package tio (https://github.com/tio/tio) has been found to be
+usable.
+
+Debug UART
+----------
+
+By default the SBI interface is used for the debug UART. But this only works
+in main U-Boot. To enable the debug UART in SPL, too, use the following
+settings::
+
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_NS16550=y
+ CONFIG_DEBUG_UART_BASE=0x10000000
+ CONFIG_SPL_DEBUG_UART_BASE=0x10000000
+ CONFIG_DEBUG_UART_CLOCK=24000000
+ CONFIG_DEBUG_UART_SHIFT=2
diff --git a/doc/board/starfive/milk-v_mars.rst b/doc/board/starfive/milk-v_mars.rst
index 554932e..ce4539a 100644
--- a/doc/board/starfive/milk-v_mars.rst
+++ b/doc/board/starfive/milk-v_mars.rst
@@ -8,7 +8,7 @@
accordingly.
Building
-~~~~~~~~
+--------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
@@ -40,7 +40,7 @@
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Device-tree selection
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
Depending on the board version U-Boot set variable $fdtfile to either
starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or
@@ -57,15 +57,8 @@
or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
provide a default value.
-Boot source selection
-~~~~~~~~~~~~~~~~~~~~~
-
-The board provides the DIP switches MSEL[1:0] to select the boot device out of
-SPI flash, eMMC, SD-card, UART. To select booting from SD-card set the DIP
-switches MSEL[1:0] to 10.
-
Preparing the SD-Card
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
@@ -105,7 +98,4 @@
sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
-Booting
-~~~~~~~
-
-Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+.. include:: jh7110_common.rst
diff --git a/doc/board/starfive/pine64_star64.rst b/doc/board/starfive/pine64_star64.rst
index 52e9a90..d1752c4 100644
--- a/doc/board/starfive/pine64_star64.rst
+++ b/doc/board/starfive/pine64_star64.rst
@@ -8,7 +8,7 @@
accordingly.
Building
-~~~~~~~~
+--------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
@@ -40,7 +40,7 @@
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Device-tree selection
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
U-Boot will set variable $fdtfile to starfive/jh7110-pine64-star64.dtb.
@@ -55,21 +55,8 @@
or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
provide a default value.
-Boot source selection
-~~~~~~~~~~~~~~~~~~~~~
-
-Boot mode is selected by an MSEL-DIP marked S1804 and GPIO_0 position adjacent
-to the 40pin GPIO header. ON/ONKE and number markings of the MSEL-DIP are
-misleading; Instead refer to the ``L`` (0) and ``H`` (1) silkscreen for
-accurate selection.
-
-+ (QSPI) Flash: 00
-+ SD: 01
-+ EMMC: 10
-+ UART: 11
-
Preparing the SD-Card
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
@@ -109,13 +96,10 @@
sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
-Booting
-~~~~~~~
-
-Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+.. include:: jh7110_common.rst
Serial Number and MAC address issues
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------
U-Boot requires valid EEPROM data to determine which board-specific fix-up to
apply at runtime. This affects the size of memory initialized, network mac
diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
index 2c68df3..11121a1 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -36,7 +36,7 @@
firmware with the latest.
Building
-~~~~~~~~
+--------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
@@ -72,7 +72,7 @@
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Device-tree selection
-~~~~~~~~~~~~~~~~~~~~~
+---------------------
Depending on the board version U-Boot set variable $fdtfile to either
starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or
@@ -90,7 +90,7 @@
a default value.
Flashing
-~~~~~~~~
+--------
The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
@@ -116,6 +116,7 @@
--new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \
--new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
/dev/sdb
+ sudo mkfs.vfat -F32 /dev/sdb3
Program the SD card
@@ -132,16 +133,10 @@
sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
-Booting
-~~~~~~~
-
-The board provides the DIP switches MSEL[1:0] to select the boot device.
-To select booting from SD-card set the DIP switches MSEL[1:0] to 10.
-
-Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+.. include:: jh7110_common.rst
Sample boot log from StarFive VisionFive2 board
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------------
.. code-block:: none
@@ -479,34 +474,3 @@
Welcome to Buildroot
buildroot login:
-
-Booting from SPI
-----------------
-
-Use Building steps from "Booting from MMC using U-Boot SPL" section.
-
-Partition the SPI in Linux via mtdblock. (Require to boot the board in
-SD boot mode by enabling MTD block in Linux)
-
-Use prebuilt image from here [1], which support to partition the SPI flash.
-
-
-Program the SPI (Require to boot the board in SD boot mode)
-
-Execute below steps on U-Boot proper,
-
-.. code-block:: none
-
- sf probe
- fatload mmc 1:3 $kernel_addr_r u-boot.itb
- sf update $kernel_addr_r 0x100000 $filesize
-
- fatload mmc 1:3 $kernel_addr_r u-boot-spl.bin.normal.out
- sf update $kernel_addr_r 0x0 $filesize
-
-
-Power off the board
-
-Change DIP switches MSEL[1:0] are set to 00, select the boot mode to flash
-
-Power up the board.
diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst
index 262340e..43a1db6 100644
--- a/doc/board/ti/am62ax_sk.rst
+++ b/doc/board/ti/am62ax_sk.rst
@@ -81,16 +81,16 @@
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62ax
- $ # we dont use any extra OPTEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62ax
+ # we dont use any extra OPTEE parameters
+ unset OPTEE_EXTRA_ARGS
1. Trusted Firmware-A:
@@ -212,6 +212,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_am62a7evm.cfg
diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst
index 99bdc03..a07d6a4 100644
--- a/doc/board/ti/am62px_sk.rst
+++ b/doc/board/ti/am62px_sk.rst
@@ -91,15 +91,15 @@
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=am62px_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am62px_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62x
- $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+ export UBOOT_CFG_CORTEXR=am62px_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62px_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62x
+ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
.. am62px_evm_rst_include_start_build_steps
@@ -312,6 +312,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_am62pevm.cfg
diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst
index edc29a4..9c53fa5 100644
--- a/doc/board/ti/j722s_evm.rst
+++ b/doc/board/ti/j722s_evm.rst
@@ -68,12 +68,12 @@
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ export OPTEE_PLATFORM=k3-am62x
+ export UBOOT_CFG_CORTEXR=j722s_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig
+ export TFA_BOARD=lite
+ export OPTEE_PLATFORM=k3-am62x
.. j722s_evm_rst_include_start_build_steps
@@ -258,6 +258,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_j722sevm.cfg
diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
index a1e927c..349fb39 100644
--- a/doc/board/ti/j784s4_evm.rst
+++ b/doc/board/ti/j784s4_evm.rst
@@ -81,14 +81,14 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash
- $ export UBOOT_CFG_CORTEXR=j784s4_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j784s4_evm_a72_defconfig
- $ export TFA_BOARD=j784s4
- $ export TFA_EXTRA_ARGS="K3_USART=0x8"
- $ export OPTEE_PLATFORM=k3-j784s4
- $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
+ export UBOOT_CFG_CORTEXR=j784s4_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j784s4_evm_a72_defconfig
+ export TFA_BOARD=j784s4
+ export TFA_EXTRA_ARGS="K3_USART=0x8"
+ export OPTEE_PLATFORM=k3-j784s4
+ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
.. j784s4_evm_rst_include_start_build_steps
@@ -326,6 +326,6 @@
To start OpenOCD and connect to J784S4-EVM or AM69-SK board, use the
following.
-.. code-block:: bash
+.. prompt:: bash
openocd -f board/ti_j784s4evm.cfg
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 0deb4d7..0d9ccd5 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -44,6 +44,7 @@
K3 SoC based boards in other sections
* :doc:`../beagle/am62x_beagleplay`
+* :doc:`../beagle/am67a_beagley_ai`
* :doc:`../beagle/j721e_beagleboneai64`
* :doc:`../phytec/phycore-am62x`
* :doc:`../phytec/phycore-am62ax`
@@ -460,7 +461,7 @@
supports packing multiple images and configurations that allow you to
choose any configuration at runtime to boot from.
-.. code-block::
+.. code-block:: dts
/dts-v1/;
@@ -484,7 +485,7 @@
* Sample Images
-.. code-block::
+.. code-block:: dts
kernel-1 {
description = "Linux kernel";
@@ -533,7 +534,7 @@
* Sample Configurations
-.. code-block::
+.. code-block:: dts
conf-ti_k3-j721e-common-proc-board.dtb {
description = "Linux kernel, FDT blob";
@@ -585,7 +586,7 @@
For e.g
- .. code-block::
+ .. code-block:: diff
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index a5c1df7e0054..6d0126d955ef 100644
@@ -605,7 +606,7 @@
For e.g
- .. code-block::
+ .. code-block:: diff
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
index 673be646b1e3..752fa805fe8d 100644
diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst
index d8fcfdc..480e0e3 100644
--- a/doc/build/gcc.rst
+++ b/doc/build/gcc.rst
@@ -31,7 +31,7 @@
python3-pkg-resources python3-pycryptodome python3-pyelftools \
python3-pytest python3-pytest-xdist python3-sphinxcontrib.apidoc \
python3-sphinx-rtd-theme python3-subunit python3-testtools \
- python3-virtualenv swig uuid-dev
+ python3-venv swig uuid-dev
SUSE based
~~~~~~~~~~
diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst
index 502053f..217ae44 100644
--- a/doc/develop/py_testing.rst
+++ b/doc/develop/py_testing.rst
@@ -69,19 +69,19 @@
`test/py/tests/fs_helper.py` which shall be used in any tests that require
creating disk images.
-Using `virtualenv` to provide requirements
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Using a Python sandbox to provide requirements
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The recommended way to run the test suite, in order to ensure reproducibility
-is to use `virtualenv` to set up the necessary environment. This can be done
-via the following commands:
+is to use a Python sandbox such as `python -m venv` to set up the necessary
+environment. This can be done via the following commands:
.. code-block:: console
$ cd /path/to/u-boot
- $ sudo apt-get install python3 python3-virtualenv
- $ virtualenv -p /usr/bin/python3 venv
+ $ sudo apt-get install python3 python3-venv
+ $ python3 -m venv venv
$ . ./venv/bin/activate
$ pip install -r test/py/requirements.txt
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 50948c0..73b354d 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -55,7 +55,7 @@
* U-Boot v2025.04 was released on Monday, 07 April 2025.
-* The Merge Window for the next release (|next_ver|) is **open** until the -rc1
+* The Merge Window for the next release (|next_ver|) was **closed** with the -rc1
release on Monday, 28 April 2025.
* The next branch is now **closed** until the -rc2 release on Monday, 12 May
@@ -69,9 +69,9 @@
.. The following commented out dates are for when release candidates are
planned to be tagged.
-.. For the next scheduled release, release candidates were made on::
+For the next scheduled release, release candidates were made on::
-.. * U-Boot |next_ver|-rc1 was released on Mon 21 April 2025.
+* U-Boot |next_ver|-rc1 was released on Mon 28 April 2025.
.. * U-Boot |next_ver|-rc2 was released on Mon 12 May 2025.
diff --git a/doc/imx/imx95_container.txt b/doc/imx/imx95_container.txt
new file mode 100644
index 0000000..05f223d
--- /dev/null
+++ b/doc/imx/imx95_container.txt
@@ -0,0 +1,136 @@
+i.MX95 Image Container Format
+-----------------------------
+
+The image container set consists of some image containers, and image container
+contains boot images. Each image container has its own container header which is
+defined in Figure 1. All container headers are placed together in a continuous
+8KB space at the beginning of the image container set - image container set header.
+
+ROM code addresses image containers in image container set one by one based on
+their headers’ order in image container set header.
+
+If ELE container exists, its container header must be the 1st one in the image
+container set header.
+
+If V2X container exists, its container header must be the 2nd one in the image
+container set header. V2X must be combined with ELE container.
+
+The information of boot images are recorded in image container header. System
+ROM code needs to retrieve the information from the image container header, like
+the offset on boot source, the target address in RAM, the length of boot image.
+The order of ROM code handling these boot images is based on the order of each
+boot image information present in image container header.
+
+Figure 1:
+------------------- +--------------+--------------+--------------+--------------+
+ ^ |Tag |Length |Length |Version |
+ | +--------------+--------------+--------------+--------------+
+ | | Flags |
+ | +--------------+--------------+--------------+--------------+
+ | |# of Images |Fuse version |SW version |
+Image | +--------------+--------------+--------------+--------------+
+Container | |Reserved |Signature Block Offset |
+Header | ------- +--------------+--------------+--------------+--------------+
+ | ^ |Image0: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, IV|
+ | | +--------------+--------------+--------------+--------------+
+ | Image | |Image1: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, IV|
+ | Array | +--------------+--------------+--------------+--------------+
+ | | | ... |
+ | | +--------------+--------------+--------------+--------------+
+ v v |ImageN: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, IV|
+------------------- +--------------+--------------+--------------+--------------+
+ | ... |
+ ----------- +--------------+--------------+--------------+--------------+ <-- SignOffset
+ ^ |Tag |Length |Length |Version |
+ | +--------------+--------------+--------------+--------------+
+ | |SRK table offset |Certificate Offset |
+ | +--------------+--------------+--------------+--------------+
+ | |Blob Offset |Signature Offset |
+ | +--------------+--------------+--------------+--------------+
+ Signature | | SRK Table |
+ Block | +--------------+--------------+--------------+--------------+
+ | | Signature |
+ | +--------------+--------------+--------------+--------------+
+ | | Certificate (optional) |
+ | +--------------+--------------+--------------+--------------+
+ v | Blob (optional) |
+ ----------- +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+ <-- Image0Offset
+ | Image0 |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+ <-- ImageNOffset
+ | ImageN |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+
+i.MX95 Low Power Boot Image Sets Layout
+---------------------------------------
+
+ Image container sets are handled by M33 ROM.
+
+ --------------- +--------------+--------------+--------------+--------------+
+ ^ | 1st Container Header |
+ | +--------------+--------------+--------------+--------------+
+ ELE + | | Padding for 1KB alignment |
+ OEM | +--------------+--------------+--------------+--------------+
+ Container | | 2nd Container Header |
+ Set | +--------------+--------------+--------------+--------------+
+ Header | | Padding for 1KB alignment |
+ | +--------------+--------------+--------------+--------------+
+ | | 3rd Container Header |
+ | +--------------+--------------+--------------+--------------+
+ v | Padding for 1KB alignment |
+ --------------- +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+ | mx95a0-ahab-container.img |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+------------------- +--------------+--------------+--------------+--------------+
+ ^ | oei-m33-ddr.bin |
+ | +--------------+--------------+--------------+--------------+
+ | | ddrfw-header.bin |
+ | +--------------+--------------+--------------+--------------+
+ | | lpddr5_imem_v202311.bin |
+ | +--------------+--------------+--------------+--------------+
+m33-oei-ddrfw.bin | | lpddr5_dmem_v202311.bin |
+ | +--------------+--------------+--------------+--------------+
+ | | ddrfw-qb-header.bin |
+ | +--------------+--------------+--------------+--------------+
+ | | lpddr5_imem_qb_v202311.bin |
+ | +--------------+--------------+--------------+--------------+
+ v | lpddr5_dmem_qb_v202311.bin |
+------------------- +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+ | oei-m33-tcm.bin |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+ | m33_image.bin |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+ | u-boot-spl.bin |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+
+ --------------- +--------------+--------------+--------------+--------------+
+ u-boot-atf ^ | 1st Container Header |
+ Container | +--------------+--------------+--------------+--------------+
+ Header v | Padding for 1KB alignment |
+ --------------- +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+ | bl31.bin |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
+ | u-boot.bin |
+ +--------------+--------------+--------------+--------------+
+ | ... |
+ +--------------+--------------+--------------+--------------+
diff --git a/doc/usage/blkmap.rst b/doc/usage/blkmap.rst
index 75f736c..4e9091e 100644
--- a/doc/usage/blkmap.rst
+++ b/doc/usage/blkmap.rst
@@ -39,7 +39,7 @@
dhcp ${ramdisk_addr_r} rootfs.ext4
-But now we are faced with a predicament: how to we extract the kernel
+But now we are faced with a predicament: how do we extract the kernel
image? Block maps to the rescue!
We start by creating a new device:
diff --git a/doc/usage/cmd/md.rst b/doc/usage/cmd/md.rst
index 9a9919f..1eeaa82 100644
--- a/doc/usage/cmd/md.rst
+++ b/doc/usage/cmd/md.rst
@@ -21,7 +21,7 @@
various data sizes and uses the endianness of the target.
The specified data_size and length become the defaults for future memory
-commands commands.
+commands.
address
start address to display
diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst
index e7faecc..e7f6e54 100644
--- a/doc/usage/cmd/part.rst
+++ b/doc/usage/cmd/part.rst
@@ -50,7 +50,7 @@
varname
an optional environment variable to store the list of partitions value into.
-The 'part start' commnad sets an environment variable to the start of the partition (in blocks),
+The 'part start' command sets an environment variable to the start of the partition (in blocks),
part can be either partition number or partition name.
interface
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 4b3d812..bc4d762 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -572,6 +572,9 @@
clk->rate = 0;
list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+ if (device_get_uclass_id(child_dev) != UCLASS_CLK)
+ continue;
+
clkp = dev_get_clk_ptr(child_dev);
clk_clean_rate_cache(clkp);
}
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index e42d203..af69850 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -8,10 +8,59 @@
#include <clk-uclass.h>
#include <dm.h>
#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
#include <asm/types.h>
#include <linux/clk-provider.h>
+struct clk_scmi {
+ struct clk clk;
+ u32 ctrl_flags;
+};
+
+struct scmi_clock_priv {
+ u32 version;
+};
+
+static int scmi_clk_get_permissions(struct udevice *dev, int clkid, u32 *perm)
+{
+ struct scmi_clock_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ struct scmi_clk_get_permissions_in in = {
+ .clock_id = clkid,
+ };
+ struct scmi_clk_get_permissions_out out;
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_CLOCK,
+ .message_id = SCMI_CLOCK_GET_PERMISSIONS,
+ .in_msg = (u8 *)&in,
+ .in_msg_sz = sizeof(in),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+
+ if (priv->version < CLOCK_PROTOCOL_VERSION_3_0) {
+ log_debug("%s: SCMI clock management protocol version is less than 3.0.\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret) {
+ log_debug("%s: get SCMI clock management protocol permissions failed\n", __func__);
+ return ret;
+ }
+
+ ret = scmi_to_linux_errno(out.status);
+ if (ret < 0) {
+ log_debug("%s: the status code of getting permissions: %d\n", __func__, ret);
+ return ret;
+ }
+
+ *perm = out.permissions;
+ return 0;
+}
+
static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
{
struct scmi_clk_protocol_attr_out out;
@@ -32,7 +81,8 @@
return 0;
}
-static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
+static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name,
+ u32 *attr)
{
struct scmi_clk_attribute_in in = {
.clock_id = clkid,
@@ -53,6 +103,7 @@
return ret;
*name = strdup(out.clock_name);
+ *attr = out.attributes;
return 0;
}
@@ -78,12 +129,48 @@
static int scmi_clk_enable(struct clk *clk)
{
- return scmi_clk_gate(clk, 1);
+ struct clk_scmi *clkscmi;
+ struct clk *c;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(CLK_CCF))
+ return scmi_clk_gate(clk, 1);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ clkscmi = container_of(c, struct clk_scmi, clk);
+
+ if (clkscmi->ctrl_flags & SUPPORT_CLK_STAT_CONTROL)
+ return scmi_clk_gate(clk, 1);
+
+ /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
+ log_debug("%s: SCMI CLOCK: the clock cannot be enabled by the agent.\n", __func__);
+ return 0;
}
static int scmi_clk_disable(struct clk *clk)
{
- return scmi_clk_gate(clk, 0);
+ struct clk_scmi *clkscmi;
+ struct clk *c;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(CLK_CCF))
+ return scmi_clk_gate(clk, 0);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ clkscmi = container_of(c, struct clk_scmi, clk);
+
+ if (clkscmi->ctrl_flags & SUPPORT_CLK_STAT_CONTROL)
+ return scmi_clk_gate(clk, 0);
+
+ /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
+ log_debug("%s: SCMI CLOCK: the clock cannot be disabled by the agent.\n", __func__);
+ return 0;
}
static ulong scmi_clk_get_rate(struct clk *clk)
@@ -108,7 +195,7 @@
return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb);
}
-static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
+static ulong __scmi_clk_set_rate(struct clk *clk, ulong rate)
{
struct scmi_clk_rate_set_in in = {
.clock_id = clk->id,
@@ -133,9 +220,33 @@
return scmi_clk_get_rate(clk);
}
+static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_scmi *clkscmi;
+ struct clk *c;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(CLK_CCF))
+ return __scmi_clk_set_rate(clk, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ clkscmi = container_of(c, struct clk_scmi, clk);
+
+ if (clkscmi->ctrl_flags & SUPPORT_CLK_RATE_CONTROL)
+ return __scmi_clk_set_rate(clk, rate);
+
+ /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
+ log_debug("%s: SCMI CLOCK: the clock rate cannot be changed by the agent.\n", __func__);
+ return 0;
+}
+
static int scmi_clk_probe(struct udevice *dev)
{
- struct clk *clk;
+ struct clk_scmi *clk_scmi;
+ struct scmi_clock_priv *priv = dev_get_priv(dev);
size_t num_clocks, i;
int ret;
@@ -153,28 +264,90 @@
ret = scmi_clk_get_num_clock(dev, &num_clocks);
if (ret)
return ret;
+
+ ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_CLOCK, &priv->version);
+ if (ret) {
+ log_debug("%s: get SCMI clock management protocol version failed\n", __func__);
+ return ret;
+ }
for (i = 0; i < num_clocks; i++) {
char *clock_name;
+ u32 attributes;
- if (!scmi_clk_get_attibute(dev, i, &clock_name)) {
- clk = kzalloc(sizeof(*clk), GFP_KERNEL);
- if (!clk || !clock_name)
+ if (!scmi_clk_get_attibute(dev, i, &clock_name, &attributes)) {
+ clk_scmi = kzalloc(sizeof(*clk_scmi), GFP_KERNEL);
+ if (!clk_scmi || !clock_name)
ret = -ENOMEM;
else
- ret = clk_register(clk, dev->driver->name,
+ ret = clk_register(&clk_scmi->clk, dev->driver->name,
clock_name, dev->name);
if (ret) {
- free(clk);
+ free(clk_scmi);
free(clock_name);
return ret;
}
+ clk_dm(i, &clk_scmi->clk);
+
+ if (CLK_HAS_RESTRICTIONS(attributes)) {
+ u32 perm;
+
- clk_dm(i, clk);
+ ret = scmi_clk_get_permissions(dev, i, &perm);
+ if (ret < 0)
+ clk_scmi->ctrl_flags = 0;
+ else
+ clk_scmi->ctrl_flags = perm;
+ } else {
+ clk_scmi->ctrl_flags = SUPPORT_CLK_STAT_CONTROL | SUPPORT_CLK_PARENT_CONTROL |
+ SUPPORT_CLK_RATE_CONTROL;
+ }
}
}
+ return 0;
+}
+
+static int __scmi_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct scmi_clk_parent_set_in in = {
+ .clock_id = clk->id,
+ .parent_clk = parent->id,
+ };
+ struct scmi_clk_parent_set_out out;
+ struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_CLOCK_PARENT_SET,
+ in, out);
+ int ret;
+
+ ret = devm_scmi_process_msg(clk->dev, &msg);
+ if (ret < 0)
+ return ret;
+
+ return scmi_to_linux_errno(out.status);
+}
+
+static int scmi_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_scmi *clkscmi;
+ struct clk *c;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(CLK_CCF))
+ return -ENOTSUPP;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ clkscmi = container_of(c, struct clk_scmi, clk);
+
+ if (clkscmi->ctrl_flags & SUPPORT_CLK_PARENT_CONTROL)
+ return __scmi_clk_set_parent(clk, parent);
+
+ /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
+ log_debug("%s: SCMI CLOCK: the clock's parent cannot be changed by the agent.\n", __func__);
return 0;
}
@@ -183,6 +356,7 @@
.disable = scmi_clk_disable,
.get_rate = scmi_clk_get_rate,
.set_rate = scmi_clk_set_rate,
+ .set_parent = scmi_clk_set_parent,
};
U_BOOT_DRIVER(scmi_clock) = {
@@ -190,4 +364,12 @@
.id = UCLASS_CLK,
.ops = &scmi_clk_ops,
.probe = scmi_clk_probe,
+ .priv_auto = sizeof(struct scmi_clock_priv),
};
+
+static struct scmi_proto_match match[] = {
+ { .proto_id = SCMI_PROTOCOL_ID_CLOCK },
+ { /* Sentinel */ }
+};
+
+U_BOOT_SCMI_PROTO_DRIVER(scmi_clock, match);
diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c
index 1326b77..fad104f 100644
--- a/drivers/clk/qcom/clock-qcm2290.c
+++ b/drivers/clk/qcom/clock-qcm2290.c
@@ -88,7 +88,7 @@
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
const struct freq_tbl *freq;
- debug("%s: clk %s rate %lu\n", __func__, clk->dev->name, rate);
+ debug("%s: clk %s rate %lu\n", __func__, qcm2290_clks[clk->id].name, rate);
switch (clk->id) {
case GCC_QUPV3_WRAP0_S4_CLK: /*UART2*/
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 4044edf..9cb69a0 100644
--- a/drivers/clk/stm32/clk-stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
@@ -551,6 +551,7 @@
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI, _DSI_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 4e1ecca..4836bdd 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -111,6 +111,8 @@
return "91(11)";/* iMX91 9x9 Reduced feature */
case MXC_CPU_IMX9101:
return "91(01)";/* iMX91 9x9 Specific feature */
+ case MXC_CPU_IMX95:
+ return "95";
default:
return "??";
}
diff --git a/drivers/firmware/scmi/base.c b/drivers/firmware/scmi/base.c
index f4e3974..78ee2ff 100644
--- a/drivers/firmware/scmi/base.c
+++ b/drivers/firmware/scmi/base.c
@@ -258,7 +258,7 @@
static int scmi_base_discover_list_protocols_int(struct udevice *dev,
u8 **protocols)
{
- struct scmi_base_discover_list_protocols_out out;
+ struct scmi_base_discover_list_protocols_out *out;
int cur;
struct scmi_msg msg = {
.protocol_id = SCMI_PROTOCOL_ID_BASE,
@@ -268,7 +268,7 @@
.out_msg = (u8 *)&out,
.out_msg_sz = sizeof(out),
};
- u32 num_agents, num_protocols;
+ u32 num_agents, num_protocols, out_size;
u8 *buf;
int i, ret;
@@ -276,22 +276,31 @@
if (ret)
return ret;
+ out_size = sizeof(*out) + sizeof(u32) * (1 + num_protocols / 4);
+ out = calloc(1, out_size);
+ if (!out)
+ return -ENOMEM;
+ msg.out_msg = (u8 *)out;
+ msg.out_msg_sz = out_size;
+
buf = calloc(sizeof(u8), num_protocols);
- if (!buf)
+ if (!buf) {
+ free(out);
return -ENOMEM;
+ }
cur = 0;
do {
ret = devm_scmi_process_msg(dev, &msg);
if (ret)
goto err;
- if (out.status) {
- ret = scmi_to_linux_errno(out.status);
+ if (out->status) {
+ ret = scmi_to_linux_errno(out->status);
goto err;
}
- for (i = 0; i < out.num_protocols; i++, cur++)
- buf[cur] = out.protocols[i / 4] >> ((i % 4) * 8);
+ for (i = 0; i < out->num_protocols; i++, cur++)
+ buf[cur] = out->protocols[i / 4] >> ((i % 4) * 8);
} while (cur < num_protocols);
*protocols = buf;
@@ -299,6 +308,7 @@
return num_protocols;
err:
free(buf);
+ free(out);
return ret;
}
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c
index 19be280..74a8783 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c
@@ -80,9 +80,9 @@
};
static struct sandbox_scmi_clk scmi_clk[] = {
- { .rate = 333 },
- { .rate = 200 },
- { .rate = 1000 },
+ { .rate = 333, .perm = 0xE0000000 },
+ { .rate = 200, .perm = 0xE0000000 },
+ { .rate = 1000, .perm = 0xE0000000 },
};
static struct sandbox_scmi_reset scmi_reset[] = {
@@ -700,6 +700,21 @@
/* Clock Protocol */
+static int sandbox_scmi_clock_protocol_version(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_protocol_version_out *out = NULL;
+
+ if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ out = (struct scmi_protocol_version_out *)msg->out_msg;
+ out->version = 0x30000;
+ out->status = SCMI_SUCCESS;
+
+ return 0;
+}
+
static int sandbox_scmi_clock_protocol_attribs(struct udevice *dev,
struct scmi_msg *msg)
{
@@ -740,6 +755,9 @@
if (clk_state->enabled)
out->attributes = 1;
+ /* Restricted clock */
+ out->attributes |= BIT(1);
+
ret = snprintf(out->clock_name, sizeof(out->clock_name),
"clk%u", in->clock_id);
assert(ret > 0 && ret < sizeof(out->clock_name));
@@ -837,6 +855,34 @@
return 0;
}
+static int sandbox_scmi_clock_permissions_get(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+ struct scmi_clk_get_permissions_in *in = NULL;
+ struct scmi_clk_get_permissions_out *out = NULL;
+ struct sandbox_scmi_clk *clk_state = NULL;
+
+ if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+ !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+ return -EINVAL;
+
+ in = (struct scmi_clk_get_permissions_in *)msg->in_msg;
+ out = (struct scmi_clk_get_permissions_out *)msg->out_msg;
+
+ clk_state = get_scmi_clk_state(in->clock_id);
+ if (!clk_state) {
+ dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
+
+ out->status = SCMI_NOT_FOUND;
+ } else {
+ out->permissions = clk_state->perm;
+
+ out->status = SCMI_SUCCESS;
+ }
+
+ return 0;
+}
+
static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg)
{
struct scmi_rd_attr_in *in = NULL;
@@ -1193,6 +1239,8 @@
return sandbox_proto_not_supported(msg);
switch (msg->message_id) {
+ case SCMI_PROTOCOL_VERSION:
+ return sandbox_scmi_clock_protocol_version(dev, msg);
case SCMI_PROTOCOL_ATTRIBUTES:
return sandbox_scmi_clock_protocol_attribs(dev, msg);
case SCMI_CLOCK_ATTRIBUTES:
@@ -1203,6 +1251,8 @@
return sandbox_scmi_clock_rate_get(dev, msg);
case SCMI_CLOCK_CONFIG_SET:
return sandbox_scmi_clock_gate(dev, msg);
+ case SCMI_CLOCK_GET_PERMISSIONS:
+ return sandbox_scmi_clock_permissions_get(dev, msg);
default:
break;
}
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index e6e43ae..e7ec2c1 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -97,6 +97,9 @@
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
proto = priv->voltagedom_dev;
break;
+ case SCMI_PROTOCOL_ID_PINCTRL:
+ proto = priv->pinctrl_dev;
+ break;
default:
dev_err(dev, "Protocol not supported\n");
proto = NULL;
@@ -147,6 +150,9 @@
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
priv->voltagedom_dev = proto;
break;
+ case SCMI_PROTOCOL_ID_PINCTRL:
+ priv->pinctrl_dev = proto;
+ break;
default:
dev_err(dev, "Protocol not supported\n");
return -EPROTO;
@@ -352,6 +358,22 @@
return 0;
}
+static struct driver *scmi_proto_driver_get(unsigned int proto_id)
+{
+ struct scmi_proto_driver *start, *entry;
+ int n_ents;
+
+ start = ll_entry_start(struct scmi_proto_driver, scmi_proto_driver);
+ n_ents = ll_entry_count(struct scmi_proto_driver, scmi_proto_driver);
+
+ for (entry = start; entry != start + n_ents; entry++) {
+ if (entry->match->proto_id == proto_id)
+ return entry->driver;
+ }
+
+ return NULL;
+}
+
/*
* SCMI agent devices binds devices of various uclasses depending on
* the FDT description. scmi_bind_protocol() is a generic bind sequence
@@ -409,31 +431,11 @@
drv = NULL;
name = ofnode_get_name(node);
- switch (protocol_id) {
- case SCMI_PROTOCOL_ID_POWER_DOMAIN:
- if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN) &&
- scmi_protocol_is_supported(dev, protocol_id))
- drv = DM_DRIVER_GET(scmi_power_domain);
- break;
- case SCMI_PROTOCOL_ID_CLOCK:
- if (CONFIG_IS_ENABLED(CLK_SCMI) &&
- scmi_protocol_is_supported(dev, protocol_id))
- drv = DM_DRIVER_GET(scmi_clock);
- break;
- case SCMI_PROTOCOL_ID_RESET_DOMAIN:
- if (IS_ENABLED(CONFIG_RESET_SCMI) &&
- scmi_protocol_is_supported(dev, protocol_id))
- drv = DM_DRIVER_GET(scmi_reset_domain);
- break;
- case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
- if (IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) &&
- scmi_protocol_is_supported(dev, protocol_id))
- drv = DM_DRIVER_GET(scmi_voltage_domain);
- break;
- default:
- break;
- }
+
+ if (!scmi_protocol_is_supported(dev, protocol_id))
+ continue;
+ drv = scmi_proto_driver_get(protocol_id);
if (!drv) {
dev_dbg(dev, "Ignore unsupported SCMI protocol %#x\n",
protocol_id);
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 54d6689..344df94 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -2845,11 +2845,11 @@
info->dev = dev;
info->seq = 0xA;
+ INIT_LIST_HEAD(&info->dev_list);
+
list_add_tail(&info->list, &ti_sci_list);
ti_sci_setup_ops(info);
- INIT_LIST_HEAD(&info->dev_list);
-
if (IS_ENABLED(CONFIG_SYSRESET_TI_SCI)) {
ret = device_bind_driver(dev, "ti-sci-sysreset", "sysreset", NULL);
if (ret)
@@ -2889,6 +2889,8 @@
info->dev = dev;
info->seq = 0xA;
+ INIT_LIST_HEAD(&info->dev_list);
+
list_add_tail(&info->list, &ti_sci_list);
ops = &info->handle.ops;
diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
index 6e632c8..181c53b 100644
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -15,6 +15,9 @@
#include <errno.h>
#include <sunxi_gpio.h>
+#define AXP_GPIO_PREFIX "AXP0-"
+#define AXP_GPIO_COUNT 4
+
static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
static u8 axp_get_gpio_ctrl_reg(unsigned pin)
@@ -46,28 +49,14 @@
static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
int val)
{
- __maybe_unused int ret;
u8 reg;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_clrbits(AXP_MISC_CTRL,
- AXP_MISC_CTRL_N_VBUSEN_FUNC);
- if (ret)
- return ret;
-
- return axp_gpio_set_value(dev, pin, val);
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
- AXP_GPIO_CTRL_OUTPUT_LOW);
- }
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
}
static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
@@ -75,25 +64,16 @@
u8 reg, val, mask;
int ret;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val);
- mask = AXP_VBUS_IPSOUT_DRIVEBUS;
- break;
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- ret = pmic_bus_read(AXP_GPIO_STATE, &val);
- mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
- }
+ ret = pmic_bus_read(AXP_GPIO_STATE, &val);
if (ret)
return ret;
+ mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
+
return (val & mask) ? 1 : 0;
}
@@ -101,25 +81,12 @@
{
u8 reg;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- if (val)
- return pmic_bus_setbits(AXP_VBUS_IPSOUT,
- AXP_VBUS_IPSOUT_DRIVEBUS);
- else
- return pmic_bus_clrbits(AXP_VBUS_IPSOUT,
- AXP_VBUS_IPSOUT_DRIVEBUS);
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
- AXP_GPIO_CTRL_OUTPUT_LOW);
- }
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
}
static const struct dm_gpio_ops gpio_axp_ops = {
@@ -134,8 +101,8 @@
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Tell the uclass how many GPIOs we have */
- uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX);
- uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT;
+ uc_priv->bank_name = AXP_GPIO_PREFIX;
+ uc_priv->gpio_count = AXP_GPIO_COUNT;
return 0;
}
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 2ca4960..094c45a 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -244,17 +244,7 @@
int sunxi_name_to_gpio(const char *name)
{
unsigned int gpio;
- int ret;
-#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO
- char lookup[8];
-
- if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
- sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
- SUNXI_GPIO_AXP0_VBUS_ENABLE);
- name = lookup;
- }
-#endif
- ret = gpio_lookup_name(name, NULL, NULL, &gpio);
+ int ret = gpio_lookup_name(name, NULL, NULL, &gpio);
return ret ? ret : gpio;
}
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index 1cad51d..3ac690a 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -15,7 +15,6 @@
#include <log.h>
#include <os.h>
#include <u-boot/sha256.h>
-#include <spi.h>
#include <time.h>
#include <asm/malloc.h>
#include <asm/state.h>
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 951e6ac..06c1e09 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -478,29 +478,29 @@
static int mmc_resource_init(int sdc_no)
{
struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *ccm = (void *)SUNXI_CCM_BASE;
debug("init mmc %d resource\n", sdc_no);
switch (sdc_no) {
case 0:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
- priv->mclkreg = &ccm->sd0_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC0_CLK_CFG;
break;
case 1:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
- priv->mclkreg = &ccm->sd1_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC1_CLK_CFG;
break;
#ifdef SUNXI_MMC2_BASE
case 2:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
- priv->mclkreg = &ccm->sd2_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC2_CLK_CFG;
break;
#endif
#ifdef SUNXI_MMC3_BASE
case 3:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
- priv->mclkreg = &ccm->sd3_clk_cfg;
+ priv->mclkreg = ccm + CCU_MMC3_CLK_CFG;
break;
#endif
default:
@@ -545,7 +545,7 @@
struct mmc *sunxi_mmc_init(int sdc_no)
{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ void *ccm = (void *)SUNXI_CCM_BASE;
struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
struct mmc_config *cfg = &priv->cfg;
int ret;
@@ -574,11 +574,11 @@
/* config ahb clock */
debug("init mmc %d clock and io\n", sdc_no);
#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2)
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
+ setbits_le32(ccm + CCU_AHB_GATE0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
#ifdef CONFIG_SUNXI_GEN_SUN6I
/* unassert reset */
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+ setbits_le32(ccm + CCU_AHB_RESET0_CFG, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
#endif
#if defined(CONFIG_MACH_SUN9I)
/* sun9i has a mmc-common module, also set the gate and reset there */
@@ -586,9 +586,9 @@
SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
#endif
#else /* CONFIG_SUN50I_GEN_H6 */
- setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
+ setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << sdc_no);
/* unassert reset */
- setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
+ setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << (RESET_SHIFT + sdc_no));
#endif
ret = mmc_set_mod_clk(priv, 24000000);
if (ret)
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 3f8edeb..842d3e7 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -236,6 +236,10 @@
if (ret)
return ret;
+ if (parts[idx].offset == MTD_OFFSET_NOT_SPECIFIED)
+ parts[idx].offset = cur_off;
+ cur_off += parts[idx].size;
+
if (parts[idx].size == MTD_SIZE_REMAINING)
parts[idx].size = parent->size - parts[idx].offset;
@@ -246,10 +250,6 @@
return -EINVAL;
}
- if (parts[idx].offset == MTD_OFFSET_NOT_SPECIFIED)
- parts[idx].offset = cur_off;
- cur_off += parts[idx].size;
-
parts[idx].ecclayout = parent->ecclayout;
}
@@ -909,11 +909,13 @@
continue;
offset = ofnode_get_addr_size_index_notrans(child, 0, &size);
- if (offset == FDT_ADDR_T_NONE || !size) {
- debug("Missing partition offset/size on \"%s\" partition\n",
+ if (offset == FDT_ADDR_T_NONE) {
+ debug("Missing partition offset on \"%s\" partition\n",
master->name);
continue;
}
+ if (size == MTDPART_SIZ_FULL)
+ size = master->size - offset;
part.name = ofnode_read_string(child, "label");
if (!part.name)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6f352c5..655bf3a 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -655,7 +655,7 @@
return mtd->priv;
}
-#ifndef CONFIG_SPI_FLASH_BAR
+#if !CONFIG_IS_ENABLED(SPI_FLASH_BAR)
static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
{
size_t i;
@@ -739,7 +739,7 @@
nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
}
-#endif /* !CONFIG_SPI_FLASH_BAR */
+#endif /* !CONFIG_IS_ENABLED(SPI_FLASH_BAR) */
/* Enable/disable 4-byte addressing mode. */
static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
@@ -930,7 +930,7 @@
return spi_nor_wait_till_ready_with_timeout(nor, timeout);
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
/*
* This "clean_bar" is necessary in a situation when one was accessing
* spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
@@ -944,6 +944,7 @@
static int clean_bar(struct spi_nor *nor)
{
u8 cmd, bank_sel = 0;
+ int ret;
if (nor->bank_curr == 0)
return 0;
@@ -951,7 +952,11 @@
nor->bank_curr = 0;
write_enable(nor);
+ ret = nor->write_reg(nor, cmd, &bank_sel, 1);
+ if (ret)
+ return ret;
+
- return nor->write_reg(nor, cmd, &bank_sel, 1);
+ return write_disable(nor);
}
static int write_bar(struct spi_nor *nor, u32 offset)
@@ -1141,7 +1146,7 @@
nor->spi->flags &= ~SPI_XFER_U_PAGE;
}
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
goto erase_err;
@@ -1175,7 +1180,7 @@
addr_known = false;
erase_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
err = clean_bar(nor);
if (!ret)
ret = err;
@@ -1272,6 +1277,10 @@
if (ret)
return ret;
+ ret = write_disable(nor);
+ if (ret)
+ return ret;
+
ret = read_sr(nor);
if (ret < 0)
return ret;
@@ -1630,7 +1639,7 @@
offset /= 2;
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
return log_ret(ret);
@@ -1667,7 +1676,7 @@
ret = 0;
read_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = clean_bar(nor);
#endif
return ret;
@@ -1809,13 +1818,18 @@
if (ctl == SST26_CTL_CHECK)
return 0;
+ /* Write latch enable before write operation */
+ ret = write_enable(nor);
+ if (ret)
+ return ret;
+
ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
if (ret < 0) {
dev_err(nor->dev, "fail to write block-protection register\n");
return ret;
}
- return 0;
+ return write_disable(nor);
}
static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
@@ -2016,7 +2030,7 @@
}
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
return ret;
@@ -2090,7 +2104,7 @@
}
write_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = clean_bar(nor);
#endif
return ret;
@@ -2217,7 +2231,7 @@
return ret;
}
- return 0;
+ return write_disable(nor);
}
/**
@@ -3592,6 +3606,19 @@
mtd->erasesize = info->sector_size;
}
+ if ((JEDEC_MFR(info) == SNOR_MFR_SST) && info->flags & SECT_4K) {
+ nor->erase_opcode = SPINOR_OP_BE_4K;
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->erasesize = 4096 * 2;
+ else
+ mtd->erasesize = 4096;
+ }
+
return 0;
}
@@ -3791,7 +3818,7 @@
int ret;
u8 cr;
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
return -ENOTSUPP; /* Bank Address Register is not supported */
#endif
/*
@@ -4123,6 +4150,12 @@
params->rdsr_addr_nbytes = 0;
/*
+ * SCCR Map 22nd DWORD does not indicate DTR Octal Mode Enable
+ * for MT35XU512ABA but is actually supported by device.
+ */
+ nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
+
+ /*
* The BFPT quad enable field is set to a reserved value so the quad
* enable function is ignored by spi_nor_parse_bfpt(). Make sure we
* disable it.
@@ -4286,6 +4319,9 @@
write_disable(nor);
}
}
+ err = write_disable(nor);
+ if (err)
+ return err;
}
if (nor->quad_enable) {
@@ -4577,7 +4613,7 @@
if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED))
shift = 1;
if (nor->addr_width == 3 && (mtd->size >> shift) > SZ_16M) {
-#ifndef CONFIG_SPI_FLASH_BAR
+#if !CONFIG_IS_ENABLED(SPI_FLASH_BAR)
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 91ae49c..e7e9778 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -358,10 +358,13 @@
#ifdef CONFIG_SPI_FLASH_MT35XU
{ INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
- { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
- { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
- { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
+ { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least
@@ -414,8 +417,10 @@
{ INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_S28HX_T
+ { INFO("s28hl256t", 0x345a19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("s28hl02gt", 0x345a1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | NO_CHIP_ERASE) },
{ INFO("s28hs256t", 0x345b19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 50e4392..4881287 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -1152,10 +1152,10 @@
ubi_wl_close(ubi);
ubi_free_internal_volumes(ubi);
vfree(ubi->vtbl);
- put_mtd_device(ubi->mtd);
vfree(ubi->peb_buf);
vfree(ubi->fm_buf);
ubi_msg(ubi, "mtd%d is detached", ubi->mtd->index);
+ put_mtd_device(ubi->mtd);
put_device(&ubi->dev);
return 0;
}
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4434d36..950ed0f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -860,7 +860,7 @@
select PHY_ETHERNET_ID
help
This driver implements support for the Ethernet AVB block in
- Renesas M3 and H3 SoCs.
+ several Renesas R-Car and RZ SoCs.
config MPC8XX_FEC
bool "Fast Ethernet Controller on MPC8XX"
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 0cfe093..551ee0e 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1599,6 +1599,10 @@
.compatible = "st,stm32mp1-dwmac",
.data = (ulong)&eqos_stm32mp15_config
},
+ {
+ .compatible = "st,stm32mp25-dwmac",
+ .data = (ulong)&eqos_stm32mp25_config
+ },
#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
{
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 403e820..c239a5c 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -301,5 +301,6 @@
extern struct eqos_config eqos_qcom_config;
extern struct eqos_config eqos_stm32mp13_config;
extern struct eqos_config eqos_stm32mp15_config;
+extern struct eqos_config eqos_stm32mp25_config;
extern struct eqos_config eqos_jh7110_config;
extern struct eqos_config eqos_adi_config;
diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index f3a973f..7a28f2a 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -350,3 +350,14 @@
.interface = dev_read_phy_mode,
.ops = &eqos_stm32_ops
};
+
+struct eqos_config __maybe_unused eqos_stm32mp25_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 10000,
+ .swr_wait = 50,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+ .axi_bus_width = EQOS_AXI_WIDTH_64,
+ .interface = dev_read_phy_mode,
+ .ops = &eqos_stm32_ops
+};
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index b772980..1c8767d 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -121,6 +121,7 @@
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_IT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_V) },
{}
};
@@ -1588,6 +1589,7 @@
case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
case PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED:
case PCI_DEVICE_ID_INTEL_I225_IT:
+ case PCI_DEVICE_ID_INTEL_I225_V:
hw->mac_type = e1000_igb;
break;
default:
@@ -4852,6 +4854,7 @@
hw->phy_type = e1000_phy_igb;
break;
case I225_I_PHY_ID:
+ case I225_V_PHY_ID:
case I226_LM_PHY_ID:
case I226_I_PHY_ID:
hw->phy_type = e1000_phy_igc;
@@ -4965,6 +4968,8 @@
match = true;
if (hw->phy_id == I225_I_PHY_ID)
match = true;
+ if (hw->phy_id == I225_V_PHY_ID)
+ match = true;
if (hw->phy_id == I226_LM_PHY_ID)
match = true;
if (hw->phy_id == I226_I_PHY_ID)
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 5ca720f..cf8bd75 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -2420,6 +2420,7 @@
#define I226_LM_PHY_ID 0x67C9DC10
#define I225_I_PHY_ID 0x67C9DCC0
#define I226_I_PHY_ID 0x67C9DCD0
+#define I225_V_PHY_ID 0x67C9DC00
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 539fd37..6852886 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -23,6 +23,7 @@
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
+#include <reset.h>
/* Registers */
#define RAVB_REG_CCC 0x000
@@ -30,6 +31,7 @@
#define RAVB_REG_CSR 0x00C
#define RAVB_REG_APSR 0x08C
#define RAVB_REG_RCR 0x090
+#define RAVB_REG_RTC 0x0B4
#define RAVB_REG_TGC 0x300
#define RAVB_REG_TCCR 0x304
#define RAVB_REG_RIC0 0x360
@@ -43,6 +45,7 @@
#define RAVB_REG_GECMR 0x5b0
#define RAVB_REG_MAHR 0x5c0
#define RAVB_REG_MALR 0x5c8
+#define RAVB_REG_CSR0 0x800
#define CCC_OPC_CONFIG BIT(0)
#define CCC_OPC_OPERATION BIT(1)
@@ -64,14 +67,24 @@
#define PIR_MDC BIT(0)
#define ECMR_TRCCM BIT(26)
+#define ECMR_RCPT BIT(25)
#define ECMR_RZPF BIT(20)
#define ECMR_PFR BIT(18)
#define ECMR_RXF BIT(17)
+#define ECMR_TXF BIT(16)
#define ECMR_RE BIT(6)
#define ECMR_TE BIT(5)
#define ECMR_DM BIT(1)
+#define ECMR_PRM BIT(0)
#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
+#define CSR0_RPE BIT(5)
+#define CSR0_TPE BIT(4)
+
+#define GECMR_SPEED_10M (0 << 4)
+#define GECMR_SPEED_100M (1 << 4)
+#define GECMR_SPEED_1G (2 << 4)
+
/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC 16
#define RAVB_NUM_TX_DESC 8
@@ -107,6 +120,13 @@
#define RAVB_TX_TIMEOUT_MS 1000
+struct ravb_device_ops {
+ void (*mac_init)(struct udevice *dev);
+ void (*dmac_init)(struct udevice *dev);
+ void (*config)(struct udevice *dev);
+ bool has_reset;
+};
+
struct ravb_desc {
u32 ctrl;
u32 dptr;
@@ -130,6 +150,7 @@
struct mii_dev *bus;
void __iomem *iobase;
struct clk_bulk clks;
+ struct reset_ctl rst;
};
static inline void ravb_flush_dcache(u32 addr, u32 len)
@@ -181,7 +202,7 @@
{
struct ravb_priv *eth = dev_get_priv(dev);
struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
- int len;
+ int len = 0;
u8 *packet;
/* Check if the rx descriptor is ready */
@@ -190,12 +211,11 @@
return -EAGAIN;
/* Check for errors */
- if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
+ if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK)
desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
- return -EAGAIN;
- }
+ else
+ len = desc->data.ctrl & RAVB_DESC_DS_MASK;
- len = desc->data.ctrl & RAVB_DESC_DS_MASK;
packet = (u8 *)(uintptr_t)desc->data.dptr;
ravb_invalidate_dcache((uintptr_t)packet, len);
@@ -349,10 +369,13 @@
}
/* E-MAC init function */
-static int ravb_mac_init(struct ravb_priv *eth)
+static void ravb_mac_init(struct udevice *dev)
{
- /* Disable MAC Interrupt */
- writel(0, eth->iobase + RAVB_REG_ECSIPR);
+ struct ravb_device_ops *device_ops =
+ (struct ravb_device_ops *)dev_get_driver_data(dev);
+ struct ravb_priv *eth = dev_get_priv(dev);
+
+ device_ops->mac_init(dev);
/*
* Set receive frame length
@@ -363,19 +386,33 @@
* largest frames add the CRC length to the maximum Rx descriptor size.
*/
writel(RFLR_RFL_MIN + ETH_FCS_LEN, eth->iobase + RAVB_REG_RFLR);
+}
- return 0;
+static void ravb_mac_init_rcar(struct udevice *dev)
+{
+ struct ravb_priv *eth = dev_get_priv(dev);
+
+ /* Disable MAC Interrupt */
+ writel(0, eth->iobase + RAVB_REG_ECSIPR);
}
+static void ravb_mac_init_rzg2l(struct udevice *dev)
+{
+ struct ravb_priv *eth = dev_get_priv(dev);
+
+ setbits_32(eth->iobase + RAVB_REG_ECMR,
+ ECMR_PRM | ECMR_RXF | ECMR_TXF | ECMR_RCPT |
+ ECMR_TE | ECMR_RE | ECMR_RZPF |
+ (eth->phydev->duplex ? ECMR_DM : 0));
+}
+
/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
+ struct ravb_device_ops *device_ops =
+ (struct ravb_device_ops *)dev_get_driver_data(dev);
struct ravb_priv *eth = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_plat(dev);
- int ret = 0;
- int mode = 0;
- unsigned int delay;
- bool explicit_delay = false;
+ int ret;
/* Set CONFIG mode */
ret = ravb_reset(dev);
@@ -391,6 +428,18 @@
/* Set little endian */
clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
+ device_ops->dmac_init(dev);
+ return 0;
+}
+
+static void ravb_dmac_init_rcar(struct udevice *dev)
+{
+ struct ravb_priv *eth = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ int mode = 0;
+ unsigned int delay;
+ bool explicit_delay = false;
+
/* AVB rx set */
writel(0x18000001, eth->iobase + RAVB_REG_RCR);
@@ -400,7 +449,7 @@
/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77990) ||
(renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995))
- return 0;
+ return;
if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) {
/* Valid values are 0 and 1800, according to DT bindings */
@@ -429,28 +478,45 @@
}
writel(mode, eth->iobase + RAVB_REG_APSR);
+}
- return 0;
+static void ravb_dmac_init_rzg2l(struct udevice *dev)
+{
+ struct ravb_priv *eth = dev_get_priv(dev);
+
+ /* Set Max Frame Length (RTC) */
+ writel(0x7ffc0000 | RFLR_RFL_MIN, eth->iobase + RAVB_REG_RTC);
}
static int ravb_config(struct udevice *dev)
{
+ struct ravb_device_ops *device_ops =
+ (struct ravb_device_ops *)dev_get_driver_data(dev);
struct ravb_priv *eth = dev_get_priv(dev);
struct phy_device *phy = eth->phydev;
- u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
int ret;
/* Configure AVB-DMAC register */
ravb_dmac_init(dev);
/* Configure E-MAC registers */
- ravb_mac_init(eth);
+ ravb_mac_init(dev);
ravb_write_hwaddr(dev);
ret = phy_startup(phy);
if (ret)
return ret;
+ device_ops->config(dev);
+ return 0;
+}
+
+static void ravb_config_rcar(struct udevice *dev)
+{
+ struct ravb_priv *eth = dev_get_priv(dev);
+ struct phy_device *phy = eth->phydev;
+ u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
+
/* Set the transfer speed */
if (phy->speed == 100)
writel(0, eth->iobase + RAVB_REG_GECMR);
@@ -462,8 +528,22 @@
mask |= ECMR_DM;
writel(mask, eth->iobase + RAVB_REG_ECMR);
+}
- return 0;
+static void ravb_config_rzg2l(struct udevice *dev)
+{
+ struct ravb_priv *eth = dev_get_priv(dev);
+ struct phy_device *phy = eth->phydev;
+
+ writel(CSR0_TPE | CSR0_RPE, eth->iobase + RAVB_REG_CSR0);
+
+ /* Set the transfer speed */
+ if (phy->speed == 10)
+ writel(GECMR_SPEED_10M, eth->iobase + RAVB_REG_GECMR);
+ else if (phy->speed == 100)
+ writel(GECMR_SPEED_100M, eth->iobase + RAVB_REG_GECMR);
+ else if (phy->speed == 1000)
+ writel(GECMR_SPEED_1G, eth->iobase + RAVB_REG_GECMR);
}
static int ravb_start(struct udevice *dev)
@@ -581,6 +661,8 @@
static int ravb_probe(struct udevice *dev)
{
+ struct ravb_device_ops *device_ops =
+ (struct ravb_device_ops *)dev_get_driver_data(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct ravb_priv *eth = dev_get_priv(dev);
struct mii_dev *mdiodev;
@@ -616,16 +698,32 @@
if (ret)
goto err_clk_enable;
+ if (device_ops->has_reset) {
+ ret = reset_get_by_index(dev, 0, ð->rst);
+ if (ret < 0)
+ goto err_clk_enable;
+
+ ret = reset_deassert(ð->rst);
+ if (ret < 0)
+ goto err_reset_deassert;
+ }
+
ret = ravb_reset(dev);
if (ret)
- goto err_clk_enable;
+ goto err_ravb_reset;
ret = ravb_phy_config(dev);
if (ret)
- goto err_clk_enable;
+ goto err_ravb_reset;
return 0;
+err_ravb_reset:
+ if (device_ops->has_reset)
+ reset_assert(ð->rst);
+err_reset_deassert:
+ if (device_ops->has_reset)
+ reset_free(ð->rst);
err_clk_enable:
mdio_unregister(mdiodev);
err_mdio_register:
@@ -639,8 +737,14 @@
static int ravb_remove(struct udevice *dev)
{
+ struct ravb_device_ops *device_ops =
+ (struct ravb_device_ops *)dev_get_driver_data(dev);
struct ravb_priv *eth = dev_get_priv(dev);
+ if (device_ops->has_reset) {
+ reset_assert(ð->rst);
+ reset_free(ð->rst);
+ }
clk_release_bulk(ð->clks);
free(eth->phydev);
@@ -675,9 +779,32 @@
return 0;
}
+static const struct ravb_device_ops ravb_device_ops_rcar = {
+ .mac_init = ravb_mac_init_rcar,
+ .dmac_init = ravb_dmac_init_rcar,
+ .config = ravb_config_rcar,
+};
+
+static const struct ravb_device_ops ravb_device_ops_rzg2l = {
+ .mac_init = ravb_mac_init_rzg2l,
+ .dmac_init = ravb_dmac_init_rzg2l,
+ .config = ravb_config_rzg2l,
+ .has_reset = true,
+};
+
static const struct udevice_id ravb_ids[] = {
- { .compatible = "renesas,etheravb-rcar-gen3" },
- { .compatible = "renesas,etheravb-rcar-gen4" },
+ {
+ .compatible = "renesas,etheravb-rcar-gen3",
+ .data = (ulong)&ravb_device_ops_rcar,
+ },
+ {
+ .compatible = "renesas,etheravb-rcar-gen4",
+ .data = (ulong)&ravb_device_ops_rcar,
+ },
+ {
+ .compatible = "renesas,rzg2l-gbeth",
+ .data = (ulong)&ravb_device_ops_rzg2l,
+ },
{ }
};
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 3c62fc0..9b69f36 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -438,6 +438,12 @@
port->port_sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
}
+ ret = phy_config(priv->phydev);
+ if (ret < 0) {
+ dev_err(dev, "phy_config failed: %d", ret);
+ goto err_dis_rx;
+ }
+
ret = phy_startup(priv->phydev);
if (ret) {
dev_err(dev, "phy_startup failed\n");
@@ -639,9 +645,6 @@
phydev->advertising = phydev->supported;
priv->phydev = phydev;
- ret = phy_config(phydev);
- if (ret < 0)
- dev_err(dev, "phy_config() failed: %d", ret);
return ret;
}
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index b9306c9..3acffb4 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -85,41 +85,14 @@
int missing_phys;
};
-struct sun4i_usb_phy_info {
- const char *gpio_vbus;
- const char *gpio_vbus_det;
- const char *gpio_id_det;
-} phy_info[] = {
- {
- .gpio_vbus = CONFIG_USB0_VBUS_PIN,
- .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
- .gpio_id_det = CONFIG_USB0_ID_DET,
- },
- {
- .gpio_vbus = CONFIG_USB1_VBUS_PIN,
- .gpio_vbus_det = NULL,
- .gpio_id_det = NULL,
- },
- {
- .gpio_vbus = CONFIG_USB2_VBUS_PIN,
- .gpio_vbus_det = NULL,
- .gpio_id_det = NULL,
- },
- {
- .gpio_vbus = CONFIG_USB3_VBUS_PIN,
- .gpio_vbus_det = NULL,
- .gpio_id_det = NULL,
- },
-};
-
struct sun4i_usb_phy_plat {
void __iomem *pmu;
- struct gpio_desc gpio_vbus;
struct gpio_desc gpio_vbus_det;
struct gpio_desc gpio_id_det;
struct clk clocks;
struct clk clk2;
struct reset_ctl resets;
+ struct udevice *vbus;
int id;
};
@@ -208,6 +181,7 @@
{
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ int ret;
if (initial_usb_scan_delay) {
mdelay(initial_usb_scan_delay);
@@ -220,8 +194,9 @@
return 0;
}
- if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
- dm_gpio_set_value(&usb_phy->gpio_vbus, 1);
+ ret = regulator_set_enable_if_allowed(usb_phy->vbus, true);
+ if (ret)
+ return ret;
return 0;
}
@@ -230,9 +205,11 @@
{
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ int ret;
- if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
- dm_gpio_set_value(&usb_phy->gpio_vbus, 0);
+ ret = regulator_set_enable_if_allowed(usb_phy->vbus, false);
+ if (ret)
+ return ret;
return 0;
}
@@ -481,48 +458,39 @@
data->usb_phy = plat;
for (i = 0; i < data->cfg->num_phys; i++) {
struct sun4i_usb_phy_plat *phy = &plat[i];
- struct sun4i_usb_phy_info *info = &phy_info[i];
- char name[16];
+ char name[32];
if (data->cfg->missing_phys & BIT(i))
continue;
- ret = dm_gpio_lookup_name(info->gpio_vbus, &phy->gpio_vbus);
- if (ret == 0) {
- ret = dm_gpio_request(&phy->gpio_vbus, "usb_vbus");
- if (ret)
- return ret;
- ret = dm_gpio_set_dir_flags(&phy->gpio_vbus,
- GPIOD_IS_OUT);
+ snprintf(name, sizeof(name), "usb%d_vbus-supply", i);
+ ret = device_get_supply_regulator(dev, name, &phy->vbus);
+ if (phy->vbus) {
+ ret = regulator_set_enable_if_allowed(phy->vbus, false);
if (ret)
return ret;
- ret = dm_gpio_set_value(&phy->gpio_vbus, 0);
- if (ret)
- return ret;
}
- ret = dm_gpio_lookup_name(info->gpio_vbus_det,
- &phy->gpio_vbus_det);
- if (ret == 0) {
- ret = dm_gpio_request(&phy->gpio_vbus_det,
- "usb_vbus_det");
- if (ret)
- return ret;
- ret = dm_gpio_set_dir_flags(&phy->gpio_vbus_det,
- GPIOD_IS_IN);
- if (ret)
+ if (i == 0) {
+ ret = gpio_request_by_name(dev, "usb0_vbus_det-gpios",
+ 0, &phy->gpio_vbus_det,
+ GPIOD_IS_IN);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev,
+ "failed to get VBUS detect GPIO: %d\n",
+ ret);
return ret;
- }
+ }
- ret = dm_gpio_lookup_name(info->gpio_id_det, &phy->gpio_id_det);
- if (ret == 0) {
- ret = dm_gpio_request(&phy->gpio_id_det, "usb_id_det");
- if (ret)
- return ret;
- ret = dm_gpio_set_dir_flags(&phy->gpio_id_det,
- GPIOD_IS_IN | GPIOD_PULL_UP);
- if (ret)
+ ret = gpio_request_by_name(dev, "usb0_id_det-gpios", 0,
+ &phy->gpio_id_det,
+ GPIOD_IS_IN | GPIOD_PULL_UP);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev,
+ "failed to get ID detect GPIO: %d\n",
+ ret);
return ret;
+ }
}
if (data->cfg->dedicated_clocks)
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index d13c5f2..84d9a36 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -139,6 +139,19 @@
only parses the 'fsl,pins' property and configure related
registers.
+config PINCTRL_IMX_SCMI
+ bool "IMX pinctrl SCMI driver"
+ depends on ARCH_IMX9 && PINCTRL_FULL
+ select PINCTRL_IMX
+ help
+ This provides a simple pinctrl driver for i.MX SoC which supports
+ SCMI. This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
+ Say Y here to enable the imx pinctrl SCMI driver
+
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 44e37c6..7d861ae 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -11,3 +11,4 @@
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o
+obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-imx-scmi.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
new file mode 100644
index 0000000..aed47be
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <asm/io.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/pinctrl.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <scmi_protocols.h>
+
+#include "pinctrl-imx.h"
+
+#define DAISY_OFFSET_IMX95 0x408
+
+/* SCMI pin control types */
+#define PINCTRL_TYPE_MUX 192
+#define PINCTRL_TYPE_CONFIG 193
+#define PINCTRL_TYPE_DAISY_ID 194
+#define PINCTRL_TYPE_DAISY_CFG 195
+#define PINCTRL_NUM_CFGS_SHIFT 2
+
+struct imx_scmi_pinctrl_priv {
+ u16 daisy_offset;
+};
+
+static int imx_pinconf_scmi_set(struct udevice *dev, u32 mux_ofs, u32 mux, u32 config_val,
+ u32 input_ofs, u32 input_val)
+{
+ struct imx_scmi_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret, num_cfgs = 0;
+ struct scmi_msg msg;
+
+ /* Call SCMI API to set the pin mux and configuration. */
+ struct scmi_pinctrl_config_set_out out;
+ struct scmi_pinctrl_config_set_in in = {
+ .identifier = mux_ofs / 4,
+ .function_id = 0xFFFFFFFF,
+ .attributes = 0,
+ };
+
+ if (mux_ofs) {
+ in.configs[num_cfgs].type = PINCTRL_TYPE_MUX;
+ in.configs[num_cfgs].val = mux;
+ num_cfgs++;
+ }
+
+ if (config_val) {
+ in.configs[num_cfgs].type = PINCTRL_TYPE_CONFIG;
+ in.configs[num_cfgs].val = config_val;
+ num_cfgs++;
+ }
+
+ if (input_ofs) {
+ in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_ID;
+ in.configs[num_cfgs].val = (input_ofs - priv->daisy_offset) / 4;
+ num_cfgs++;
+ in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_CFG;
+ in.configs[num_cfgs].val = input_val;
+ num_cfgs++;
+ }
+
+ /* Update the number of configs sent in this call. */
+ in.attributes = num_cfgs << PINCTRL_NUM_CFGS_SHIFT;
+
+ msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_PINCTRL,
+ SCMI_MSG_PINCTRL_CONFIG_SET, in, out);
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (ret || out.status) {
+ dev_err(dev, "Failed to set PAD = %d, daisy = %d, scmi_err = %d, ret = %d\n",
+ mux_ofs / 4, input_ofs / 4, out.status, ret);
+ }
+
+ return ret;
+}
+
+static int imx_pinctrl_set_state_scmi(struct udevice *dev, struct udevice *config)
+{
+ int mux_ofs, mux, config_val, input_reg, input_val;
+ u32 *pin_data;
+ int i, j = 0;
+ int npins;
+ int ret;
+
+ ret = imx_pinctrl_set_state_common(dev, config, FSL_PIN_SIZE,
+ &pin_data, &npins);
+ if (ret)
+ return ret;
+
+ /*
+ * Refer to linux documentation for details:
+ * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+ */
+ for (i = 0; i < npins; i++) {
+ mux_ofs = pin_data[j++];
+ /* Skip config_reg */
+ j++;
+ input_reg = pin_data[j++];
+
+ mux = pin_data[j++];
+ input_val = pin_data[j++];
+ config_val = pin_data[j++];
+
+ if (config_val & IMX_PAD_SION)
+ mux |= IOMUXC_CONFIG_SION;
+
+ config_val &= ~IMX_PAD_SION;
+
+ ret = imx_pinconf_scmi_set(dev, mux_ofs, mux, config_val, input_reg, input_val);
+ if (ret && ret != -EPERM) {
+ dev_err(dev, "Set pin %d, mux %d, val %d, error\n",
+ mux_ofs, mux, config_val);
+ }
+ }
+
+ devm_kfree(dev, pin_data);
+
+ return ret;
+}
+
+static const struct pinctrl_ops imx_scmi_pinctrl_ops = {
+ .set_state = imx_pinctrl_set_state_scmi,
+};
+
+static int imx_scmi_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_scmi_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (IS_ENABLED(CONFIG_IMX95))
+ priv->daisy_offset = DAISY_OFFSET_IMX95;
+ else
+ return -EINVAL;
+
+ return devm_scmi_of_get_channel(dev);
+}
+
+static int imx_scmi_pinctrl_bind(struct udevice *dev)
+{
+ if (IS_ENABLED(CONFIG_IMX95))
+ return 0;
+
+ return -ENODEV;
+}
+
+U_BOOT_DRIVER(scmi_pinctrl_imx) = {
+ .name = "scmi_pinctrl_imx",
+ .id = UCLASS_PINCTRL,
+ .bind = imx_scmi_pinctrl_bind,
+ .probe = imx_scmi_pinctrl_probe,
+ .priv_auto = sizeof(struct imx_scmi_pinctrl_priv),
+ .ops = &imx_scmi_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static struct scmi_proto_match match[] = {
+ { .proto_id = SCMI_PROTOCOL_ID_PINCTRL },
+ { /* Sentinel */ }
+};
+
+U_BOOT_SCMI_PROTO_DRIVER(scmi_pinctrl_imx, match);
diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
index 0c2222c..84f76b6 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
@@ -45,7 +45,7 @@
struct msm_pinctrl_data qcm2290_data = {
.pin_data = {
- .pin_count = 133,
+ .pin_count = 134,
.special_pins_start = 127,
},
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c
index 3cd0f07..e8c0ba8 100644
--- a/drivers/power/domain/scmi-power-domain.c
+++ b/drivers/power/domain/scmi-power-domain.c
@@ -11,6 +11,7 @@
#include <power-domain.h>
#include <power-domain-uclass.h>
#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
#include <dm/device_compat.h>
@@ -190,3 +191,10 @@
.probe = scmi_power_domain_probe,
.priv_auto = sizeof(struct scmi_power_domain_priv),
};
+
+static struct scmi_proto_match match[] = {
+ { .proto_id = SCMI_PROTOCOL_ID_POWER_DOMAIN },
+ { /* Sentinel */ }
+};
+
+U_BOOT_SCMI_PROTO_DRIVER(scmi_power_domain, match);
diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
index 521a39d..c300fd2 100644
--- a/drivers/power/pmic/axp.c
+++ b/drivers/power/pmic/axp.c
@@ -51,6 +51,7 @@
{ "cldo", "axp_regulator" },
{ "dc", "axp_regulator" },
{ "dldo", "axp_regulator" },
+ { "drivevbus", "axp_drivevbus" },
{ "eldo", "axp_regulator" },
{ "fldo", "axp_regulator" },
{ "ldo", "axp_regulator" },
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index bec2d2d..95912ef 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -57,6 +57,13 @@
Enable support in SPL for the regulators (DCDCs, LDOs) in the
X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+config REGULATOR_AXP_DRIVEVBUS
+ bool "Enable driver for X-Powers AXP PMIC drivevbus"
+ depends on DM_REGULATOR && PMIC_AXP
+ help
+ Enable support for sensing or driving the USB VBUS on
+ X-Powers AXP2xx and AXP8xx PMICs.
+
config REGULATOR_AXP_USB_POWER
bool "Enable driver for X-Powers AXP PMIC USB power supply"
depends on DM_REGULATOR && PMIC_AXP
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 99affa2..0ee5d90 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_$(PHASE_)REGULATOR_AXP) += axp_regulator.o
+obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_DRIVEVBUS) += axp_drivevbus.o
obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
obj-$(CONFIG_$(PHASE_)DM_REGULATOR_DA9063) += da9063.o
obj-$(CONFIG_$(PHASE_)DM_REGULATOR_MAX77663) += max77663_regulator.o
diff --git a/drivers/power/regulator/axp_drivevbus.c b/drivers/power/regulator/axp_drivevbus.c
new file mode 100644
index 0000000..c463de8
--- /dev/null
+++ b/drivers/power/regulator/axp_drivevbus.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define AXP_VBUS_IPSOUT 0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS BIT(2)
+#define AXP_MISC_CTRL 0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC BIT(4)
+
+static int axp_drivevbus_get_enable(struct udevice *dev)
+{
+ int ret;
+
+ ret = pmic_reg_read(dev->parent, AXP_VBUS_IPSOUT);
+ if (ret < 0)
+ return ret;
+
+ return !!(ret & AXP_VBUS_IPSOUT_DRIVEBUS);
+}
+
+static int axp_drivevbus_set_enable(struct udevice *dev, bool enable)
+{
+ return pmic_clrsetbits(dev->parent, AXP_VBUS_IPSOUT,
+ AXP_VBUS_IPSOUT_DRIVEBUS,
+ enable ? AXP_VBUS_IPSOUT_DRIVEBUS : 0);
+}
+
+static const struct dm_regulator_ops axp_drivevbus_ops = {
+ .get_enable = axp_drivevbus_get_enable,
+ .set_enable = axp_drivevbus_set_enable,
+};
+
+static int axp_drivevbus_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
+ int ret;
+
+ uc_plat->type = REGULATOR_TYPE_FIXED;
+
+ if (dev_read_bool(dev->parent, "x-powers,drive-vbus-en")) {
+ ret = pmic_clrsetbits(dev->parent, AXP_MISC_CTRL,
+ AXP_MISC_CTRL_N_VBUSEN_FUNC, 0);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(axp_drivevbus) = {
+ .name = "axp_drivevbus",
+ .id = UCLASS_REGULATOR,
+ .probe = axp_drivevbus_probe,
+ .ops = &axp_drivevbus_ops,
+};
diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c
index 79db1a6..7d2db1e 100644
--- a/drivers/power/regulator/scmi_regulator.c
+++ b/drivers/power/regulator/scmi_regulator.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <errno.h>
#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
#include <asm/types.h>
#include <dm/device.h>
@@ -202,3 +203,10 @@
.id = UCLASS_NOP,
.bind = scmi_regulator_bind,
};
+
+static struct scmi_proto_match match[] = {
+ { .proto_id = SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN },
+ { /* Sentinel */ }
+};
+
+U_BOOT_SCMI_PROTO_DRIVER(scmi_voltage_domain, match);
diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
index 6dc1fcb..f92a9e3 100644
--- a/drivers/reset/reset-scmi.c
+++ b/drivers/reset/reset-scmi.c
@@ -9,6 +9,7 @@
#include <errno.h>
#include <reset-uclass.h>
#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
#include <asm/types.h>
@@ -81,3 +82,10 @@
.ops = &scmi_reset_domain_ops,
.probe = scmi_reset_probe,
};
+
+static struct scmi_proto_match match[] = {
+ { .proto_id = SCMI_PROTOCOL_ID_RESET_DOMAIN },
+ { /* Sentinel */ }
+};
+
+U_BOOT_SCMI_PROTO_DRIVER(scmi_reset_domain, match);
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index f2f69cf..b579699 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -747,6 +747,10 @@
goto failrd;
}
+ /* Wait til QSPI is idle */
+ if (!cadence_qspi_wait_idle(priv->regbase))
+ return -EIO;
+
return 0;
failrd:
@@ -914,6 +918,11 @@
if (bounce_buf)
free(bounce_buf);
+
+ /* Wait til QSPI is idle */
+ if (!cadence_qspi_wait_idle(priv->regbase))
+ return -EIO;
+
return 0;
failwr:
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 7335394..fe70e98 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -89,15 +89,33 @@
config VIDEO_COPY
bool "Enable copying the frame buffer to a hardware copy"
+ select VIDEO_DAMAGE
help
On some machines (e.g. x86), reading from the frame buffer is very
slow because it is uncached. To improve performance, this feature
allows the frame buffer to be kept in cached memory (allocated by
U-Boot) and then copied to the hardware frame-buffer as needed.
+ It uses the VIDEO_DAMAGE feature to keep track of regions to copy
+ and will only copy actually touched regions.
To use this, your video driver must set @copy_base in
struct video_uc_plat.
+config VIDEO_DAMAGE
+ bool "Enable damage tracking of frame buffer regions"
+ help
+ On some machines (most ARM), the display frame buffer resides in
+ RAM. To make the display controller pick up screen updates, we
+ have to flush frame buffer contents from CPU caches into RAM which
+ can be a slow operation.
+
+ This feature adds damage tracking to collect information about regions
+ that received updates. When we want to sync, we then only flush
+ regions of the frame buffer that were modified before, speeding up
+ screen refreshes significantly.
+
+ It is also used by VIDEO_COPY to identify which regions changed.
+
config BACKLIGHT_PWM
bool "Generic PWM based Backlight Driver"
depends on BACKLIGHT && DM_PWM
@@ -495,6 +513,7 @@
config ATMEL_LCD
bool "Atmel LCD panel support"
+ imply VIDEO_DAMAGE
depends on ARCH_AT91
config ATMEL_LCD_BGR555
@@ -504,6 +523,7 @@
config VIDEO_BCM2835
bool "Display support for BCM2835"
+ imply VIDEO_DAMAGE
help
The graphics processor already sets up the display so this driver
simply checks the resolution and then sets up the frame buffer with
@@ -539,6 +559,13 @@
unknown. The panel has a 540x960 resolution and uses 24 bit RGB per
pixel.
+config VIDEO_LCD_NOVATEK_NT35510
+ bool "Novatek NT35510 DSI LCD panel support"
+ select VIDEO_MIPI_DSI
+ help
+ Say Y here if you want to enable support for Novatek nt35510
+ dsi panel.
+
config VIDEO_LCD_ORISETECH_OTM8009A
bool "OTM8009A DSI LCD panel support"
select VIDEO_MIPI_DSI
@@ -695,6 +722,7 @@
config VIDEO_MVEBU
bool "Armada XP LCD controller"
+ imply VIDEO_DAMAGE
---help---
Support for the LCD controller integrated in the Marvell
Armada XP SoC.
@@ -735,6 +763,7 @@
config ATMEL_HLCD
bool "Enable ATMEL video support using HLCDC"
+ imply VIDEO_DAMAGE
help
HLCDC supports video output to an attached LCD panel.
@@ -836,6 +865,7 @@
config VIDEO_MXS
bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs"
+ imply VIDEO_DAMAGE
help
Enable framebuffer driver for i.MX28/i.MX6UL/i.MX7 processors
@@ -898,6 +928,7 @@
config VIDEO_SIMPLE
bool "Simple display driver for preconfigured display"
+ imply VIDEO_DAMAGE
help
Enables a simple generic display driver which utilizes the
simple-framebuffer devicetree bindings.
@@ -916,6 +947,7 @@
config VIDEO_MCDE_SIMPLE
bool "Simple driver for ST-Ericsson MCDE with preconfigured display"
+ imply VIDEO_DAMAGE
help
Enables a simple display driver for ST-Ericsson MCDE
(Multichannel Display Engine), which reads the configuration from
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index fbdb058..31f6858 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -61,6 +61,7 @@
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o
obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o
+obj-$(CONFIG_VIDEO_LCD_NOVATEK_NT35510) += novatek-nt35510.o
obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 6f4194a..07db613 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -35,9 +35,11 @@
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
end = dst;
- ret = vidconsole_sync_copy(dev, line, end);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ 0,
+ fontdata->height * row,
+ vid_priv->xsize,
+ fontdata->height);
return 0;
}
@@ -51,14 +53,17 @@
void *dst;
void *src;
int size;
- int ret;
dst = vid_priv->fb + rowdst * fontdata->height * vid_priv->line_length;
src = vid_priv->fb + rowsrc * fontdata->height * vid_priv->line_length;
size = fontdata->height * vid_priv->line_length * count;
- ret = vidconsole_memmove(dev, dst, src, size);
- if (ret)
- return ret;
+ memmove(dst, src, size);
+
+ video_damage(dev->parent,
+ 0,
+ fontdata->height * rowdst,
+ vid_priv->xsize,
+ fontdata->height * count);
return 0;
}
@@ -91,9 +96,11 @@
if (ret)
return ret;
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ x,
+ y,
+ fontdata->width,
+ fontdata->height);
return VID_TO_POS(fontdata->width);
}
diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c
index a3f8c63..886b25d 100644
--- a/drivers/video/console_rotate.c
+++ b/drivers/video/console_rotate.c
@@ -21,7 +21,6 @@
int pbytes = VNBYTES(vid_priv->bpix);
void *start, *dst, *line;
int i, j;
- int ret;
start = vid_priv->fb + vid_priv->line_length -
(row + 1) * fontdata->height * pbytes;
@@ -32,9 +31,12 @@
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ vid_priv->xsize - ((row + 1) * fontdata->height),
+ 0,
+ fontdata->height,
+ vid_priv->ysize);
return 0;
}
@@ -48,7 +50,7 @@
int pbytes = VNBYTES(vid_priv->bpix);
void *dst;
void *src;
- int j, ret;
+ int j;
dst = vid_priv->fb + vid_priv->line_length -
(rowdst + count) * fontdata->height * pbytes;
@@ -56,14 +58,17 @@
(rowsrc + count) * fontdata->height * pbytes;
for (j = 0; j < vid_priv->ysize; j++) {
- ret = vidconsole_memmove(dev, dst, src,
- fontdata->height * pbytes * count);
- if (ret)
- return ret;
+ memmove(dst, src, fontdata->height * pbytes * count);
src += vid_priv->line_length;
dst += vid_priv->line_length;
}
+ video_damage(dev->parent,
+ vid_priv->xsize - ((rowdst + count) * fontdata->height),
+ 0,
+ count * fontdata->height,
+ vid_priv->ysize);
+
return 0;
}
@@ -93,9 +98,11 @@
return ret;
/* We draw backwards from 'start, so account for the first line */
- ret = vidconsole_sync_copy(dev, start - vid_priv->line_length, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ vid_priv->xsize - y - fontdata->height,
+ linenum - 1,
+ fontdata->height,
+ fontdata->width);
return VID_TO_POS(fontdata->width);
}
@@ -107,7 +114,7 @@
struct video_fontdata *fontdata = priv->fontdata;
void *start, *line, *dst, *end;
int pixels = fontdata->height * vid_priv->xsize;
- int i, ret;
+ int i;
int pbytes = VNBYTES(vid_priv->bpix);
start = vid_priv->fb + vid_priv->ysize * vid_priv->line_length -
@@ -117,9 +124,12 @@
for (i = 0; i < pixels; i++)
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
end = dst;
- ret = vidconsole_sync_copy(dev, start, end);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ 0,
+ vid_priv->ysize - (row + 1) * fontdata->height,
+ vid_priv->xsize,
+ fontdata->height);
return 0;
}
@@ -139,8 +149,13 @@
vid_priv->line_length;
src = end - (rowsrc + count) * fontdata->height *
vid_priv->line_length;
- vidconsole_memmove(dev, dst, src,
- fontdata->height * vid_priv->line_length * count);
+ memmove(dst, src, fontdata->height * vid_priv->line_length * count);
+
+ video_damage(dev->parent,
+ 0,
+ vid_priv->ysize - (rowdst + count) * fontdata->height,
+ vid_priv->xsize,
+ count * fontdata->height);
return 0;
}
@@ -170,10 +185,11 @@
if (ret)
return ret;
- /* Add 4 bytes to allow for the first pixel writen */
- ret = vidconsole_sync_copy(dev, start + 4, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ x - fontdata->width + 1,
+ linenum - fontdata->height + 1,
+ fontdata->width,
+ fontdata->height);
return VID_TO_POS(fontdata->width);
}
@@ -185,7 +201,7 @@
struct video_fontdata *fontdata = priv->fontdata;
int pbytes = VNBYTES(vid_priv->bpix);
void *start, *dst, *line;
- int i, j, ret;
+ int i, j;
start = vid_priv->fb + row * fontdata->height * pbytes;
line = start;
@@ -195,9 +211,12 @@
fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes);
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ row * fontdata->height,
+ 0,
+ fontdata->height,
+ vid_priv->ysize);
return 0;
}
@@ -211,20 +230,23 @@
int pbytes = VNBYTES(vid_priv->bpix);
void *dst;
void *src;
- int j, ret;
+ int j;
dst = vid_priv->fb + rowdst * fontdata->height * pbytes;
src = vid_priv->fb + rowsrc * fontdata->height * pbytes;
for (j = 0; j < vid_priv->ysize; j++) {
- ret = vidconsole_memmove(dev, dst, src,
- fontdata->height * pbytes * count);
- if (ret)
- return ret;
+ memmove(dst, src, fontdata->height * pbytes * count);
src += vid_priv->line_length;
dst += vid_priv->line_length;
}
+ video_damage(dev->parent,
+ rowdst * fontdata->height,
+ 0,
+ count * fontdata->height,
+ vid_priv->ysize);
+
return 0;
}
@@ -252,11 +274,13 @@
ret = fill_char_horizontally(pfont, &line, vid_priv, fontdata, NORMAL_DIRECTION);
if (ret)
return ret;
- /* Add a line to allow for the first pixels writen */
- ret = vidconsole_sync_copy(dev, start + vid_priv->line_length, line);
- if (ret)
- return ret;
+ video_damage(dev->parent,
+ y,
+ linenum - fontdata->width + 1,
+ fontdata->height,
+ fontdata->width);
+
return VID_TO_POS(fontdata->width);
}
diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 17a2981..6d2c2c2 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -3,6 +3,8 @@
* Copyright (c) 2016 Google, Inc
*/
+#define LOG_CATEGORY UCLASS_VIDEO
+
#include <abuf.h>
#include <dm.h>
#include <log.h>
@@ -190,10 +192,10 @@
static int console_truetype_set_row(struct udevice *dev, uint row, int clr)
{
struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct console_tt_priv *priv = dev_get_priv(dev);
struct console_tt_metrics *met = priv->cur_met;
void *end, *line;
- int ret;
line = vid_priv->fb + row * met->font_size * vid_priv->line_length;
end = line + met->font_size * vid_priv->line_length;
@@ -229,9 +231,12 @@
default:
return -ENOSYS;
}
- ret = vidconsole_sync_copy(dev, line, end);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ 0,
+ vc_priv->y_charsize * row,
+ vid_priv->xsize,
+ vc_priv->y_charsize);
return 0;
}
@@ -240,24 +245,28 @@
uint rowsrc, uint count)
{
struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct console_tt_priv *priv = dev_get_priv(dev);
struct console_tt_metrics *met = priv->cur_met;
void *dst;
void *src;
- int i, diff, ret;
+ int i, diff;
dst = vid_priv->fb + rowdst * met->font_size * vid_priv->line_length;
src = vid_priv->fb + rowsrc * met->font_size * vid_priv->line_length;
- ret = vidconsole_memmove(dev, dst, src, met->font_size *
- vid_priv->line_length * count);
- if (ret)
- return ret;
+ memmove(dst, src, met->font_size * vid_priv->line_length * count);
/* Scroll up our position history */
diff = (rowsrc - rowdst) * met->font_size;
for (i = 0; i < priv->pos_ptr; i++)
priv->pos[i].ypos -= diff;
+ video_damage(dev->parent,
+ 0,
+ vc_priv->y_charsize * rowdst,
+ vid_priv->xsize,
+ vc_priv->y_charsize * count);
+
return 0;
}
@@ -278,7 +287,7 @@
u8 *bits, *data;
int advance;
void *start, *end, *line;
- int row, ret;
+ int row;
/* First get some basic metrics about this character */
stbtt_GetCodepointHMetrics(font, cp, &advance, &lsb);
@@ -418,9 +427,13 @@
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent,
+ VID_TO_PIXEL(x) + xoff,
+ y + met->baseline + yoff,
+ width,
+ height);
+
free(data);
return width_frac;
@@ -477,10 +490,12 @@
static int console_truetype_entry_start(struct udevice *dev)
{
+ struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct console_tt_priv *priv = dev_get_priv(dev);
/* A new input line has start, so clear our history */
priv->pos_ptr = 0;
+ vc_priv->last_ch = 0;
return 0;
}
@@ -722,14 +737,18 @@
}
static int truetype_measure(struct udevice *dev, const char *name, uint size,
- const char *text, struct vidconsole_bbox *bbox)
+ const char *text, int pixel_limit,
+ struct vidconsole_bbox *bbox, struct alist *lines)
{
struct console_tt_metrics *met;
+ struct vidconsole_mline mline;
+ const char *s, *last_space;
+ int width, last_width;
stbtt_fontinfo *font;
int lsb, advance;
- const char *s;
- int width;
- int last;
+ int start;
+ int limit;
+ int lastch;
int ret;
ret = get_metrics(dev, name, size, &met);
@@ -740,27 +759,85 @@
if (!*text)
return 0;
+ limit = -1;
+ if (pixel_limit != -1)
+ limit = tt_ceil((double)pixel_limit / met->scale);
+
font = &met->font;
width = 0;
- for (last = 0, s = text; *s; s++) {
+ bbox->y1 = 0;
+ bbox->x1 = 0;
+ start = 0;
+ last_space = NULL;
+ last_width = 0;
+ for (lastch = 0, s = text; *s; s++) {
+ int neww;
int ch = *s;
- /* Used kerning to fine-tune the position of this character */
- if (last)
- width += stbtt_GetCodepointKernAdvance(font, last, ch);
+ if (ch == ' ') {
+ /*
+ * store the position and width so we can use it again
+ * if we need to word-wrap
+ */
+ last_space = s;
+ last_width = width;
+ }
/* First get some basic metrics about this character */
stbtt_GetCodepointHMetrics(font, ch, &advance, &lsb);
+ neww = width + advance;
+
+ /* Use kerning to fine-tune the position of this character */
+ if (lastch)
+ neww += stbtt_GetCodepointKernAdvance(font, lastch, ch);
+ lastch = ch;
+
+ /* see if we need to start a new line */
+ if (ch == '\n' || (limit != -1 && neww >= limit)) {
+ if (ch != '\n' && last_space) {
+ s = last_space;
+ width = last_width;
+ }
+ last_space = NULL;
+ mline.bbox.x0 = 0;
+ mline.bbox.y0 = bbox->y1;
+ mline.bbox.x1 = tt_ceil((double)width * met->scale);
+ bbox->x1 = max(bbox->x1, mline.bbox.x1);
+ bbox->y1 += met->font_size;
+ mline.bbox.y1 = bbox->y1;
+ mline.bbox.valid = true;
+ mline.start = start;
+ mline.len = (s - text) - start;
+ if (lines && !alist_add(lines, mline))
+ return log_msg_ret("ttm", -ENOMEM);
+ log_debug("line x1 %d y0 %d y1 %d start %d len %d text '%.*s'\n",
+ mline.bbox.x1, mline.bbox.y0, mline.bbox.y1,
+ mline.start, mline.len, mline.len, text + mline.start);
+
+ start = s - text;
+ start++;
+ lastch = 0;
+ neww = 0;
+ }
- width += advance;
- last = ch;
+ width = neww;
}
+ /* add the final line */
+ mline.bbox.x0 = 0;
+ mline.bbox.y0 = bbox->y1;
+ mline.bbox.x1 = tt_ceil((double)width * met->scale);
+ bbox->y1 += met->font_size;
+ mline.bbox.y1 = bbox->y1;
+ mline.start = start;
+ mline.len = (s - text) - start;
+ if (lines && !alist_add(lines, mline))
+ return log_msg_ret("ttM", -ENOMEM);
+
bbox->valid = true;
bbox->x0 = 0;
bbox->y0 = 0;
- bbox->x1 = tt_ceil((double)width * met->scale);
- bbox->y1 = met->font_size;
+ bbox->x1 = max(bbox->x1, mline.bbox.x1);
return 0;
}
@@ -851,7 +928,6 @@
uint row, width, height, xoff;
void *start, *line;
uint out, val;
- int ret;
if (xpl_phase() <= PHASE_SPL)
return -ENOSYS;
@@ -941,9 +1017,8 @@
line += vid_priv->line_length;
}
- ret = vidconsole_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev->parent, x, y, width, height);
return video_sync(vid, true);
}
diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig
index 599d19d..a2cf752 100644
--- a/drivers/video/exynos/Kconfig
+++ b/drivers/video/exynos/Kconfig
@@ -12,6 +12,7 @@
config EXYNOS_FB
bool "Exynos FIMD support"
+ imply VIDEO_DAMAGE
config EXYNOS_MIPI_DSIM
bool "Exynos MIPI DSI support"
diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig
index 12f11c2..4a1927c 100644
--- a/drivers/video/imx/Kconfig
+++ b/drivers/video/imx/Kconfig
@@ -2,6 +2,7 @@
config VIDEO_IPUV3
bool "i.MX IPUv3 Core video support"
depends on VIDEO && (MX5 || MX6)
+ imply VIDEO_DAMAGE
help
This enables framebuffer driver for i.MX processors working
on the IPUv3(Image Processing Unit) internal graphic processor.
diff --git a/drivers/video/meson/Kconfig b/drivers/video/meson/Kconfig
index 3c2d72d..fcf486c 100644
--- a/drivers/video/meson/Kconfig
+++ b/drivers/video/meson/Kconfig
@@ -8,5 +8,6 @@
bool "Enable Amlogic Meson video support"
depends on VIDEO
select DISPLAY
+ imply VIDEO_DAMAGE
help
Enable Amlogic Meson Video Processing Unit video support.
diff --git a/drivers/video/novatek-nt35510.c b/drivers/video/novatek-nt35510.c
new file mode 100644
index 0000000..f343293
--- /dev/null
+++ b/drivers/video/novatek-nt35510.c
@@ -0,0 +1,1253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ *
+ * Inspired from the Linux kernel driver panel-novatek-nt35510.c
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+#define NT35510_CMD_CORRECT_GAMMA BIT(0)
+#define NT35510_CMD_CONTROL_DISPLAY BIT(1)
+#define NT35510_CMD_SETVCMOFF BIT(2)
+
+#define MCS_CMD_MAUCCTR 0xF0 /* Manufacturer command enable */
+#define MCS_CMD_READ_ID1 0xDA
+#define MCS_CMD_READ_ID2 0xDB
+#define MCS_CMD_READ_ID3 0xDC
+#define MCS_CMD_MTP_READ_SETTING 0xF8 /* Uncertain about name */
+#define MCS_CMD_MTP_READ_PARAM 0xFF /* Uncertain about name */
+
+/*
+ * These manufacturer commands are available after we enable manufacturer
+ * command set (MCS) for page 0.
+ */
+#define NT35510_P0_DOPCTR 0xB1
+#define NT35510_P0_SDHDTCTR 0xB6
+#define NT35510_P0_GSEQCTR 0xB7
+#define NT35510_P0_SDEQCTR 0xB8
+#define NT35510_P0_SDVPCTR 0xBA
+#define NT35510_P0_DPFRCTR1 0xBD
+#define NT35510_P0_DPFRCTR2 0xBE
+#define NT35510_P0_DPFRCTR3 0xBF
+#define NT35510_P0_DPMCTR12 0xCC
+
+#define NT35510_P0_DOPCTR_LEN 2
+#define NT35510_P0_GSEQCTR_LEN 2
+#define NT35510_P0_SDEQCTR_LEN 4
+#define NT35510_P0_SDVPCTR_LEN 1
+#define NT35510_P0_DPFRCTR1_LEN 5
+#define NT35510_P0_DPFRCTR2_LEN 5
+#define NT35510_P0_DPFRCTR3_LEN 5
+#define NT35510_P0_DPMCTR12_LEN 3
+
+#define NT35510_DOPCTR_0_RAMKP BIT(7) /* Contents kept in sleep */
+#define NT35510_DOPCTR_0_DSITE BIT(6) /* Enable TE signal */
+#define NT35510_DOPCTR_0_DSIG BIT(5) /* Enable generic read/write */
+#define NT35510_DOPCTR_0_DSIM BIT(4) /* Enable video mode on DSI */
+#define NT35510_DOPCTR_0_EOTP BIT(3) /* Support EoTP */
+#define NT35510_DOPCTR_0_N565 BIT(2) /* RGB or BGR pixel format */
+#define NT35510_DOPCTR_1_TW_PWR_SEL BIT(4) /* TE power selector */
+#define NT35510_DOPCTR_1_CRGB BIT(3) /* RGB or BGR byte order */
+#define NT35510_DOPCTR_1_CTB BIT(2) /* Vertical scanning direction */
+#define NT35510_DOPCTR_1_CRL BIT(1) /* Source driver data shift */
+#define NT35510_P0_SDVPCTR_PRG BIT(2) /* 0 = normal operation, 1 = VGLO */
+#define NT35510_P0_SDVPCTR_AVDD 0 /* source driver output = AVDD */
+#define NT35510_P0_SDVPCTR_OFFCOL 1 /* source driver output = off color */
+#define NT35510_P0_SDVPCTR_AVSS 2 /* source driver output = AVSS */
+#define NT35510_P0_SDVPCTR_HI_Z 3 /* source driver output = High impedance */
+
+/*
+ * These manufacturer commands are available after we enable manufacturer
+ * command set (MCS) for page 1.
+ */
+#define NT35510_P1_SETAVDD 0xB0
+#define NT35510_P1_SETAVEE 0xB1
+#define NT35510_P1_SETVCL 0xB2
+#define NT35510_P1_SETVGH 0xB3
+#define NT35510_P1_SETVRGH 0xB4
+#define NT35510_P1_SETVGL 0xB5
+#define NT35510_P1_BT1CTR 0xB6
+#define NT35510_P1_BT2CTR 0xB7
+#define NT35510_P1_BT3CTR 0xB8
+#define NT35510_P1_BT4CTR 0xB9 /* VGH boosting times/freq */
+#define NT35510_P1_BT5CTR 0xBA
+#define NT35510_P1_PFMCTR 0xBB
+#define NT35510_P1_SETVGP 0xBC
+#define NT35510_P1_SETVGN 0xBD
+#define NT35510_P1_SETVCMOFF 0xBE
+#define NT35510_P1_VGHCTR 0xBF /* VGH output ctrl */
+#define NT35510_P1_SET_GAMMA_RED_POS 0xD1
+#define NT35510_P1_SET_GAMMA_GREEN_POS 0xD2
+#define NT35510_P1_SET_GAMMA_BLUE_POS 0xD3
+#define NT35510_P1_SET_GAMMA_RED_NEG 0xD4
+#define NT35510_P1_SET_GAMMA_GREEN_NEG 0xD5
+#define NT35510_P1_SET_GAMMA_BLUE_NEG 0xD6
+
+/* AVDD and AVEE setting 3 bytes */
+#define NT35510_P1_AVDD_LEN 3
+#define NT35510_P1_AVEE_LEN 3
+#define NT35510_P1_VCL_LEN 3
+#define NT35510_P1_VGH_LEN 3
+#define NT35510_P1_VGL_LEN 3
+#define NT35510_P1_VGP_LEN 3
+#define NT35510_P1_VGN_LEN 3
+#define NT35510_P1_VCMOFF_LEN 2
+/* BT1CTR thru BT5CTR setting 3 bytes */
+#define NT35510_P1_BT1CTR_LEN 3
+#define NT35510_P1_BT2CTR_LEN 3
+#define NT35510_P1_BT3CTR_LEN 3
+#define NT35510_P1_BT4CTR_LEN 3
+#define NT35510_P1_BT5CTR_LEN 3
+/* 52 gamma parameters times two per color: positive and negative */
+#define NT35510_P1_GAMMA_LEN 52
+
+#define NT35510_WRCTRLD_BCTRL BIT(5)
+#define NT35510_WRCTRLD_A BIT(4)
+#define NT35510_WRCTRLD_DD BIT(3)
+#define NT35510_WRCTRLD_BL BIT(2)
+#define NT35510_WRCTRLD_DB BIT(1)
+#define NT35510_WRCTRLD_G BIT(0)
+
+#define NT35510_WRCABC_OFF 0
+#define NT35510_WRCABC_UI_MODE 1
+#define NT35510_WRCABC_STILL_MODE 2
+#define NT35510_WRCABC_MOVING_MODE 3
+
+/**
+ * struct nt35510_config - the display-specific NT35510 configuration
+ *
+ * Some of the settings provide an array of bytes, A, B C which mean:
+ * A = normal / idle off mode
+ * B = idle on mode
+ * C = partial / idle off mode
+ *
+ * Gamma correction arrays are 10bit numbers, two consecutive bytes
+ * makes out one point on the gamma correction curve. The points are
+ * not linearly placed along the X axis, we get points 0, 1, 3, 5
+ * 7, 11, 15, 23, 31, 47, 63, 95, 127, 128, 160, 192, 208, 224, 232,
+ * 240, 244, 248, 250, 252, 254, 255. The voltages tuples form
+ * V0, V1, V3 ... V255, with 0x0000 being the lowest voltage and
+ * 0x03FF being the highest voltage.
+ *
+ * Each value must be strictly higher than the previous value forming
+ * a rising curve like this:
+ *
+ * ^
+ * | V255
+ * | V254
+ * | ....
+ * | V5
+ * | V3
+ * | V1
+ * | V0
+ * +------------------------------------------->
+ *
+ * The details about all settings can be found in the NT35510 Application
+ * Note.
+ */
+struct nt35510_config {
+ /**
+ * @width_mm: physical panel width [mm]
+ */
+ u32 width_mm;
+ /**
+ * @height_mm: physical panel height [mm]
+ */
+ u32 height_mm;
+ /**
+ * @timings: display timings
+ */
+ struct display_timing timings;
+ /**
+ * @mode_flags: DSI operation mode related flags
+ */
+ unsigned long mode_flags;
+ /**
+ * @cmds: enable DSI commands
+ */
+ u32 cmds;
+ /**
+ * @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V
+ * in 0.1V steps the default is 0x05 which means 6.0V
+ */
+ u8 avdd[NT35510_P1_AVDD_LEN];
+ /**
+ * @bt1ctr: setting for boost power control for the AVDD step-up
+ * circuit (1)
+ * bits 0..2 in the lower nibble controls PCK, the booster clock
+ * frequency for the step-up circuit:
+ * 0 = Hsync/32
+ * 1 = Hsync/16
+ * 2 = Hsync/8
+ * 3 = Hsync/4
+ * 4 = Hsync/2
+ * 5 = Hsync
+ * 6 = Hsync x 2
+ * 7 = Hsync x 4
+ * bits 4..6 in the upper nibble controls BTP, the boosting
+ * amplification for the step-up circuit:
+ * 0 = Disable
+ * 1 = 1.5 x VDDB
+ * 2 = 1.66 x VDDB
+ * 3 = 2 x VDDB
+ * 4 = 2.5 x VDDB
+ * 5 = 3 x VDDB
+ * The defaults are 4 and 4 yielding 0x44
+ */
+ u8 bt1ctr[NT35510_P1_BT1CTR_LEN];
+ /**
+ * @avee: setting for AVEE ranging from 0x00 = -6.5V to 0x14 = -4.5V
+ * in 0.1V steps the default is 0x05 which means -6.0V
+ */
+ u8 avee[NT35510_P1_AVEE_LEN];
+ /**
+ * @bt2ctr: setting for boost power control for the AVEE step-up
+ * circuit (2)
+ * bits 0..2 in the lower nibble controls NCK, the booster clock
+ * frequency, the values are the same as for PCK in @bt1ctr.
+ * bits 4..5 in the upper nibble controls BTN, the boosting
+ * amplification for the step-up circuit.
+ * 0 = Disable
+ * 1 = -1.5 x VDDB
+ * 2 = -2 x VDDB
+ * 3 = -2.5 x VDDB
+ * 4 = -3 x VDDB
+ * The defaults are 4 and 3 yielding 0x34
+ */
+ u8 bt2ctr[NT35510_P1_BT2CTR_LEN];
+ /**
+ * @vcl: setting for VCL ranging from 0x00 = -2.5V to 0x11 = -4.0V
+ * in 1V steps, the default is 0x00 which means -2.5V
+ */
+ u8 vcl[NT35510_P1_VCL_LEN];
+ /**
+ * @bt3ctr: setting for boost power control for the VCL step-up
+ * circuit (3)
+ * bits 0..2 in the lower nibble controls CLCK, the booster clock
+ * frequency, the values are the same as for PCK in @bt1ctr.
+ * bits 4..5 in the upper nibble controls BTCL, the boosting
+ * amplification for the step-up circuit.
+ * 0 = Disable
+ * 1 = -0.5 x VDDB
+ * 2 = -1 x VDDB
+ * 3 = -2 x VDDB
+ * The defaults are 4 and 2 yielding 0x24
+ */
+ u8 bt3ctr[NT35510_P1_BT3CTR_LEN];
+ /**
+ * @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V
+ * in 1V steps, the default is 0x08 which means 15V
+ */
+ u8 vgh[NT35510_P1_VGH_LEN];
+ /**
+ * @bt4ctr: setting for boost power control for the VGH step-up
+ * circuit (4)
+ * bits 0..2 in the lower nibble controls HCK, the booster clock
+ * frequency, the values are the same as for PCK in @bt1ctr.
+ * bits 4..5 in the upper nibble controls BTH, the boosting
+ * amplification for the step-up circuit.
+ * 0 = AVDD + VDDB
+ * 1 = AVDD - AVEE
+ * 2 = AVDD - AVEE + VDDB
+ * 3 = AVDD x 2 - AVEE
+ * The defaults are 4 and 3 yielding 0x34
+ */
+ u8 bt4ctr[NT35510_P1_BT4CTR_LEN];
+ /**
+ * @vgl: setting for VGL ranging from 0x00 = -2V to 0x0f = -15V in
+ * 1V steps, the default is 0x08 which means -10V
+ */
+ u8 vgl[NT35510_P1_VGL_LEN];
+ /**
+ * @bt5ctr: setting for boost power control for the VGL step-up
+ * circuit (5)
+ * bits 0..2 in the lower nibble controls LCK, the booster clock
+ * frequency, the values are the same as for PCK in @bt1ctr.
+ * bits 4..5 in the upper nibble controls BTL, the boosting
+ * amplification for the step-up circuit.
+ * 0 = AVEE + VCL
+ * 1 = AVEE - AVDD
+ * 2 = AVEE + VCL - AVDD
+ * 3 = AVEE x 2 - AVDD
+ * The defaults are 3 and 2 yielding 0x32
+ */
+ u8 bt5ctr[NT35510_P1_BT5CTR_LEN];
+ /**
+ * @vgp: setting for VGP, the positive gamma divider voltages
+ * VGMP the high voltage and VGSP the low voltage.
+ * The first byte contains bit 8 of VGMP and VGSP in bits 4 and 0
+ * The second byte contains bit 0..7 of VGMP
+ * The third byte contains bit 0..7 of VGSP
+ * VGMP 0x00 = 3.0V .. 0x108 = 6.3V in steps of 12.5mV
+ * VGSP 0x00 = 0V .. 0x111 = 3.7V in steps of 12.5mV
+ */
+ u8 vgp[NT35510_P1_VGP_LEN];
+ /**
+ * @vgn: setting for VGN, the negative gamma divider voltages,
+ * same layout of bytes as @vgp.
+ */
+ u8 vgn[NT35510_P1_VGN_LEN];
+ /**
+ * @vcmoff: setting the DC VCOM offset voltage
+ * The first byte contains bit 8 of VCM in bit 0 and VCMOFFSEL in bit 4.
+ * The second byte contains bits 0..7 of VCM.
+ * VCMOFFSEL the common voltage offset mode.
+ * VCMOFFSEL 0x00 = VCOM .. 0x01 Gamma.
+ * The default is 0x00.
+ * VCM the VCOM output voltage (VCMOFFSEL = 0) or the internal register
+ * offset for gamma voltage (VCMOFFSEL = 1).
+ * VCM 0x00 = 0V/0 .. 0x118 = 3.5V/280 in steps of 12.5mV/1step
+ * The default is 0x00 = 0V/0.
+ */
+ u8 vcmoff[NT35510_P1_VCMOFF_LEN];
+ /**
+ * @dopctr: setting optional control for display
+ * ERR bits 0..1 in the first byte is the ERR pin output signal setting.
+ * 0 = Disable, ERR pin output low
+ * 1 = ERR pin output CRC error only
+ * 2 = ERR pin output ECC error only
+ * 3 = ERR pin output CRC and ECC error
+ * The default is 0.
+ * N565 bit 2 in the first byte is the 16-bit/pixel format selection.
+ * 0 = R[4:0] + G[5:3] & G[2:0] + B[4:0]
+ * 1 = G[2:0] + R[4:0] & B[4:0] + G[5:3]
+ * The default is 0.
+ * DIS_EoTP_HS bit 3 in the first byte is "DSI protocol violation" error
+ * reporting.
+ * 0 = reporting when error
+ * 1 = not reporting when error
+ * DSIM bit 4 in the first byte is the video mode data type enable
+ * 0 = Video mode data type disable
+ * 1 = Video mode data type enable
+ * The default is 0.
+ * DSIG bit 5 int the first byte is the generic r/w data type enable
+ * 0 = Generic r/w disable
+ * 1 = Generic r/w enable
+ * The default is 0.
+ * DSITE bit 6 in the first byte is TE line enable
+ * 0 = TE line is disabled
+ * 1 = TE line is enabled
+ * The default is 0.
+ * RAMKP bit 7 in the first byte is the frame memory keep/loss in
+ * sleep-in mode
+ * 0 = contents loss in sleep-in
+ * 1 = contents keep in sleep-in
+ * The default is 0.
+ * CRL bit 1 in the second byte is the source driver data shift
+ * direction selection. This bit is XOR operation with bit RSMX
+ * of 3600h command.
+ * 0 (RMSX = 0) = S1 -> S1440
+ * 0 (RMSX = 1) = S1440 -> S1
+ * 1 (RMSX = 0) = S1440 -> S1
+ * 1 (RMSX = 1) = S1 -> S1440
+ * The default is 0.
+ * CTB bit 2 in the second byte is the vertical scanning direction
+ * selection for gate control signals. This bit is XOR operation
+ * with bit ML of 3600h command.
+ * 0 (ML = 0) = Forward (top -> bottom)
+ * 0 (ML = 1) = Reverse (bottom -> top)
+ * 1 (ML = 0) = Reverse (bottom -> top)
+ * 1 (ML = 1) = Forward (top -> bottom)
+ * The default is 0.
+ * CRGB bit 3 in the second byte is RGB-BGR order selection. This
+ * bit is XOR operation with bit RGB of 3600h command.
+ * 0 (RGB = 0) = RGB/Normal
+ * 0 (RGB = 1) = BGR/RB swap
+ * 1 (RGB = 0) = BGR/RB swap
+ * 1 (RGB = 1) = RGB/Normal
+ * The default is 0.
+ * TE_PWR_SEL bit 4 in the second byte is the TE output voltage
+ * level selection (only valid when DSTB_SEL = 0 or DSTB_SEL = 1,
+ * VSEL = High and VDDI = 1.665~3.3V).
+ * 0 = TE output voltage level is VDDI
+ * 1 = TE output voltage level is VDDA
+ * The default is 0.
+ */
+ u8 dopctr[NT35510_P0_DOPCTR_LEN];
+ /**
+ * @madctl: Memory data access control
+ * RSMY bit 0 is flip vertical. Flips the display image top to down.
+ * RSMX bit 1 is flip horizontal. Flips the display image left to right.
+ * MH bit 2 is the horizontal refresh order.
+ * RGB bit 3 is the RGB-BGR order.
+ * 0 = RGB color sequence
+ * 1 = BGR color sequence
+ * ML bit 4 is the vertical refresh order.
+ * MV bit 5 is the row/column exchange.
+ * MX bit 6 is the column address order.
+ * MY bit 7 is the row address order.
+ */
+ u8 madctl;
+ /**
+ * @sdhdtctr: source output data hold time
+ * 0x00..0x3F = 0..31.5us in steps of 0.5us
+ * The default is 0x05 = 2.5us.
+ */
+ u8 sdhdtctr;
+ /**
+ * @gseqctr: EQ control for gate signals
+ * GFEQ_XX[3:0]: time setting of EQ step for falling edge in steps
+ * of 0.5us.
+ * The default is 0x07 = 3.5us
+ * GREQ_XX[7:4]: time setting of EQ step for rising edge in steps
+ * of 0.5us.
+ * The default is 0x07 = 3.5us
+ */
+ u8 gseqctr[NT35510_P0_GSEQCTR_LEN];
+ /**
+ * @sdeqctr: Source driver control settings, first byte is
+ * 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and
+ * mode 2 uses three steps meaning EQS3 is not used in mode
+ * 1. Mode 2 is default. The last three parameters are EQS1, EQS2
+ * and EQS3, setting the rise time for each equalizer step:
+ * 0x00 = 0.0 us to 0x0f = 7.5 us in steps of 0.5us. The default
+ * is 0x07 = 3.5 us.
+ */
+ u8 sdeqctr[NT35510_P0_SDEQCTR_LEN];
+ /**
+ * @sdvpctr: power/voltage behaviour during vertical porch time
+ */
+ u8 sdvpctr;
+ /**
+ * @t1: the number of pixel clocks on one scanline, range
+ * 0x100 (258 ticks) .. 0x3FF (1024 ticks) so the value + 1
+ * clock ticks.
+ */
+ u16 t1;
+ /**
+ * @vbp: vertical back porch toward the PANEL note: not toward
+ * the DSI host; these are separate interfaces, in from DSI host
+ * and out to the panel.
+ */
+ u8 vbp;
+ /**
+ * @vfp: vertical front porch toward the PANEL.
+ */
+ u8 vfp;
+ /**
+ * @psel: pixel clock divisor: 0 = 1, 1 = 2, 2 = 4, 3 = 8.
+ */
+ u8 psel;
+ /**
+ * @dpmctr12: Display timing control 12
+ * Byte 1 bit 4 selects LVGL voltage level: 0 = VGLX, 1 = VGL_REG
+ * Byte 1 bit 1 selects gate signal mode: 0 = non-overlap, 1 = overlap
+ * Byte 1 bit 0 selects output signal control R/L swap, 0 = normal
+ * 1 = swap all O->E, L->R
+ * Byte 2 is CLW delay clock for CK O/E and CKB O/E signals:
+ * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
+ * Byte 3 is FTI_H0 delay time for STP O/E signals:
+ * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
+ */
+ u8 dpmctr12[NT35510_P0_DPMCTR12_LEN];
+ /**
+ * @gamma_corr_pos_r: Red gamma correction parameters, positive
+ */
+ u8 gamma_corr_pos_r[NT35510_P1_GAMMA_LEN];
+ /**
+ * @gamma_corr_pos_g: Green gamma correction parameters, positive
+ */
+ u8 gamma_corr_pos_g[NT35510_P1_GAMMA_LEN];
+ /**
+ * @gamma_corr_pos_b: Blue gamma correction parameters, positive
+ */
+ u8 gamma_corr_pos_b[NT35510_P1_GAMMA_LEN];
+ /**
+ * @gamma_corr_neg_r: Red gamma correction parameters, negative
+ */
+ u8 gamma_corr_neg_r[NT35510_P1_GAMMA_LEN];
+ /**
+ * @gamma_corr_neg_g: Green gamma correction parameters, negative
+ */
+ u8 gamma_corr_neg_g[NT35510_P1_GAMMA_LEN];
+ /**
+ * @gamma_corr_neg_b: Blue gamma correction parameters, negative
+ */
+ u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN];
+ /**
+ * @wrdisbv: write display brightness
+ * 0x00 value means the lowest brightness and 0xff value means
+ * the highest brightness.
+ * The default is 0x00.
+ */
+ u8 wrdisbv;
+ /**
+ * @wrctrld: write control display
+ * G bit 0 selects gamma curve: 0 = Manual, 1 = Automatic
+ * DB bit 1 selects display brightness: 0 = Manual, 1 = Automatic
+ * BL bit 2 controls backlight control: 0 = Off, 1 = On
+ * DD bit 3 controls display dimming: 0 = Off, 1 = On
+ * A bit 4 controls LABC block: 0 = Off, 1 = On
+ * BCTRL bit 5 controls brightness block: 0 = Off, 1 = On
+ */
+ u8 wrctrld;
+ /**
+ * @wrcabc: write content adaptive brightness control
+ * There is possible to use 4 different modes for content adaptive
+ * image functionality:
+ * 0: Off
+ * 1: User Interface Image (UI-Mode)
+ * 2: Still Picture Image (Still-Mode)
+ * 3: Moving Picture Image (Moving-Mode)
+ * The default is 0
+ */
+ u8 wrcabc;
+ /**
+ * @wrcabcmb: write CABC minimum brightness
+ * Set the minimum brightness value of the display for CABC
+ * function.
+ * 0x00 value means the lowest brightness for CABC and 0xff
+ * value means the highest brightness for CABC.
+ * The default is 0x00.
+ */
+ u8 wrcabcmb;
+};
+
+/**
+ * struct nt35510 - state container for the NT35510 panel
+ */
+struct nt35510_panel_priv {
+ const struct nt35510_config *conf;
+ struct udevice *vdd_reg;
+ struct udevice *vddi_reg;
+ struct gpio_desc *reset;
+};
+
+/* Manufacturer command has strictly this byte sequence */
+static const u8 nt35510_mauc_mtp_read_param[] = { 0xAA, 0x55, 0x25, 0x01 };
+static const u8 nt35510_mauc_mtp_read_setting[] = { 0x01, 0x02, 0x00, 0x20,
+ 0x33, 0x13, 0x00, 0x40,
+ 0x00, 0x00, 0x23, 0x02 };
+static const u8 nt35510_mauc_select_page_0[] = { 0x55, 0xAA, 0x52, 0x08, 0x00 };
+static const u8 nt35510_mauc_select_page_1[] = { 0x55, 0xAA, 0x52, 0x08, 0x01 };
+static const u8 nt35510_vgh_on[] = { 0x01 };
+
+#define NT35510_ROTATE_0_SETTING 0x02
+#define NT35510_ROTATE_180_SETTING 0x00
+
+static inline struct mipi_dsi_device *to_mipi_dsi_device(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+ return plat->device;
+}
+
+static inline const struct nt35510_config *to_panel_config(struct udevice *dev)
+{
+ struct nt35510_panel_priv *priv = dev_get_priv(dev);
+
+ return priv->conf;
+}
+
+static int nt35510_send_long(struct udevice *dev, u8 cmd, u8 cmdlen,
+ const u8 *seq)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
+ const u8 *seqp = seq;
+ int cmdwritten = 0;
+ int chunk = cmdlen;
+ int ret;
+
+ if (chunk > 15)
+ chunk = 15;
+ ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk);
+ if (ret < 0) {
+ dev_err(dev, "error sending DCS command seq cmd %02x\n", cmd);
+ return ret;
+ }
+ cmdwritten += chunk;
+ seqp += chunk;
+
+ while (cmdwritten < cmdlen) {
+ chunk = cmdlen - cmdwritten;
+ if (chunk > 15)
+ chunk = 15;
+ ret = mipi_dsi_generic_write(dsi, seqp, chunk);
+ if (ret < 0) {
+ dev_err(dev, "error sending generic write seq %02x\n", cmd);
+ return ret;
+ }
+ cmdwritten += chunk;
+ seqp += chunk;
+ }
+ dev_dbg(dev, "sent command %02x %02x bytes\n", cmd, cmdlen);
+ return 0;
+}
+
+static int nt35510_setup_power(struct udevice *dev)
+{
+ const struct nt35510_config *conf = to_panel_config(dev);
+ int ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SETAVDD,
+ NT35510_P1_AVDD_LEN,
+ conf->avdd);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_BT1CTR,
+ NT35510_P1_BT1CTR_LEN,
+ conf->bt1ctr);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SETAVEE,
+ NT35510_P1_AVEE_LEN,
+ conf->avee);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_BT2CTR,
+ NT35510_P1_BT2CTR_LEN,
+ conf->bt2ctr);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SETVCL,
+ NT35510_P1_VCL_LEN,
+ conf->vcl);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_BT3CTR,
+ NT35510_P1_BT3CTR_LEN,
+ conf->bt3ctr);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SETVGH,
+ NT35510_P1_VGH_LEN,
+ conf->vgh);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_BT4CTR,
+ NT35510_P1_BT4CTR_LEN,
+ conf->bt4ctr);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_VGHCTR,
+ ARRAY_SIZE(nt35510_vgh_on),
+ nt35510_vgh_on);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SETVGL,
+ NT35510_P1_VGL_LEN,
+ conf->vgl);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_BT5CTR,
+ NT35510_P1_BT5CTR_LEN,
+ conf->bt5ctr);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SETVGP,
+ NT35510_P1_VGP_LEN,
+ conf->vgp);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SETVGN,
+ NT35510_P1_VGN_LEN,
+ conf->vgn);
+ if (ret)
+ return ret;
+
+ if (conf->cmds & NT35510_CMD_SETVCMOFF) {
+ ret = nt35510_send_long(dev, NT35510_P1_SETVCMOFF,
+ NT35510_P1_VCMOFF_LEN,
+ conf->vcmoff);
+ if (ret)
+ return ret;
+ }
+
+ /* Typically 10 ms */
+ mdelay(10);
+
+ return 0;
+}
+
+static int nt35510_setup_display(struct udevice *dev)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
+ const struct nt35510_config *conf = to_panel_config(dev);
+ u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN];
+ int ret;
+
+ ret = nt35510_send_long(dev, NT35510_P0_DOPCTR,
+ NT35510_P0_DOPCTR_LEN,
+ conf->dopctr);
+ if (ret)
+ return ret;
+
+ ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &conf->madctl,
+ sizeof(conf->madctl));
+ if (ret < 0)
+ return ret;
+
+ ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &conf->sdhdtctr,
+ sizeof(conf->sdhdtctr));
+ if (ret < 0)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P0_GSEQCTR,
+ NT35510_P0_GSEQCTR_LEN,
+ conf->gseqctr);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P0_SDEQCTR,
+ NT35510_P0_SDEQCTR_LEN,
+ conf->sdeqctr);
+ if (ret)
+ return ret;
+
+ ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDVPCTR,
+ &conf->sdvpctr, 1);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Display timing control for active and idle off mode:
+ * the first byte contains
+ * the two high bits of T1A and second byte the low 8 bits, and
+ * the valid range is 0x100 (257) to 0x3ff (1023) representing
+ * 258..1024 (+1) pixel clock ticks for one scanline. At 20MHz pixel
+ * clock this covers the range of 12.90us .. 51.20us in steps of
+ * 0.05us, the default is 0x184 (388) representing 389 ticks.
+ * The third byte is VBPDA, vertical back porch display active
+ * and the fourth VFPDA, vertical front porch display active,
+ * both given in number of scanlines in the range 0x02..0xff
+ * for 2..255 scanlines. The fifth byte is 2 bits selecting
+ * PSEL for active and idle off mode, how much the 20MHz clock
+ * is divided by 0..3. This needs to be adjusted to get the right
+ * frame rate.
+ */
+ dpfrctr[0] = (conf->t1 >> 8) & 0xFF;
+ dpfrctr[1] = conf->t1 & 0xFF;
+ /* Vertical back porch */
+ dpfrctr[2] = conf->vbp;
+ /* Vertical front porch */
+ dpfrctr[3] = conf->vfp;
+ dpfrctr[4] = conf->psel;
+ ret = nt35510_send_long(dev, NT35510_P0_DPFRCTR1,
+ NT35510_P0_DPFRCTR1_LEN,
+ dpfrctr);
+ if (ret)
+ return ret;
+ /* For idle and partial idle off mode we decrease front porch by one */
+ dpfrctr[3]--;
+ ret = nt35510_send_long(dev, NT35510_P0_DPFRCTR2,
+ NT35510_P0_DPFRCTR2_LEN,
+ dpfrctr);
+ if (ret)
+ return ret;
+ ret = nt35510_send_long(dev, NT35510_P0_DPFRCTR3,
+ NT35510_P0_DPFRCTR3_LEN,
+ dpfrctr);
+ if (ret)
+ return ret;
+
+ /* Enable TE on vblank */
+ ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+ if (ret)
+ return ret;
+
+ /* Turn on the pads? */
+ ret = nt35510_send_long(dev, NT35510_P0_DPMCTR12,
+ NT35510_P0_DPMCTR12_LEN,
+ conf->dpmctr12);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int nt35510_read_id(struct udevice *dev)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
+ u8 id1, id2, id3;
+ int ret;
+
+ ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID1, &id1, 1);
+ if (ret < 0) {
+ dev_err(dev, "could not read MTP ID1\n");
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID2, &id2, 1);
+ if (ret < 0) {
+ dev_err(dev, "could not read MTP ID2\n");
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID3, &id3, 1);
+ if (ret < 0) {
+ dev_err(dev, "could not read MTP ID3\n");
+ return ret;
+ }
+
+ /*
+ * Multi-Time Programmable (?) memory contains manufacturer
+ * ID (e.g. Hydis 0x55), driver ID (e.g. NT35510 0xc0) and
+ * version.
+ */
+ dev_info(dev, "MTP ID manufacturer: %02x version: %02x driver: %02x\n",
+ id1, id2, id3);
+
+ return 0;
+}
+
+static int nt35510_init_sequence(struct udevice *dev)
+{
+ const struct nt35510_config *conf = to_panel_config(dev);
+ int ret;
+
+ ret = nt35510_send_long(dev, MCS_CMD_MTP_READ_PARAM,
+ ARRAY_SIZE(nt35510_mauc_mtp_read_param),
+ nt35510_mauc_mtp_read_param);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, MCS_CMD_MTP_READ_SETTING,
+ ARRAY_SIZE(nt35510_mauc_mtp_read_setting),
+ nt35510_mauc_mtp_read_setting);
+ if (ret)
+ return ret;
+
+ nt35510_read_id(dev);
+
+ /* Set up stuff in manufacturer control, page 1 */
+ ret = nt35510_send_long(dev, MCS_CMD_MAUCCTR,
+ ARRAY_SIZE(nt35510_mauc_select_page_1),
+ nt35510_mauc_select_page_1);
+ if (ret)
+ return ret;
+
+ ret = nt35510_setup_power(dev);
+ if (ret)
+ return ret;
+
+ if (conf->cmds & NT35510_CMD_CORRECT_GAMMA) {
+ ret = nt35510_send_long(dev, NT35510_P1_SET_GAMMA_RED_POS,
+ NT35510_P1_GAMMA_LEN,
+ conf->gamma_corr_pos_r);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SET_GAMMA_GREEN_POS,
+ NT35510_P1_GAMMA_LEN,
+ conf->gamma_corr_pos_g);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SET_GAMMA_BLUE_POS,
+ NT35510_P1_GAMMA_LEN,
+ conf->gamma_corr_pos_b);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SET_GAMMA_RED_NEG,
+ NT35510_P1_GAMMA_LEN,
+ conf->gamma_corr_neg_r);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SET_GAMMA_GREEN_NEG,
+ NT35510_P1_GAMMA_LEN,
+ conf->gamma_corr_neg_g);
+ if (ret)
+ return ret;
+
+ ret = nt35510_send_long(dev, NT35510_P1_SET_GAMMA_BLUE_NEG,
+ NT35510_P1_GAMMA_LEN,
+ conf->gamma_corr_neg_b);
+ if (ret)
+ return ret;
+ }
+
+ /* Set up stuff in manufacturer control, page 0 */
+ ret = nt35510_send_long(dev, MCS_CMD_MAUCCTR,
+ ARRAY_SIZE(nt35510_mauc_select_page_0),
+ nt35510_mauc_select_page_0);
+ if (ret)
+ return ret;
+
+ ret = nt35510_setup_display(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int nt35510_panel_enable_backlight(struct udevice *dev)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
+ const struct nt35510_config *conf = to_panel_config(dev);
+ int ret;
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0)
+ return ret;
+
+ ret = nt35510_init_sequence(dev);
+ if (ret)
+ return ret;
+
+ /* Exit sleep mode */
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret) {
+ dev_err(dev, "failed to exit sleep mode (%d)\n", ret);
+ return ret;
+ }
+
+ /* Up to 120 ms */
+ mdelay(120);
+
+ if (conf->cmds & NT35510_CMD_CONTROL_DISPLAY) {
+ ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY,
+ &conf->wrctrld,
+ sizeof(conf->wrctrld));
+ if (ret < 0)
+ return ret;
+
+ ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_POWER_SAVE,
+ &conf->wrcabc,
+ sizeof(conf->wrcabc));
+ if (ret < 0)
+ return ret;
+
+ ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS,
+ &conf->wrcabcmb,
+ sizeof(conf->wrcabcmb));
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_display_on(dsi);
+ if (ret) {
+ dev_err(dev, "failed to turn display on (%d)\n", ret);
+ return ret;
+ }
+
+ /* Some 10 ms */
+ mdelay(10);
+
+ ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x7f);
+ if (ret < 0)
+ return ret;
+
+ /* Need to wait a few time before sending the first image */
+ mdelay(10);
+
+ return 0;
+}
+
+static int nt35510_panel_get_display_timing(struct udevice *dev,
+ struct display_timing *timings)
+{
+ struct nt35510_panel_priv *priv = dev_get_priv(dev);
+
+ memcpy(timings, &priv->conf->timings, sizeof(*timings));
+ return 0;
+}
+
+static int nt35510_panel_of_to_plat(struct udevice *dev)
+{
+ struct nt35510_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+ ret = device_get_supply_regulator(dev, "vdd-supply",
+ &priv->vdd_reg);
+ if (ret) {
+ dev_err(dev, "Warning: cannot get vdd supply\n");
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vddi-supply",
+ &priv->vddi_reg);
+ if (ret) {
+ dev_err(dev, "Warning: cannot get vddi supply\n");
+ return ret;
+ }
+ }
+
+ priv->reset =
+ devm_gpiod_get_optional(dev, "reset",
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (IS_ERR(priv->reset)) {
+ dev_err(dev, "error getting RESET GPIO\n");
+ return PTR_ERR(priv->reset);
+ }
+
+ return 0;
+}
+
+static int nt35510_panel_probe(struct udevice *dev)
+{
+ struct nt35510_panel_priv *priv = dev_get_priv(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+ int ret;
+
+ priv->conf = (struct nt35510_config *)dev_get_driver_data(dev);
+ if (!priv->conf) {
+ dev_err(dev, "missing device configuration\n");
+ return -ENODEV;
+ }
+
+ if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+ dev_dbg(dev, "enable regulator '%s'\n", priv->vdd_reg->name);
+ ret = regulator_set_enable(priv->vdd_reg, true);
+ if (ret)
+ return ret;
+
+ dev_dbg(dev, "enable regulator '%s'\n", priv->vddi_reg->name);
+ ret = regulator_set_enable(priv->vddi_reg, true);
+ if (ret)
+ return ret;
+ }
+
+ /* Toggle RESET in accordance with datasheet page 370 */
+ if (priv->reset) {
+ dm_gpio_set_value(priv->reset, 1);
+ /* Active min 10 us according to datasheet, let's say 20 */
+ mdelay(1);
+ dm_gpio_set_value(priv->reset, 0);
+ /*
+ * 5 ms during sleep mode, 120 ms during sleep out mode
+ * according to datasheet, let's use 15 ms.
+ */
+ mdelay(150);
+ }
+
+ plat->lanes = 2;
+ plat->format = MIPI_DSI_FMT_RGB888;
+ plat->mode_flags = priv->conf->mode_flags;
+
+ return 0;
+}
+
+static const struct panel_ops nt35510_panel_ops = {
+ .enable_backlight = nt35510_panel_enable_backlight,
+ .get_display_timing = nt35510_panel_get_display_timing,
+};
+
+/*
+ * These gamma correction values are 10bit tuples, so only bits 0 and 1 is
+ * ever used in the first byte. They form a positive and negative gamma
+ * correction curve for each color, values must be strictly higher for each
+ * step on the curve. As can be seen these default curves goes from 0x0001
+ * to 0x03FE.
+ */
+#define NT35510_GAMMA_POS_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \
+ 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \
+ 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \
+ 0x83, 0x02, 0x78, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \
+ 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \
+ 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE
+
+#define NT35510_GAMMA_NEG_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \
+ 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \
+ 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \
+ 0x43, 0x02, 0x50, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \
+ 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \
+ 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE
+
+/*
+ * The Hydis HVA40WV1 panel
+ */
+static const struct nt35510_config nt35510_hydis_hva40wv1 = {
+ .width_mm = 52,
+ .height_mm = 86,
+ /**
+ * As the Hydis panel is used in command mode, the porches etc
+ * are settings programmed internally into the NT35510 controller
+ * and generated toward the physical display. As the panel is not
+ * used in video mode, these are not really exposed to the DSI
+ * host.
+ *
+ * Display frame rate control:
+ * Frame rate = (20 MHz / 1) / (389 * (7 + 50 + 800)) ~= 60 Hz
+ */
+ .timings = {
+ /* The internal pixel clock of the NT35510 is 20 MHz */
+ .pixelclock.typ = 20000,
+ .hactive.typ = 480,
+ .hfront_porch.typ = 2,
+ .hsync_len.typ = 0,
+ .hback_porch.typ = 5,
+ .vactive.typ = 800,
+ .vfront_porch.typ = 2,
+ .vsync_len.typ = 0,
+ .vback_porch.typ = 5,
+ },
+ .mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .cmds = NT35510_CMD_CORRECT_GAMMA,
+ /* 0x09: AVDD = 5.6V */
+ .avdd = { 0x09, 0x09, 0x09 },
+ /* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */
+ .bt1ctr = { 0x34, 0x34, 0x34 },
+ /* 0x09: AVEE = -5.6V */
+ .avee = { 0x09, 0x09, 0x09 },
+ /* 0x24: NCK = Hsync/2, BTN = -2 x VDDB */
+ .bt2ctr = { 0x24, 0x24, 0x24 },
+ /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -2.5V */
+ .vcl = { 0x00, 0x00, 0x00 },
+ /* 0x24: CLCK = Hsync/2, BTN = -1 x VDDB */
+ .bt3ctr = { 0x24, 0x24, 0x24 },
+ /* 0x05 = 12V */
+ .vgh = { 0x05, 0x05, 0x05 },
+ /* 0x24: NCKA = Hsync/2, VGH = 2 x AVDD - AVEE */
+ .bt4ctr = { 0x24, 0x24, 0x24 },
+ /* 0x0B = -13V */
+ .vgl = { 0x0B, 0x0B, 0x0B },
+ /* 0x24: LCKA = Hsync, VGL = AVDD + VCL - AVDD */
+ .bt5ctr = { 0x24, 0x24, 0x24 },
+ /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */
+ .vgp = { 0x00, 0xA3, 0x00 },
+ /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */
+ .vgn = { 0x00, 0xA3, 0x00 },
+ /* VCMOFFSEL = VCOM voltage offset mode, VCM = 0V */
+ .vcmoff = { 0x00, 0x00 },
+ /* Enable TE, EoTP and RGB pixel format */
+ .dopctr = { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP |
+ NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB },
+ .madctl = NT35510_ROTATE_0_SETTING,
+ /* 0x0A: SDT = 5 us */
+ .sdhdtctr = 0x0A,
+ /* EQ control for gate signals, 0x00 = 0 us */
+ .gseqctr = { 0x00, 0x00 },
+ /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */
+ .sdeqctr = { 0x01, 0x05, 0x05, 0x05 },
+ /* SDVPCTR: Normal operation off color during v porch */
+ .sdvpctr = 0x01,
+ /* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */
+ .t1 = 0x0184,
+ /* VBP: vertical back porch toward the panel */
+ .vbp = 7,
+ /* VFP: vertical front porch toward the panel */
+ .vfp = 50,
+ /* PSEL: divide pixel clock 20MHz with 1 (no clock downscaling) */
+ .psel = 0,
+ /* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */
+ .dpmctr12 = { 0x03, 0x00, 0x00, },
+ /* Default gamma correction values */
+ .gamma_corr_pos_r = { NT35510_GAMMA_POS_DEFAULT },
+ .gamma_corr_pos_g = { NT35510_GAMMA_POS_DEFAULT },
+ .gamma_corr_pos_b = { NT35510_GAMMA_POS_DEFAULT },
+ .gamma_corr_neg_r = { NT35510_GAMMA_NEG_DEFAULT },
+ .gamma_corr_neg_g = { NT35510_GAMMA_NEG_DEFAULT },
+ .gamma_corr_neg_b = { NT35510_GAMMA_NEG_DEFAULT },
+};
+
+static const struct nt35510_config nt35510_frida_frd400b25025 = {
+ .width_mm = 52,
+ .height_mm = 86,
+ .timings = {
+ .pixelclock.typ = 23000000,
+ .hactive.typ = 480,
+ .hfront_porch.typ = 34,
+ .hback_porch.typ = 34,
+ .hsync_len.typ = 2,
+ .vactive.typ = 800,
+ .vfront_porch.typ = 15,
+ .vback_porch.typ = 15,
+ .vsync_len.typ = 12,
+ },
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_LPM,
+ .cmds = NT35510_CMD_CONTROL_DISPLAY | NT35510_CMD_SETVCMOFF,
+ /* 0x03: AVDD = 6.2V */
+ .avdd = { 0x03, 0x03, 0x03 },
+ /* 0x46: PCK = 2 x Hsync, BTP = 2.5 x VDDB */
+ .bt1ctr = { 0x46, 0x46, 0x46 },
+ /* 0x03: AVEE = -6.2V */
+ .avee = { 0x03, 0x03, 0x03 },
+ /* 0x36: PCK = 2 x Hsync, BTP = 2 x VDDB */
+ .bt2ctr = { 0x36, 0x36, 0x36 },
+ /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -3.5V */
+ .vcl = { 0x00, 0x00, 0x02 },
+ /* 0x26: CLCK = 2 x Hsync, BTN = -1 x VDDB */
+ .bt3ctr = { 0x26, 0x26, 0x26 },
+ /* 0x09 = 16V */
+ .vgh = { 0x09, 0x09, 0x09 },
+ /* 0x36: HCK = 2 x Hsync, VGH = 2 x AVDD - AVEE */
+ .bt4ctr = { 0x36, 0x36, 0x36 },
+ /* 0x08 = -10V */
+ .vgl = { 0x08, 0x08, 0x08 },
+ /* 0x26: LCK = 2 x Hsync, VGL = AVDD + VCL - AVDD */
+ .bt5ctr = { 0x26, 0x26, 0x26 },
+ /* VGMP: 0x080 = 4.6V, VGSP = 0V */
+ .vgp = { 0x00, 0x80, 0x00 },
+ /* VGMP: 0x080 = 4.6V, VGSP = 0V */
+ .vgn = { 0x00, 0x80, 0x00 },
+ /* VCMOFFSEL = VCOM voltage offset mode, VCM = -1V */
+ .vcmoff = { 0x00, 0x50 },
+ .dopctr = { NT35510_DOPCTR_0_RAMKP | NT35510_DOPCTR_0_DSITE |
+ NT35510_DOPCTR_0_DSIG | NT35510_DOPCTR_0_DSIM |
+ NT35510_DOPCTR_0_EOTP | NT35510_DOPCTR_0_N565, 0 },
+ .madctl = NT35510_ROTATE_180_SETTING,
+ /* 0x03: SDT = 1.5 us */
+ .sdhdtctr = 0x03,
+ /* EQ control for gate signals, 0x00 = 0 us */
+ .gseqctr = { 0x00, 0x00 },
+ /* SDEQCTR: source driver EQ mode 2, 1 us rise time on each step */
+ .sdeqctr = { 0x01, 0x02, 0x02, 0x02 },
+ /* SDVPCTR: Normal operation off color during v porch */
+ .sdvpctr = 0x01,
+ /* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */
+ .t1 = 0x0184,
+ /* VBP: vertical back porch toward the panel */
+ .vbp = 0x1C,
+ /* VFP: vertical front porch toward the panel */
+ .vfp = 0x1C,
+ /* PSEL: divide pixel clock 23MHz with 1 (no clock downscaling) */
+ .psel = 0,
+ /* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */
+ .dpmctr12 = { 0x03, 0x00, 0x00, },
+ /* write display brightness */
+ .wrdisbv = 0x7f,
+ /* write control display */
+ .wrctrld = NT35510_WRCTRLD_BCTRL | NT35510_WRCTRLD_DD |
+ NT35510_WRCTRLD_BL,
+ /* write content adaptive brightness control */
+ .wrcabc = NT35510_WRCABC_STILL_MODE,
+ /* write CABC minimum brightness */
+ .wrcabcmb = 0xff,
+};
+
+static const struct udevice_id nt35510_panel_ids[] = {
+ {
+ .compatible = "frida,frd400b25025",
+ .data = (ulong)&nt35510_frida_frd400b25025,
+ },
+ {
+ .compatible = "hydis,hva40wv1",
+ .data = (ulong)&nt35510_hydis_hva40wv1,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(nt35510_panel) = {
+ .name = "nt35510_panel",
+ .id = UCLASS_PANEL,
+ .of_match = nt35510_panel_ids,
+ .ops = &nt35510_panel_ops,
+ .of_to_plat = nt35510_panel_of_to_plat,
+ .probe = nt35510_panel_probe,
+ .plat_auto = sizeof(struct mipi_dsi_panel_plat),
+ .priv_auto = sizeof(struct nt35510_panel_priv),
+};
diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
index 01804dc..0f4550a 100644
--- a/drivers/video/rockchip/Kconfig
+++ b/drivers/video/rockchip/Kconfig
@@ -11,6 +11,7 @@
menuconfig VIDEO_ROCKCHIP
bool "Enable Rockchip Video Support"
depends on VIDEO
+ imply VIDEO_DAMAGE
help
Rockchip SoCs provide video output capabilities for High-Definition
Multimedia Interface (HDMI), Low-voltage Differential Signalling
diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 4806606..c354c40 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -8,6 +8,7 @@
menuconfig VIDEO_STM32
bool "Enable STM32 video support"
depends on VIDEO
+ imply VIDEO_DAMAGE
help
STM32 supports many video output options including RGB and
DSI. This option enables these supports which can be used on
diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig
index d3b8dbb..1a328407 100644
--- a/drivers/video/tegra/Kconfig
+++ b/drivers/video/tegra/Kconfig
@@ -44,6 +44,7 @@
config VIDEO_TEGRA124
bool "Enable video support on Tegra124"
+ imply VIDEO_DAMAGE
help
Tegra124 supports many video output options including eDP and
HDMI. At present only eDP is supported by U-Boot. This option
diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig
index 95086f3..3291b3c 100644
--- a/drivers/video/tidss/Kconfig
+++ b/drivers/video/tidss/Kconfig
@@ -11,6 +11,7 @@
menuconfig VIDEO_TIDSS
bool "Enable TIDSS video support"
depends on VIDEO
+ imply VIDEO_DAMAGE
help
TIDSS supports video output options LVDS and
DPI . This option enables these supports which can be used on
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index ebe96bf..f1b2d61 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -127,6 +127,9 @@
priv->xcur_frac = VID_TO_POS(x);
priv->xstart_frac = priv->xcur_frac;
priv->ycur = y;
+
+ /* make sure not to kern against the previous character */
+ priv->last_ch = 0;
vidconsole_entry_start(dev);
}
@@ -508,12 +511,14 @@
return 0;
}
-int vidconsole_put_string(struct udevice *dev, const char *str)
+int vidconsole_put_stringn(struct udevice *dev, const char *str, int maxlen)
{
- const char *s;
+ const char *s, *end = NULL;
int ret;
- for (s = str; *s; s++) {
+ if (maxlen != -1)
+ end = str + maxlen;
+ for (s = str; *s && (maxlen == -1 || s < end); s++) {
ret = vidconsole_put_char(dev, *s);
if (ret)
return ret;
@@ -522,11 +527,19 @@
return 0;
}
+int vidconsole_put_string(struct udevice *dev, const char *str)
+{
+ return vidconsole_put_stringn(dev, str, -1);
+}
+
static void vidconsole_putc(struct stdio_dev *sdev, const char ch)
{
struct udevice *dev = sdev->priv;
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
int ret;
+ if (priv->quiet)
+ return;
ret = vidconsole_put_char(dev, ch);
if (ret) {
#ifdef DEBUG
@@ -544,8 +557,11 @@
static void vidconsole_puts(struct stdio_dev *sdev, const char *s)
{
struct udevice *dev = sdev->priv;
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
int ret;
+ if (priv->quiet)
+ return;
ret = vidconsole_put_string(dev, s);
if (ret) {
#ifdef DEBUG
@@ -608,14 +624,17 @@
}
int vidconsole_measure(struct udevice *dev, const char *name, uint size,
- const char *text, struct vidconsole_bbox *bbox)
+ const char *text, int limit,
+ struct vidconsole_bbox *bbox, struct alist *lines)
{
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
struct vidconsole_ops *ops = vidconsole_get_ops(dev);
int ret;
if (ops->measure) {
- ret = ops->measure(dev, name, size, text, bbox);
+ if (lines)
+ alist_empty(lines);
+ ret = ops->measure(dev, name, size, text, limit, bbox, lines);
if (ret != -ENOSYS)
return ret;
}
@@ -761,22 +780,6 @@
.per_device_auto = sizeof(struct vidconsole_priv),
};
-#ifdef CONFIG_VIDEO_COPY
-int vidconsole_sync_copy(struct udevice *dev, void *from, void *to)
-{
- struct udevice *vid = dev_get_parent(dev);
-
- return video_sync_copy(vid, from, to);
-}
-
-int vidconsole_memmove(struct udevice *dev, void *dst, const void *src,
- int size)
-{
- memmove(dst, src, size);
- return vidconsole_sync_copy(dev, dst, dst + size);
-}
-#endif
-
int vidconsole_clear_and_reset(struct udevice *dev)
{
int ret;
@@ -800,3 +803,10 @@
y = min_t(short, row * priv->y_charsize, vid_priv->ysize - 1);
vidconsole_set_cursor_pos(dev, x, y);
}
+
+void vidconsole_set_quiet(struct udevice *dev, bool quiet)
+{
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+
+ priv->quiet = quiet;
+}
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index c684c99..53641fc 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -26,6 +26,7 @@
#ifdef CONFIG_SANDBOX
#include <asm/sdl.h>
#endif
+#include "vidconsole_internal.h"
/*
* Theory of operation:
@@ -171,7 +172,7 @@
struct video_priv *priv = dev_get_uclass_priv(dev);
void *start, *line;
int pixels = xend - xstart;
- int row, i, ret;
+ int row, i;
start = priv->fb + ystart * priv->line_length;
start += xstart * VNBYTES(priv->bpix);
@@ -210,9 +211,42 @@
}
line += priv->line_length;
}
- ret = video_sync_copy(dev, start, line);
- if (ret)
- return ret;
+
+ video_damage(dev, xstart, ystart, xend - xstart, yend - ystart);
+
+ return 0;
+}
+
+int video_draw_box(struct udevice *dev, int x0, int y0, int x1, int y1,
+ int width, u32 colour)
+{
+ struct video_priv *priv = dev_get_uclass_priv(dev);
+ int pbytes = VNBYTES(priv->bpix);
+ void *start, *line;
+ int pixels = x1 - x0;
+ int row;
+
+ start = priv->fb + y0 * priv->line_length;
+ start += x0 * pbytes;
+ line = start;
+ for (row = y0; row < y1; row++) {
+ void *ptr = line;
+ int i;
+
+ for (i = 0; i < width; i++)
+ fill_pixel_and_goto_next(&ptr, colour, pbytes, pbytes);
+ if (row < y0 + width || row >= y1 - width) {
+ for (i = 0; i < pixels - width * 2; i++)
+ fill_pixel_and_goto_next(&ptr, colour, pbytes,
+ pbytes);
+ } else {
+ ptr += (pixels - width * 2) * pbytes;
+ }
+ for (i = 0; i < width; i++)
+ fill_pixel_and_goto_next(&ptr, colour, pbytes, pbytes);
+ line += priv->line_length;
+ }
+ video_damage(dev, x0, y0, x1 - x0, y1 - y0);
return 0;
}
@@ -233,7 +267,6 @@
int video_fill(struct udevice *dev, u32 colour)
{
struct video_priv *priv = dev_get_uclass_priv(dev);
- int ret;
switch (priv->bpix) {
case VIDEO_BPP16:
@@ -260,9 +293,8 @@
memset(priv->fb, colour, priv->fb_size);
break;
}
- ret = video_sync_copy(dev, priv->fb, priv->fb + priv->fb_size);
- if (ret)
- return ret;
+
+ video_damage(dev, 0, 0, priv->xsize, priv->ysize);
return video_sync(dev, false);
}
@@ -348,7 +380,7 @@
struct video_priv *priv = dev_get_uclass_priv(dev);
int fore, back;
- if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
+ if (priv->white_on_black) {
/* White is used when switching to bold, use light gray here */
fore = VID_LIGHT_GRAY;
back = VID_BLACK;
@@ -369,6 +401,95 @@
priv->colour_bg = video_index_to_colour(priv, back);
}
+/* Notify about changes in the frame buffer */
+#ifdef CONFIG_VIDEO_DAMAGE
+void video_damage(struct udevice *vid, int x, int y, int width, int height)
+{
+ struct video_priv *priv = dev_get_uclass_priv(vid);
+ int xend = x + width;
+ int yend = y + height;
+
+ if (x > priv->xsize)
+ return;
+
+ if (y > priv->ysize)
+ return;
+
+ if (xend > priv->xsize)
+ xend = priv->xsize;
+
+ if (yend > priv->ysize)
+ yend = priv->ysize;
+
+ /* Span a rectangle across all old and new damage */
+ priv->damage.xstart = min(x, priv->damage.xstart);
+ priv->damage.ystart = min(y, priv->damage.ystart);
+ priv->damage.xend = max(xend, priv->damage.xend);
+ priv->damage.yend = max(yend, priv->damage.yend);
+}
+#endif
+
+static void video_flush_dcache(struct udevice *vid, bool use_copy)
+{
+ struct video_priv *priv = dev_get_uclass_priv(vid);
+ ulong fb = use_copy ? (ulong)priv->copy_fb : (ulong)priv->fb;
+ uint cacheline_size = 32;
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+ cacheline_size = CONFIG_SYS_CACHELINE_SIZE;
+#endif
+
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ if (!priv->flush_dcache)
+ return;
+
+ if (!IS_ENABLED(CONFIG_VIDEO_DAMAGE)) {
+ flush_dcache_range(fb, ALIGN(fb + priv->fb_size,
+ cacheline_size));
+
+ return;
+ }
+
+ if (priv->damage.xend && priv->damage.yend) {
+ int lstart = priv->damage.xstart * VNBYTES(priv->bpix);
+ int lend = priv->damage.xend * VNBYTES(priv->bpix);
+ int y;
+
+ for (y = priv->damage.ystart; y < priv->damage.yend; y++) {
+ ulong start = fb + (y * priv->line_length) + lstart;
+ ulong end = start + lend - lstart;
+
+ start = ALIGN_DOWN(start, cacheline_size);
+ end = ALIGN(end, cacheline_size);
+
+ flush_dcache_range(start, end);
+ }
+ }
+}
+
+static void video_flush_copy(struct udevice *vid)
+{
+ struct video_priv *priv = dev_get_uclass_priv(vid);
+
+ if (!priv->copy_fb)
+ return;
+
+ if (priv->damage.xend && priv->damage.yend) {
+ int lstart = priv->damage.xstart * VNBYTES(priv->bpix);
+ int lend = priv->damage.xend * VNBYTES(priv->bpix);
+ int y;
+
+ for (y = priv->damage.ystart; y < priv->damage.yend; y++) {
+ ulong offset = (y * priv->line_length) + lstart;
+ ulong len = lend - lstart;
+
+ memcpy(priv->copy_fb + offset, priv->fb + offset, len);
+ }
+ }
+}
+
/* Flush video activity to the caches */
int video_sync(struct udevice *vid, bool force)
{
@@ -376,6 +497,9 @@
struct video_ops *ops = video_get_ops(vid);
int ret;
+ if (IS_ENABLED(CONFIG_VIDEO_COPY))
+ video_flush_copy(vid);
+
if (ops && ops->video_sync) {
ret = ops->video_sync(vid);
if (ret)
@@ -386,22 +510,24 @@
get_timer(priv->last_sync) < CONFIG_VIDEO_SYNC_MS)
return 0;
- /*
- * flush_dcache_range() is declared in common.h but it seems that some
- * architectures do not actually implement it. Is there a way to find
- * out whether it exists? For now, ARM is safe.
- */
-#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
- if (priv->flush_dcache) {
- flush_dcache_range((ulong)priv->fb,
- ALIGN((ulong)priv->fb + priv->fb_size,
- CONFIG_SYS_CACHELINE_SIZE));
- }
-#elif defined(CONFIG_VIDEO_SANDBOX_SDL)
+ video_flush_dcache(vid, false);
+
+ if (IS_ENABLED(CONFIG_VIDEO_COPY))
+ video_flush_dcache(vid, true);
+
+#if defined(CONFIG_VIDEO_SANDBOX_SDL)
+ /* to see the copy framebuffer, use priv->copy_fb */
sandbox_sdl_sync(priv->fb);
#endif
priv->last_sync = get_timer(0);
+ if (IS_ENABLED(CONFIG_VIDEO_DAMAGE)) {
+ priv->damage.xstart = priv->xsize;
+ priv->damage.ystart = priv->ysize;
+ priv->damage.xend = 0;
+ priv->damage.yend = 0;
+ }
+
return 0;
}
@@ -453,69 +579,6 @@
return priv->ysize;
}
-#ifdef CONFIG_VIDEO_COPY
-int video_sync_copy(struct udevice *dev, void *from, void *to)
-{
- struct video_priv *priv = dev_get_uclass_priv(dev);
-
- if (priv->copy_fb) {
- long offset, size;
-
- /* Find the offset of the first byte to copy */
- if ((ulong)to > (ulong)from) {
- size = to - from;
- offset = from - priv->fb;
- } else {
- size = from - to;
- offset = to - priv->fb;
- }
-
- /*
- * Allow a bit of leeway for valid requests somewhere near the
- * frame buffer
- */
- if (offset < -priv->fb_size || offset > 2 * priv->fb_size) {
-#ifdef DEBUG
- char str[120];
-
- snprintf(str, sizeof(str),
- "[** FAULT sync_copy fb=%p, from=%p, to=%p, offset=%lx]",
- priv->fb, from, to, offset);
- console_puts_select_stderr(true, str);
-#endif
- return -EFAULT;
- }
-
- /*
- * Silently crop the memcpy. This allows callers to avoid doing
- * this themselves. It is common for the end pointer to go a
- * few lines after the end of the frame buffer, since most of
- * the update algorithms terminate a line after their last write
- */
- if (offset + size > priv->fb_size) {
- size = priv->fb_size - offset;
- } else if (offset < 0) {
- size += offset;
- offset = 0;
- }
-
- memcpy(priv->copy_fb + offset, priv->fb + offset, size);
- }
-
- return 0;
-}
-
-int video_sync_copy_all(struct udevice *dev)
-{
- struct video_priv *priv = dev_get_uclass_priv(dev);
-
- video_sync_copy(dev, priv->fb, priv->fb + priv->fb_size);
-
- return 0;
-}
-
-#endif
-
#define SPLASH_DECL(_name) \
extern u8 __splash_ ## _name ## _begin[]; \
extern u8 __splash_ ## _name ## _end[]
@@ -555,6 +618,18 @@
video_sync_all();
}
+void video_set_white_on_black(struct udevice *dev, bool white_on_black)
+{
+ struct video_priv *priv = dev_get_uclass_priv(dev);
+
+ if (priv->white_on_black != white_on_black) {
+ priv->white_on_black = white_on_black;
+ video_set_default_colors(dev, false);
+
+ video_clear(dev);
+ }
+}
+
/* Set up the display ready for use */
static int video_post_probe(struct udevice *dev)
{
@@ -597,6 +672,8 @@
if (IS_ENABLED(CONFIG_VIDEO_COPY) && plat->copy_base)
priv->copy_fb = map_sysmem(plat->copy_base, plat->size);
+ priv->white_on_black = CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK);
+
/* Set up colors */
video_set_default_colors(dev, false);
diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index ad512d9..1f267d4 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -267,7 +267,6 @@
enum video_format eformat;
struct bmp_color_table_entry *palette;
int hdr_size;
- int ret;
if (!bmp || !(bmp->header.signature[0] == 'B' &&
bmp->header.signature[1] == 'M')) {
@@ -459,11 +458,7 @@
break;
};
- /* Find the position of the top left of the image in the framebuffer */
- fb = (uchar *)(priv->fb + y * priv->line_length + x * bpix / 8);
- ret = video_sync_copy(dev, start, fb);
- if (ret)
- return log_ret(ret);
+ video_damage(dev, x, y, width, height);
return video_sync(dev, false);
}
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
index 8eeac93..467db5f 100644
--- a/drivers/watchdog/sunxi_wdt.c
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -153,10 +153,21 @@
.wdt_key_val = 0x16aa0000,
};
+static const struct sunxi_wdt_reg sun55i_wdt_reg = {
+ .wdt_ctrl = 0x0c,
+ .wdt_cfg = 0x10,
+ .wdt_mode = 0x14,
+ .wdt_timeout_shift = 4,
+ .wdt_reset_mask = 0x03,
+ .wdt_reset_val = 0x01,
+ .wdt_key_val = 0x16aa0000,
+};
+
static const struct udevice_id sunxi_wdt_ids[] = {
{ .compatible = "allwinner,sun4i-a10-wdt", .data = (ulong)&sun4i_wdt_reg },
{ .compatible = "allwinner,sun6i-a31-wdt", .data = (ulong)&sun6i_wdt_reg },
{ .compatible = "allwinner,sun20i-d1-wdt", .data = (ulong)&sun20i_wdt_reg },
+ { .compatible = "allwinner,sun55i-a523-wdt", .data = (ulong)&sun55i_wdt_reg },
{ /* sentinel */ }
};
diff --git a/env/Kconfig b/env/Kconfig
index 9507aee..9f5ec44 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -74,7 +74,7 @@
!ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
!ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
!ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
- !ENV_IS_IN_UBI
+ !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
select ENV_IS_NOWHERE
config ENV_IS_NOWHERE
@@ -387,6 +387,25 @@
during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
aligned to an erase sector boundary.
+config ENV_IS_IN_MTD
+ bool "Environment is in MTD flash"
+ depends on !CHAIN_OF_TRUST && (SPI_FLASH || DM_SPI_FLASH)
+ default y if ARCH_AIROHA
+ help
+ Define this if you have a MTD Flash memory device which you
+ want to use for the environment.
+
+ - CONFIG_ENV_MTD_DEV:
+
+ Specifies which SPI NAND device the environment is stored in.
+
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the
+ environment area within the MTD Flash.
+ CONFIG_ENV_OFFSET must be aligned to an erase sector boundary.
+
config ENV_SECT_SIZE_AUTO
bool "Use automatically detected sector size"
depends on ENV_IS_IN_SPI_FLASH
@@ -562,8 +581,8 @@
config ENV_ADDR
hex "Environment address"
depends on ENV_IS_IN_FLASH || ENV_IS_IN_NVRAM || ENV_IS_IN_ONENAND || \
- ENV_IS_IN_REMOTE || ENV_IS_IN_SPI_FLASH
- default 0x0 if ENV_IS_IN_SPI_FLASH
+ ENV_IS_IN_REMOTE || ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD
+ default 0x0 if ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD
help
Offset from the start of the device (or partition)
@@ -577,7 +596,7 @@
config ENV_OFFSET
hex "Environment offset"
depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
- ENV_IS_IN_SPI_FLASH
+ ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD
default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
default 0xF0000 if ARCH_SUNXI
@@ -666,6 +685,12 @@
Relocate the early env_addr pointer so we know it is not inside
the binary. Some systems need this and for the rest, it doesn't hurt.
+config ENV_MTD_DEV
+ string "mtd device name"
+ depends on ENV_IS_IN_MTD
+ help
+ MTD device name on the platform where the environment is stored.
+
config SYS_MMC_ENV_DEV
int "mmc device number"
depends on ENV_IS_IN_MMC || ENV_IS_IN_FAT || ENV_IS_IN_EXT4 || \
diff --git a/env/Makefile b/env/Makefile
index a54e924..3b9c71d 100644
--- a/env/Makefile
+++ b/env/Makefile
@@ -26,6 +26,7 @@
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o
+obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o
obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
CFLAGS_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
diff --git a/env/common.c b/env/common.c
index a58955a..8612258 100644
--- a/env/common.c
+++ b/env/common.c
@@ -16,6 +16,7 @@
#include <asm/global_data.h>
#include <linux/printk.h>
#include <linux/stddef.h>
+#include <mapmem.h>
#include <search.h>
#include <errno.h>
#include <malloc.h>
@@ -368,6 +369,18 @@
return env_get_from_linear(default_environment, name, buf, len);
}
+static int env_update_fdt_addr_from_bloblist(void)
+{
+ /*
+ * fdt_addr is by default used by booti, bootm and bootefi,
+ * thus set it to point to the fdt embedded in a bloblist if it exists.
+ */
+ if (!CONFIG_IS_ENABLED(BLOBLIST) || gd->fdt_src != FDTSRC_BLOBLIST)
+ return 0;
+
+ return env_set_hex("fdt_addr", (uintptr_t)map_to_sysmem(gd->fdt_blob));
+}
+
void env_set_default(const char *s, int flags)
{
if (s) {
@@ -392,6 +405,10 @@
gd->flags |= GD_FLG_ENV_READY;
gd->flags |= GD_FLG_ENV_DEFAULT;
+
+ /* This has to be done after GD_FLG_ENV_READY is set */
+ if (env_update_fdt_addr_from_bloblist())
+ pr_err("Failed to set fdt_addr to point at DTB\n");
}
/* [re]set individual variables to their value in the default environment */
@@ -437,7 +454,9 @@
if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', flags, 0,
0, NULL)) {
gd->flags |= GD_FLG_ENV_READY;
- return 0;
+
+ /* This has to be done after GD_FLG_ENV_READY is set */
+ return env_update_fdt_addr_from_bloblist();
}
pr_err("Cannot import environment: errno = %d\n", errno);
diff --git a/env/env.c b/env/env.c
index bcc189e..dbaeedc 100644
--- a/env/env.c
+++ b/env/env.c
@@ -58,6 +58,9 @@
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
ENVL_SPI_FLASH,
#endif
+#ifdef CONFIG_ENV_IS_IN_MTD
+ ENVL_MTD,
+#endif
#ifdef CONFIG_ENV_IS_IN_UBI
ENVL_UBI,
#endif
diff --git a/env/mtd.c b/env/mtd.c
new file mode 100644
index 0000000..721faeb
--- /dev/null
+++ b/env/mtd.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <env_internal.h>
+#include <errno.h>
+#include <malloc.h>
+#include <mtd.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <linux/mtd/mtd.h>
+#include <u-boot/crc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int setup_mtd_device(struct mtd_info **mtd_env)
+{
+ struct mtd_info *mtd;
+
+ mtd_probe_devices();
+
+ mtd = get_mtd_device_nm(CONFIG_ENV_MTD_DEV);
+ if (IS_ERR_OR_NULL(mtd)) {
+ env_set_default("get_mtd_device_nm() failed", 0);
+ return mtd ? PTR_ERR(mtd) : -EINVAL;
+ }
+
+ *mtd_env = mtd;
+
+ return 0;
+}
+
+static int env_mtd_save(void)
+{
+ char *saved_buf, *write_buf, *tmp;
+ struct erase_info ei = { };
+ struct mtd_info *mtd_env;
+ u32 sect_size, sect_num;
+ size_t ret_len = 0;
+ u32 write_size;
+ env_t env_new;
+ int remaining;
+ u32 offset;
+ int ret;
+
+ ret = setup_mtd_device(&mtd_env);
+ if (ret)
+ return ret;
+
+ sect_size = mtd_env->erasesize;
+
+ /* Is the sector larger than the env (i.e. embedded) */
+ if (sect_size > CONFIG_ENV_SIZE) {
+ saved_buf = malloc(sect_size);
+ if (!saved_buf) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ offset = CONFIG_ENV_OFFSET;
+ remaining = sect_size;
+ tmp = saved_buf;
+
+ while (remaining) {
+ /* Skip the block if it is bad */
+ if (!(offset % sect_size) &&
+ mtd_block_isbad(mtd_env, offset)) {
+ offset += sect_size;
+ continue;
+ }
+
+ ret = mtd_read(mtd_env, offset, mtd_env->writesize,
+ &ret_len, tmp);
+ if (ret)
+ goto done;
+
+ tmp += ret_len;
+ offset += ret_len;
+ remaining -= ret_len;
+ }
+ }
+
+ ret = env_export(&env_new);
+ if (ret)
+ goto done;
+
+ sect_num = DIV_ROUND_UP(CONFIG_ENV_SIZE, sect_size);
+
+ ei.mtd = mtd_env;
+ ei.addr = CONFIG_ENV_OFFSET;
+ ei.len = sect_num * sect_size;
+
+ puts("Erasing MTD...");
+ ret = mtd_erase(mtd_env, &ei);
+ if (ret)
+ goto done;
+
+ if (sect_size > CONFIG_ENV_SIZE) {
+ memcpy(saved_buf, &env_new, CONFIG_ENV_SIZE);
+ write_size = sect_size;
+ write_buf = saved_buf;
+ } else {
+ write_size = sect_num * sect_size;
+ write_buf = (char *)&env_new;
+ }
+
+ offset = CONFIG_ENV_OFFSET;
+ remaining = sect_size;
+ tmp = write_buf;
+
+ puts("Writing to MTD...");
+ while (remaining) {
+ /* Skip the block if it is bad */
+ if (!(offset % sect_size) &&
+ mtd_block_isbad(mtd_env, offset)) {
+ offset += sect_size;
+ continue;
+ }
+
+ ret = mtd_write(mtd_env, offset, mtd_env->writesize,
+ &ret_len, tmp);
+ if (ret)
+ goto done;
+
+ offset += mtd_env->writesize;
+ remaining -= ret_len;
+ tmp += ret_len;
+ }
+
+ ret = 0;
+ puts("done\n");
+
+done:
+ if (saved_buf)
+ free(saved_buf);
+
+ return ret;
+}
+
+static int env_mtd_load(void)
+{
+ struct mtd_info *mtd_env;
+ char *buf, *tmp;
+ size_t ret_len;
+ int remaining;
+ u32 sect_size;
+ u32 offset;
+ int ret;
+
+ buf = (char *)memalign(ARCH_DMA_MINALIGN, CONFIG_ENV_SIZE);
+ if (!buf) {
+ env_set_default("memalign() failed", 0);
+ return -EIO;
+ }
+
+ ret = setup_mtd_device(&mtd_env);
+ if (ret)
+ goto out;
+
+ sect_size = mtd_env->erasesize;
+
+ offset = CONFIG_ENV_OFFSET;
+ remaining = CONFIG_ENV_SIZE;
+ tmp = buf;
+
+ while (remaining) {
+ /* Skip the block if it is bad */
+ if (!(offset % sect_size) &&
+ mtd_block_isbad(mtd_env, offset)) {
+ offset += sect_size;
+ continue;
+ }
+
+ ret = mtd_read(mtd_env, offset, mtd_env->writesize,
+ &ret_len, tmp);
+ if (ret) {
+ env_set_default("mtd_read() failed", 1);
+ goto out;
+ }
+
+ tmp += ret_len;
+ offset += ret_len;
+ remaining -= ret_len;
+ }
+
+ ret = env_import(buf, 1, H_EXTERNAL);
+ if (!ret)
+ gd->env_valid = ENV_VALID;
+
+out:
+ free(buf);
+
+ return ret;
+}
+
+static int env_mtd_erase(void)
+{
+ struct mtd_info *mtd_env;
+ u32 sect_size, sect_num;
+ char *saved_buf, *tmp;
+ struct erase_info ei;
+ size_t ret_len;
+ int remaining;
+ u32 offset;
+ int ret;
+
+ ret = setup_mtd_device(&mtd_env);
+ if (ret)
+ return ret;
+
+ sect_size = mtd_env->erasesize;
+
+ /* Is the sector larger than the env (i.e. embedded) */
+ if (sect_size > CONFIG_ENV_SIZE) {
+ saved_buf = malloc(sect_size);
+ if (!saved_buf) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ offset = CONFIG_ENV_OFFSET;
+ remaining = sect_size;
+ tmp = saved_buf;
+
+ while (remaining) {
+ /* Skip the block if it is bad */
+ if (!(offset % sect_size) &&
+ mtd_block_isbad(mtd_env, offset)) {
+ offset += sect_size;
+ continue;
+ }
+
+ ret = mtd_read(mtd_env, offset, mtd_env->writesize,
+ &ret_len, tmp);
+ if (ret)
+ goto done;
+
+ tmp += ret_len;
+ offset += ret_len;
+ remaining -= ret_len;
+ }
+ }
+
+ sect_num = DIV_ROUND_UP(CONFIG_ENV_SIZE, sect_size);
+
+ ei.mtd = mtd_env;
+ ei.addr = CONFIG_ENV_OFFSET;
+ ei.len = sect_num * sect_size;
+
+ ret = mtd_erase(mtd_env, &ei);
+ if (ret)
+ goto done;
+
+ if (sect_size > CONFIG_ENV_SIZE) {
+ memset(saved_buf, 0, CONFIG_ENV_SIZE);
+
+ offset = CONFIG_ENV_OFFSET;
+ remaining = sect_size;
+ tmp = saved_buf;
+
+ while (remaining) {
+ /* Skip the block if it is bad */
+ if (!(offset % sect_size) &&
+ mtd_block_isbad(mtd_env, offset)) {
+ offset += sect_size;
+ continue;
+ }
+
+ ret = mtd_write(mtd_env, offset, mtd_env->writesize,
+ &ret_len, tmp);
+ if (ret)
+ goto done;
+
+ offset += mtd_env->writesize;
+ remaining -= ret_len;
+ tmp += ret_len;
+ }
+ }
+
+ ret = 0;
+
+done:
+ if (saved_buf)
+ free(saved_buf);
+
+ return ret;
+}
+
+__weak void *env_mtd_get_env_addr(void)
+{
+ return (void *)CONFIG_ENV_ADDR;
+}
+
+/*
+ * Check if Environment on CONFIG_ENV_ADDR is valid.
+ */
+static int env_mtd_init_addr(void)
+{
+ env_t *env_ptr = (env_t *)env_mtd_get_env_addr();
+
+ if (!env_ptr)
+ return -ENOENT;
+
+ if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+ gd->env_addr = (ulong)&env_ptr->data;
+ gd->env_valid = ENV_VALID;
+ } else {
+ gd->env_valid = ENV_INVALID;
+ }
+
+ return 0;
+}
+
+static int env_mtd_init(void)
+{
+ int ret;
+
+ ret = env_mtd_init_addr();
+ if (ret != -ENOENT)
+ return ret;
+
+ /*
+ * return here -ENOENT, so env_init()
+ * can set the init bit and later if no
+ * other Environment storage is defined
+ * can set the default environment
+ */
+ return -ENOENT;
+}
+
+U_BOOT_ENV_LOCATION(mtd) = {
+ .location = ENVL_MTD,
+ ENV_NAME("MTD")
+ .load = env_mtd_load,
+ .save = ENV_SAVE_PTR(env_mtd_save),
+ .erase = ENV_ERASE_PTR(env_mtd_erase),
+ .init = env_mtd_init,
+};
diff --git a/fs/exfat/exfat.h b/fs/exfat/exfat.h
index cce3e30..ca6f22b 100644
--- a/fs/exfat/exfat.h
+++ b/fs/exfat/exfat.h
@@ -210,9 +210,11 @@
uint32_t exfat_vbr_add_checksum(const void* sector, size_t size, uint32_t sum);
le16_t exfat_calc_name_hash(const struct exfat* ef, const le16_t* name,
size_t length);
+#ifndef __UBOOT__
void exfat_humanize_bytes(uint64_t value, struct exfat_human_bytes* hb);
void exfat_print_info(const struct exfat_super_block* sb,
uint32_t free_clusters);
+#endif
bool exfat_match_option(const char* options, const char* option_name);
int exfat_utf16_to_utf8(char* output, const le16_t* input, size_t outsize,
diff --git a/fs/exfat/io.c b/fs/exfat/io.c
index c56f567..77cd2df 100644
--- a/fs/exfat/io.c
+++ b/fs/exfat/io.c
@@ -720,6 +720,9 @@
struct exfat_node *dnode;
int err;
+ if (strlen(filename) >= PATH_MAX)
+ return -ENAMETOOLONG;
+
err = exfat_lookup_realpath(&ctxt.ef, &dnode, filename);
if (err)
return err;
@@ -736,7 +739,7 @@
if (!dirs)
return -ENOMEM;
- strcpy(dirs->dirname, filename);
+ strncpy(dirs->dirname, filename, PATH_MAX - 1);
dirs->offset = -1;
*dirsp = &dirs->fs_dirs;
diff --git a/fs/exfat/utils.c b/fs/exfat/utils.c
index 0d97b65..f99dcba 100644
--- a/fs/exfat/utils.c
+++ b/fs/exfat/utils.c
@@ -134,6 +134,7 @@
return cpu_to_le16(hash);
}
+#ifndef __UBOOT__
void exfat_humanize_bytes(uint64_t value, struct exfat_human_bytes* hb)
{
size_t i;
@@ -178,6 +179,7 @@
exfat_humanize_bytes(avail_space, &hb);
printf("Available space %10"PRIu64" %s\n", hb.value, hb.unit);
}
+#endif
bool exfat_match_option(const char* options, const char* option_name)
{
diff --git a/include/axp221.h b/include/axp221.h
index 32b988f..8a4a3cc 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -53,10 +53,6 @@
#ifdef CONFIG_AXP221_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
diff --git a/include/axp809.h b/include/axp809.h
index 71a7cb2..3bd71b3 100644
--- a/include/axp809.h
+++ b/include/axp809.h
@@ -47,10 +47,6 @@
#ifdef CONFIG_AXP809_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
diff --git a/include/axp818.h b/include/axp818.h
index 08ac35d..b3a9686 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -61,10 +61,6 @@
#ifdef CONFIG_AXP818_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 8ac3a4f..7b6ac6e 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -194,6 +194,11 @@
#define SCAN_DEV_FOR_EFI
#endif
+#ifndef SCAN_DEV_FOR_BOOT_PARTS
+#define SCAN_DEV_FOR_BOOT_PARTS \
+ "part list ${devtype} ${devnum} -bootable devplist; "
+#endif
+
#ifdef CONFIG_SATA
#define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata)
#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV
@@ -538,7 +543,7 @@
"\0" \
\
"scan_dev_for_boot_part=" \
- "part list ${devtype} ${devnum} -bootable devplist; " \
+ SCAN_DEV_FOR_BOOT_PARTS \
"env exists devplist || setenv devplist 1; " \
"for distro_bootpart in ${devplist}; do " \
"if fstype ${devtype} " \
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index cf43fc0..d2164b4 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -126,6 +126,8 @@
"setenv fdtfile am335x-bonegreen.dtb; fi; " \
"if test $board_name = BBGW; then " \
"setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \
+ "if test $board_name = BBGE; then " \
+ "setenv fdtfile am335x-bonegreen-eco.dtb; fi; " \
"if test $board_name = BBBL; then " \
"setenv fdtfile am335x-boneblue.dtb; fi; " \
"if test $board_name = BBEN; then " \
diff --git a/include/configs/imx95_evk.h b/include/configs/imx95_evk.h
new file mode 100644
index 0000000..2eebdad
--- /dev/null
+++ b/include/configs/imx95_evk.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __IMX95_EVK_H
+#define __IMX95_EVK_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_INIT_RAM_ADDR 0x90000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CFG_SYS_SDRAM_BASE 0x90000000
+#define PHYS_SDRAM 0x90000000
+/* Totally 16GB */
+#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */
+#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB */
+
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+#endif
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 00ec9ef..e6f8dee 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -30,7 +30,7 @@
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xC0008000\0" \
- "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0" \
+ "fdtfile="CONFIG_DEFAULT_FDT_FILE".dtb\0" \
"fdt_addr_r=0xC0408000\0" \
"scriptaddr=0xC0418000\0" \
"pxefile_addr_r=0xC0428000\0" \
diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h
index c004a8c..267e344 100644
--- a/include/configs/stm32mp15_dh_dhsom.h
+++ b/include/configs/stm32mp15_dh_dhsom.h
@@ -17,7 +17,40 @@
" 0x800000\0"
#endif
+/* Add the search for AB partitons */
+#define SCAN_DEV_FOR_BOOT_PARTS \
+ "run dh_check_if_ab; " \
+ "if test -z \"${devplist}\"; " \
+ "then " \
+ "part list ${devtype} ${devnum} -bootable devplist; " \
+ "fi; "
+
#define STM32MP_BOARD_EXTRA_ENV \
+ "altbootcmd= " \
+ "setenv dh_ab_get_partnames " \
+ "'setenv dh_ab_partnames ${dh_ab_partname_secondary} " \
+ "${dh_ab_partname_primary}' && " \
+ "run bootcmd\0" \
+ "dh_check_if_ab= " /* Sets devplist if AB partitions*/ \
+ "echo test for AB on ${devtype} ${devnum} && " \
+ "run dh_ab_get_partnames && " \
+ "setenv devplist && " \
+ "for partname in ${dh_ab_partnames}; do " \
+ "setenv partnum && " \
+ "if part number ${devtype} ${devnum} ${partname} partnum; "\
+ "then " \
+ "setenv devplist \"${devplist} ${partnum}\" && "\
+ "setenv bootretry 60 ;" \
+ "fi; " \
+ "done ; " \
+ "if test -n \"${devplist}\"; " \
+ "then echo AB partitions found! ; " \
+ "fi\0" \
+ "dh_ab_get_partnames= " /* Sets dh_ab_partnames */ \
+ "setenv dh_ab_partnames ${dh_ab_partname_primary} " \
+ "${dh_ab_partname_secondary}\0" \
+ "dh_ab_partname_primary=rootfs-a\0" /* Names of AB partitions */\
+ "dh_ab_partname_secondary=rootfs-b\0" \
"dh_preboot=" \
"run dh_testbench_backward_compat\0" \
"dh_update_sd_to_emmc=" /* Install U-Boot from SD to eMMC */ \
diff --git a/include/configs/stm32mp25_common.h b/include/configs/stm32mp25_common.h
index ec980ee..b42316f 100644
--- a/include/configs/stm32mp25_common.h
+++ b/include/configs/stm32mp25_common.h
@@ -21,4 +21,106 @@
*/
#define CFG_SYS_BOOTMAPSZ SZ_256M
+/*****************************************************************************/
+#ifdef CONFIG_DISTRO_DEFAULTS
+/*****************************************************************************/
+
+#ifdef CONFIG_NET
+#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0)
+#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1)
+#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2)
+#else
+#define BOOT_TARGET_MMC0(func)
+#define BOOT_TARGET_MMC1(func)
+#define BOOT_TARGET_MMC2(func)
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot)
+#else
+#define BOOT_TARGET_UBIFS(func)
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_MMC1(func) \
+ BOOT_TARGET_UBIFS(func) \
+ BOOT_TARGET_MMC0(func) \
+ BOOT_TARGET_MMC2(func) \
+ BOOT_TARGET_USB(func) \
+ BOOT_TARGET_PXE(func)
+
+/*
+ * default bootcmd for stm32mp25:
+ * for serial/usb: execute the stm32prog command
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for NAND or SPI-NAND boot, distro boot with UBIFS on UBI partition
+ * for other boot, use the default distro order in ${boot_targets}
+ */
+#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+ "then stm32prog ${boot_device} ${boot_instance}; " \
+ "else " \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "if test ${boot_device} = nand ||" \
+ " test ${boot_device} = spi-nand ;" \
+ "then env set boot_targets ubifs0; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#ifndef STM32MP_BOARD_EXTRA_ENV
+#define STM32MP_BOARD_EXTRA_ENV
+#endif
+
+#define STM32MP_EXTRA \
+ "env_check=if env info -p -d -q; then env save; fi\0" \
+ "boot_net_usb_start=true\0"
+/*
+ * memory layout for 96MB uncompressed/compressed kernel,
+ * 1M fdt, 1M script, 1M pxe and 1M for overlay
+ * and the ramdisk at the end.
+ */
+#define __KERNEL_COMP_ADDR_R __stringify(0x84000000)
+#define __KERNEL_COMP_SIZE_R __stringify(0x04000000)
+#define __KERNEL_ADDR_R __stringify(0x8a000000)
+#define __FDT_ADDR_R __stringify(0x90000000)
+#define __SCRIPT_ADDR_R __stringify(0x90100000)
+#define __PXEFILE_ADDR_R __stringify(0x90200000)
+#define __FDTOVERLAY_ADDR_R __stringify(0x90300000)
+#define __RAMDISK_ADDR_R __stringify(0x90400000)
+
+#define STM32MP_MEM_LAYOUT \
+ "kernel_addr_r=" __KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" __FDT_ADDR_R "\0" \
+ "scriptaddr=" __SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \
+ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \
+ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" \
+ "kernel_comp_addr_r=" __KERNEL_COMP_ADDR_R "\0" \
+ "kernel_comp_size=" __KERNEL_COMP_SIZE_R "\0"
+
+#include <config_distro_bootcmd.h>
+#define CFG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ STM32MP_BOOTCMD \
+ BOOTENV \
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
+
+#endif
+
#endif /* __CONFIG_STM32MP25_COMMMON_H */
diff --git a/include/configs/stm32mp25_st_common.h b/include/configs/stm32mp25_st_common.h
new file mode 100644
index 0000000..ab5a4a9
--- /dev/null
+++ b/include/configs/stm32mp25_st_common.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STMicroelectonics STM32MP25x boards
+ */
+
+#ifndef __CONFIG_STM32MP25_ST_COMMON_H__
+#define __CONFIG_STM32MP25_ST_COMMON_H__
+
+#define STM32MP_BOARD_EXTRA_ENV \
+ "usb_pgood_delay=2000\0" \
+ "console=ttySTM0\0"
+
+#include <configs/stm32mp25_common.h>
+
+#ifdef CFG_EXTRA_ENV_SETTINGS
+/*
+ * default bootcmd for stm32mp25 STMicroelectronics boards:
+ * for serial/usb: execute the stm32prog command
+ * for mmc boot (eMMC, SD card), distro boot on the same mmc device
+ * for nand or spi-nand boot, distro boot with ubifs on UBI partition or
+ * sdcard
+ * for nor boot, distro boot on SD card = mmc0 ONLY !
+ */
+#define ST_STM32MP25_BOOTCMD "bootcmd_stm32mp=" \
+ "echo \"Boot over ${boot_device}${boot_instance}!\";" \
+ "if test ${boot_device} = serial || test ${boot_device} = usb;" \
+ "then stm32prog ${boot_device} ${boot_instance}; " \
+ "else " \
+ "run env_check;" \
+ "if test ${boot_device} = mmc;" \
+ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+ "if test ${boot_device} = nand ||" \
+ " test ${boot_device} = spi-nand ;" \
+ "then env set boot_targets ubifs0 mmc0; fi;" \
+ "if test ${boot_device} = nor;" \
+ "then env set boot_targets mmc0; fi;" \
+ "run distro_bootcmd;" \
+ "fi;\0"
+
+#undef CFG_EXTRA_ENV_SETTINGS
+#define CFG_EXTRA_ENV_SETTINGS \
+ STM32MP_MEM_LAYOUT \
+ ST_STM32MP25_BOOTCMD \
+ BOOTENV \
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
+
+#endif
+#endif
diff --git a/include/console.h b/include/console.h
index 57fdb08..8d0d7bb 100644
--- a/include/console.h
+++ b/include/console.h
@@ -170,6 +170,21 @@
void console_puts_select_stderr(bool serial_only, const char *s);
/**
+ * console_printf_select_stderr() - Output a formatted string to selected devs
+ *
+ * This writes to stderr only. It is useful for outputting errors. Note that it
+ * uses its own buffer, separate from the print buffer, to allow printing
+ * messages within console/stdio code
+ *
+ * @serial_only: true to output only to serial, false to output to everything
+ * else
+ * @fmt: Printf format string, followed by format arguments
+ * Return: number of characters written
+ */
+int console_printf_select_stderr(bool serial_only, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 2, 3)));
+
+/**
* console_clear() - Clear the console
*
* Uses an ANSI sequence to clear the display, failing back to clearing the
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
deleted file mode 100644
index 082edd9..0000000
--- a/include/dt-bindings/clock/stih407-clks.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This header provides constants clk index STMicroelectronics
- * STiH407 SoC.
- */
-#ifndef _DT_BINDINGS_CLK_STIH407
-#define _DT_BINDINGS_CLK_STIH407
-
-/* CLOCKGEN A0 */
-#define CLK_IC_LMI0 0
-#define CLK_IC_LMI1 1
-
-/* CLOCKGEN C0 */
-#define CLK_ICN_GPU 0
-#define CLK_FDMA 1
-#define CLK_NAND 2
-#define CLK_HVA 3
-#define CLK_PROC_STFE 4
-#define CLK_PROC_TP 5
-#define CLK_RX_ICN_DMU 6
-#define CLK_RX_ICN_DISP_0 6
-#define CLK_RX_ICN_DISP_1 6
-#define CLK_RX_ICN_HVA 7
-#define CLK_RX_ICN_TS 7
-#define CLK_ICN_CPU 8
-#define CLK_TX_ICN_DMU 9
-#define CLK_TX_ICN_HVA 9
-#define CLK_TX_ICN_TS 9
-#define CLK_ICN_COMPO 9
-#define CLK_MMC_0 10
-#define CLK_MMC_1 11
-#define CLK_JPEGDEC 12
-#define CLK_ICN_REG 13
-#define CLK_TRACE_A9 13
-#define CLK_PTI_STM 13
-#define CLK_EXT2F_A9 13
-#define CLK_IC_BDISP_0 14
-#define CLK_IC_BDISP_1 15
-#define CLK_PP_DMU 16
-#define CLK_VID_DMU 17
-#define CLK_DSS_LPC 18
-#define CLK_ST231_AUD_0 19
-#define CLK_ST231_GP_0 19
-#define CLK_ST231_GP_1 20
-#define CLK_ST231_DMU 21
-#define CLK_ICN_LMI 22
-#define CLK_TX_ICN_DISP_0 23
-#define CLK_TX_ICN_DISP_1 23
-#define CLK_ICN_SBC 24
-#define CLK_STFE_FRC2 25
-#define CLK_ETH_PHY 26
-#define CLK_ETH_REF_PHYCLK 27
-#define CLK_FLASH_PROMIP 28
-#define CLK_MAIN_DISP 29
-#define CLK_AUX_DISP 30
-#define CLK_COMPO_DVP 31
-
-/* CLOCKGEN D0 */
-#define CLK_PCM_0 0
-#define CLK_PCM_1 1
-#define CLK_PCM_2 2
-#define CLK_SPDIFF 3
-
-/* CLOCKGEN D2 */
-#define CLK_PIX_MAIN_DISP 0
-#define CLK_PIX_PIP 1
-#define CLK_PIX_GDP1 2
-#define CLK_PIX_GDP2 3
-#define CLK_PIX_GDP3 4
-#define CLK_PIX_GDP4 5
-#define CLK_PIX_AUX_DISP 6
-#define CLK_DENC 7
-#define CLK_PIX_HDDAC 8
-#define CLK_HDDAC 9
-#define CLK_SDDAC 10
-#define CLK_PIX_DVO 11
-#define CLK_DVO 12
-#define CLK_PIX_HDMI 13
-#define CLK_TMDS_HDMI 14
-#define CLK_REF_HDMIPHY 15
-
-/* CLOCKGEN D3 */
-#define CLK_STFE_FRC1 0
-#define CLK_TSOUT_0 1
-#define CLK_TSOUT_1 2
-#define CLK_MCHI 3
-#define CLK_VSENS_COMPO 4
-#define CLK_FRC1_REMOTE 5
-#define CLK_LPC_0 6
-#define CLK_LPC_1 7
-#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
deleted file mode 100644
index 2097a4b..0000000
--- a/include/dt-bindings/clock/stih410-clks.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This header provides constants clk index STMicroelectronics
- * STiH410 SoC.
- */
-#ifndef _DT_BINDINGS_CLK_STIH410
-#define _DT_BINDINGS_CLK_STIH410
-
-#include "stih407-clks.h"
-
-/* STiH410 introduces new clock outputs compared to STiH407 */
-
-/* CLOCKGEN C0 */
-#define CLK_TX_ICN_HADES 32
-#define CLK_RX_ICN_HADES 33
-#define CLK_ICN_REG_16 34
-#define CLK_PP_HADES 35
-#define CLK_CLUST_HADES 36
-#define CLK_HWPE_HADES 37
-#define CLK_FC_HADES 38
-
-/* CLOCKGEN D0 */
-#define CLK_PCMR10_MASTER 4
-#define CLK_USB2_PHY 5
-
-#endif
diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h
deleted file mode 100644
index d05894a..0000000
--- a/include/dt-bindings/mfd/st-lpc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This header provides shared DT/Driver defines for ST's LPC device
- *
- * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved
- *
- * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics
- */
-
-#ifndef __DT_BINDINGS_ST_LPC_H__
-#define __DT_BINDINGS_ST_LPC_H__
-
-#define ST_LPC_MODE_RTC 0
-#define ST_LPC_MODE_WDT 1
-#define ST_LPC_MODE_CLKSRC 2
-
-#endif /* __DT_BINDINGS_ST_LPC_H__ */
diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h
deleted file mode 100644
index 4ab3a1c..0000000
--- a/include/dt-bindings/reset/stih407-resets.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This header provides constants for the reset controller
- * based peripheral powerdown requests on the STMicroelectronics
- * STiH407 SoC.
- */
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
-#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
-
-/* Powerdown requests control 0 */
-#define STIH407_EMISS_POWERDOWN 0
-#define STIH407_NAND_POWERDOWN 1
-
-/* Synp GMAC PowerDown */
-#define STIH407_ETH1_POWERDOWN 2
-
-/* Powerdown requests control 1 */
-#define STIH407_USB3_POWERDOWN 3
-#define STIH407_USB2_PORT1_POWERDOWN 4
-#define STIH407_USB2_PORT0_POWERDOWN 5
-#define STIH407_PCIE1_POWERDOWN 6
-#define STIH407_PCIE0_POWERDOWN 7
-#define STIH407_SATA1_POWERDOWN 8
-#define STIH407_SATA0_POWERDOWN 9
-
-/* Reset defines */
-#define STIH407_ETH1_SOFTRESET 0
-#define STIH407_MMC1_SOFTRESET 1
-#define STIH407_PICOPHY_SOFTRESET 2
-#define STIH407_IRB_SOFTRESET 3
-#define STIH407_PCIE0_SOFTRESET 4
-#define STIH407_PCIE1_SOFTRESET 5
-#define STIH407_SATA0_SOFTRESET 6
-#define STIH407_SATA1_SOFTRESET 7
-#define STIH407_MIPHY0_SOFTRESET 8
-#define STIH407_MIPHY1_SOFTRESET 9
-#define STIH407_MIPHY2_SOFTRESET 10
-#define STIH407_SATA0_PWR_SOFTRESET 11
-#define STIH407_SATA1_PWR_SOFTRESET 12
-#define STIH407_DELTA_SOFTRESET 13
-#define STIH407_BLITTER_SOFTRESET 14
-#define STIH407_HDTVOUT_SOFTRESET 15
-#define STIH407_HDQVDP_SOFTRESET 16
-#define STIH407_VDP_AUX_SOFTRESET 17
-#define STIH407_COMPO_SOFTRESET 18
-#define STIH407_HDMI_TX_PHY_SOFTRESET 19
-#define STIH407_JPEG_DEC_SOFTRESET 20
-#define STIH407_VP8_DEC_SOFTRESET 21
-#define STIH407_GPU_SOFTRESET 22
-#define STIH407_HVA_SOFTRESET 23
-#define STIH407_ERAM_HVA_SOFTRESET 24
-#define STIH407_LPM_SOFTRESET 25
-#define STIH407_KEYSCAN_SOFTRESET 26
-#define STIH407_USB2_PORT0_SOFTRESET 27
-#define STIH407_USB2_PORT1_SOFTRESET 28
-#define STIH407_ST231_AUD_SOFTRESET 29
-#define STIH407_ST231_DMU_SOFTRESET 30
-#define STIH407_ST231_GP0_SOFTRESET 31
-#define STIH407_ST231_GP1_SOFTRESET 32
-
-/* Picophy reset defines */
-#define STIH407_PICOPHY0_RESET 0
-#define STIH407_PICOPHY1_RESET 1
-#define STIH407_PICOPHY2_RESET 2
-
-#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 144b749..84e8cfe 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -597,6 +597,8 @@
void *efi_get_configuration_table(const efi_guid_t *guid);
/* Install device tree */
efi_status_t efi_install_fdt(void *fdt);
+/* Install initrd */
+efi_status_t efi_install_initrd(void *initrd, size_t initd_sz);
/* Execute loaded UEFI image */
efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options);
/* Run loaded UEFI image with given fdt */
diff --git a/include/env_internal.h b/include/env_internal.h
index c1c0727..ee939ba 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -113,6 +113,7 @@
ENVL_ONENAND,
ENVL_REMOTE,
ENVL_SPI_FLASH,
+ ENVL_MTD,
ENVL_UBI,
ENVL_NOWHERE,
diff --git a/include/event.h b/include/event.h
index 75141a1..1d267f1 100644
--- a/include/event.h
+++ b/include/event.h
@@ -154,6 +154,15 @@
EVT_MAIN_LOOP,
/**
+ * @EVT_OF_LIVE_BUILT:
+ * This event is triggered immediately after the live device tree has been
+ * built. This allows for machine specific fixups to be done to the live tree
+ * (like disabling known-unsupported devices) before it is used. This
+ * event is only available if OF_LIVE is enabled and is only used after relocation.
+ */
+ EVT_OF_LIVE_BUILT,
+
+ /**
* @EVT_COUNT:
* This constants holds the maximum event number + 1 and is used when
* looping over all event classes.
@@ -203,6 +212,15 @@
oftree tree;
struct bootm_headers *images;
} ft_fixup;
+
+ /**
+ * struct event_of_live_built - livetree has been built
+ *
+ * @root: The root node of the live device tree
+ */
+ struct event_of_live_built {
+ struct device_node *root;
+ } of_live_built;
};
/**
diff --git a/include/imx8image.h b/include/imx8image.h
index 6b95e93..e0d25c5 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -157,7 +157,9 @@
CMD_SOC_TYPE,
CMD_CONTAINER,
CMD_IMAGE,
- CMD_DATA
+ CMD_DATA,
+ CMD_DUMMY_V2X,
+ CMD_HOLD,
};
enum imx8image_core_type {
@@ -169,7 +171,9 @@
CFG_A35,
CFG_A55,
CFG_A53,
- CFG_A72
+ CFG_A72,
+ CFG_M33,
+ CFG_OEI,
};
enum imx8image_fld_types {
@@ -208,7 +212,10 @@
FILEOFF,
MSG_BLOCK,
SENTINEL,
- UPOWER
+ UPOWER,
+ OEI,
+ DUMMY_V2X,
+ HOLD,
} option_type_t;
typedef struct {
@@ -227,12 +234,16 @@
#define CORE_CA35 4
#define CORE_CA72 5
#define CORE_SECO 6
+#define CORE_M33 7
#define CORE_ULP_CM33 0x1
#define CORE_ULP_CA35 0x2
#define CORE_ULP_UPOWER 0x4
#define CORE_ULP_SENTINEL 0x6
+#define CORE_IMX95_M33P 0
+#define CORE_IMX95_A55C0 2
+
#define SC_R_OTP 357U
#define SC_R_DEBUG 354U
#define SC_R_ROM_0 236U
@@ -246,10 +257,12 @@
#define IMG_TYPE_EXEC 0x03 /* Executable image type */
#define IMG_TYPE_DATA 0x04 /* Data image type */
#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
+#define IMG_TYPE_OEI 0x05 /* Optional Executable image type */
#define IMG_TYPE_SECO 0x06 /* SECO image type */
#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
#define IMG_TYPE_PROV 0x07 /* Provisioning image type */
#define IMG_TYPE_DEK 0x08 /* DEK validation type */
+#define IMG_TYPE_V2X_DUMMY 0x0E /* V2X Dummy image */
#define IMG_TYPE_SHIFT 0
#define IMG_TYPE_MASK 0x1f
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index b8b207f..4eef4ab 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -569,7 +569,7 @@
u8 rdsr_dummy;
u8 rdsr_addr_nbytes;
u8 addr_mode_nbytes;
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
u8 bank_read_cmd;
u8 bank_write_cmd;
u8 bank_curr;
diff --git a/include/lmb.h b/include/lmb.h
index 0d316c6..606a92c 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -27,9 +27,9 @@
* %LMB_NONOTIFY: Do not notify other modules of changes to this memory region
*/
#define LMB_NONE 0
-#define LMB_NOMAP BIT(0)
-#define LMB_NOOVERWRITE BIT(1)
-#define LMB_NONOTIFY BIT(2)
+#define LMB_NOMAP BIT(1)
+#define LMB_NOOVERWRITE BIT(2)
+#define LMB_NONOTIFY BIT(3)
/**
* enum lmb_map_op - memory map operation
diff --git a/include/pci_ids.h b/include/pci_ids.h
index a8939b1..cfff275 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2725,6 +2725,7 @@
#define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c
#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15fd
#define PCI_DEVICE_ID_INTEL_I225_IT 0x0d9f
+#define PCI_DEVICE_ID_INTEL_I225_V 0x15f3
#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960
#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h
index 33e0e18..d6586eb 100644
--- a/include/scmi_agent-uclass.h
+++ b/include/scmi_agent-uclass.h
@@ -27,6 +27,7 @@
* @clock_dev: SCMI clock protocol device
* @resetdom_dev: SCMI reset domain protocol device
* @voltagedom_dev: SCMI voltage domain protocol device
+ * @pinctrl_dev: SCMI pin control protocol device
*/
struct scmi_agent_priv {
u32 version;
@@ -43,6 +44,7 @@
struct udevice *clock_dev;
struct udevice *resetdom_dev;
struct udevice *voltagedom_dev;
+ struct udevice *pinctrl_dev;
};
static inline u32 scmi_version(struct udevice *dev)
@@ -115,4 +117,19 @@
struct scmi_msg *msg);
};
+struct scmi_proto_match {
+ unsigned int proto_id;
+};
+
+struct scmi_proto_driver {
+ struct driver *driver;
+ const struct scmi_proto_match *match;
+};
+
+#define U_BOOT_SCMI_PROTO_DRIVER(__name, __match) \
+ ll_entry_declare(struct scmi_proto_driver, __name, scmi_proto_driver) = { \
+ .driver = llsym(struct driver, __name, driver), \
+ .match = __match, \
+ }
+
#endif /* _SCMI_TRANSPORT_UCLASS_H */
diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 7abb2a6..9046de7 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -24,6 +24,8 @@
SCMI_PROTOCOL_ID_SENSOR = 0x15,
SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17,
+ SCMI_PROTOCOL_ID_PINCTRL = 0x19,
+ SCMI_PROTOCOL_ID_IMX_MISC = 0x84,
};
enum scmi_status_code {
@@ -49,6 +51,10 @@
SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
};
+enum scmi_imx_misc_message_id {
+ SCMI_MISC_ROM_PASSOVER_GET = 0x7
+};
+
/*
* SCMI Base Protocol
*/
@@ -139,7 +145,7 @@
struct scmi_base_discover_list_protocols_out {
s32 status;
u32 num_protocols;
- u32 protocols[3];
+ u32 protocols[];
};
/**
@@ -725,12 +731,15 @@
/*
* SCMI Clock Protocol
*/
+#define CLOCK_PROTOCOL_VERSION_3_0 0x30000
enum scmi_clock_message_id {
SCMI_CLOCK_ATTRIBUTES = 0x3,
SCMI_CLOCK_RATE_SET = 0x5,
SCMI_CLOCK_RATE_GET = 0x6,
SCMI_CLOCK_CONFIG_SET = 0x7,
+ SCMI_CLOCK_PARENT_SET = 0xD,
+ SCMI_CLOCK_GET_PERMISSIONS = 0xF,
};
#define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0)
@@ -769,6 +778,7 @@
struct scmi_clk_attribute_out {
s32 status;
u32 attributes;
+#define CLK_HAS_RESTRICTIONS(x) ((x) & BIT(1))
char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX];
};
@@ -833,6 +843,45 @@
s32 status;
};
+/**
+ * struct scmi_clk_parent_state_in - Message payload for CLOCK_PARENT_SET command
+ * @clock_id: SCMI clock ID
+ * @parent_clk: SCMI clock ID
+ */
+struct scmi_clk_parent_set_in {
+ u32 clock_id;
+ u32 parent_clk;
+};
+
+/**
+ * struct scmi_clk_parent_set_out - Response payload for CLOCK_PARENT_SET command
+ * @status: SCMI command status
+ */
+struct scmi_clk_parent_set_out {
+ s32 status;
+};
+
+/**
+ * @clock_id: Identifier for the clock device.
+ */
+struct scmi_clk_get_permissions_in {
+ u32 clock_id;
+};
+
+/**
+ * @status: Negative 32-bit integers are used to return error status codes.
+ * @permissions: Bit[31] Clock state control, Bit[30] Clock parent control,
+ * Bit[29] Clock rate control, Bits[28:0] Reserved, must be zero.
+ */
+struct scmi_clk_get_permissions_out {
+ s32 status;
+ u32 permissions;
+};
+
+#define SUPPORT_CLK_STAT_CONTROL BIT(31)
+#define SUPPORT_CLK_PARENT_CONTROL BIT(30)
+#define SUPPORT_CLK_RATE_CONTROL BIT(29)
+
/*
* SCMI Reset Domain Protocol
*/
@@ -1005,4 +1054,57 @@
s32 voltage_level;
};
+/* SCMI Pinctrl Protocol */
+enum scmi_pinctrl_message_id {
+ SCMI_MSG_PINCTRL_CONFIG_SET = 0x6
+};
+
+struct scmi_pin_config {
+ u32 type;
+ u32 val;
+};
+
+/**
+ * struct scmi_pad_config_set_in - Message payload for PAD_CONFIG_SET command
+ * @identifier: Identifier for the pin or group.
+ * @function_id: Identifier for the function selected to be enabled
+ * for the selected pin or group. This field is set to
+ * 0xFFFFFFFF if no function should be enabled by the
+ * pin or group.
+ * @attributes: Bits[31:11] Reserved, must be zero.
+ * Bit[10] Function valid.
+ * Bits[9:2] Number of configurations to set.
+ * Bits[1:0] Selector: Whether the identifier field
+ * refers to a pin or a group.
+ * @configs: Array of configurations.
+ */
+struct scmi_pinctrl_config_set_in {
+ u32 identifier;
+ u32 function_id;
+ u32 attributes;
+ struct scmi_pin_config configs[4];
+};
+
+struct scmi_pinctrl_config_set_out {
+ s32 status;
+};
+
+/* SCMI Perf Protocol */
+enum scmi_perf_message_id {
+ SCMI_PERF_DOMAIN_ATTRIBUTES = 0x3,
+ SCMI_PERF_DESCRIBE_LEVELS = 0x4,
+ SCMI_PERF_LIMITS_SET = 0x5,
+ SCMI_PERF_LIMITS_GET = 0x6,
+ SCMI_PERF_LEVEL_SET = 0x7,
+ SCMI_PERF_LEVEL_GET = 0x8
+};
+
+struct scmi_perf_in {
+ u32 domain_id;
+ u32 perf_level;
+};
+
+struct scmi_perf_out {
+ s32 status;
+};
#endif /* _SCMI_PROTOCOLS_H */
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 122987c..12b54c8 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -82,7 +82,6 @@
SUNXI_GPIO_L_START = 352,
SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
- SUNXI_GPIO_AXP0_START = 1024,
};
/* SUNXI GPIO number definitions */
@@ -99,8 +98,6 @@
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
-#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
-
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
#define SUNXI_GPIO_OUTPUT 1
@@ -185,11 +182,6 @@
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
-/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
-#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
-
struct sunxi_gpio_plat {
void *regs;
char bank_name[3];
diff --git a/include/test/video.h b/include/test/video.h
new file mode 100644
index 0000000..000fd70
--- /dev/null
+++ b/include/test/video.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc.
+ */
+
+#ifndef __TEST_VIDEO_H
+#define __TEST_VIDEO_H
+
+#include <stdbool.h>
+
+struct udevice;
+struct unit_test_state;
+
+/**
+ * video_compress_fb() - Compress the frame buffer and return its size
+ *
+ * We want to write tests which perform operations on the video console and
+ * check that the frame buffer ends up with the correct contents. But it is
+ * painful to store 'known good' images for comparison with the frame
+ * buffer. As an alternative, we can compress the frame buffer and check the
+ * size of the compressed data. This provides a pretty good level of
+ * certainty and the resulting tests need only check a single value.
+ *
+ * @uts: Test state
+ * @dev: Video device
+ * @use_copy: Use copy frame buffer if available
+ * Return: compressed size of the frame buffer, or -ve on error
+ */
+int video_compress_fb(struct unit_test_state *uts, struct udevice *dev,
+ bool use_copy);
+
+/**
+ * check_copy_frame_buffer() - Compare main frame buffer to copy
+ *
+ * If the copy frame buffer is enabled, this compares it to the main
+ * frame buffer. Normally they should have the same contents after a
+ * sync.
+ *
+ * @uts: Test state
+ * @dev: Video device
+ * Return: 0, or -ve on error
+ */
+int video_check_copy_fb(struct unit_test_state *uts, struct udevice *dev);
+
+#endif
diff --git a/include/uthread.h b/include/uthread.h
index 89fa552..11a19aa 100644
--- a/include/uthread.h
+++ b/include/uthread.h
@@ -51,7 +51,10 @@
};
/**
- * Internal state of a struct uthread_mutex
+ * enum uthread_mutex_state - internal state of a struct uthread_mutex
+ *
+ * @UTHREAD_MUTEX_UNLOCKED: mutex has no owner
+ * @UTHREAD_MUTEX_LOCKED: mutex has one owner
*/
enum uthread_mutex_state {
UTHREAD_MUTEX_UNLOCKED = 0,
@@ -59,7 +62,9 @@
};
/**
- * Uthread mutex
+ * struct uthread_mutex - a mutex object
+ *
+ * @state: the internal state of the mutex
*/
struct uthread_mutex {
enum uthread_mutex_state state;
diff --git a/include/video.h b/include/video.h
index a1f7fd7..9ea6b67 100644
--- a/include/video.h
+++ b/include/video.h
@@ -85,6 +85,11 @@
* @fb_size: Frame buffer size
* @copy_fb: Copy of the frame buffer to keep up to date; see struct
* video_uc_plat
+ * @damage: A bounding box of framebuffer regions updated since last sync
+ * @damage.xstart: X start position in pixels from the left
+ * @damage.ystart: Y start position in pixels from the top
+ * @damage.xend: X end position in pixels from the left
+ * @damage.xend: Y end position in pixels from the top
* @line_length: Length of each frame buffer line, in bytes. This can be
* set by the driver, but if not, the uclass will set it after
* probing
@@ -95,6 +100,7 @@
* @fg_col_idx: Foreground color code (bit 3 = bold, bit 0-2 = color)
* @bg_col_idx: Background color code (bit 3 = bold, bit 0-2 = color)
* @last_sync: Monotonic time of last video sync
+ * @white_on_black: Use a black background
*/
struct video_priv {
/* Things set up by the driver: */
@@ -113,6 +119,12 @@
void *fb;
int fb_size;
void *copy_fb;
+ struct {
+ int xstart;
+ int ystart;
+ int xend;
+ int yend;
+ } damage;
int line_length;
u32 colour_fg;
u32 colour_bg;
@@ -120,6 +132,7 @@
u8 fg_col_idx;
u8 bg_col_idx;
ulong last_sync;
+ bool white_on_black;
};
/**
@@ -236,7 +249,7 @@
/**
* video_fill_part() - Erase a region
*
- * Erase a rectangle of the display within the given bounds.
+ * Erase a rectangle on the display within the given bounds
*
* @dev: Device to update
* @xstart: X start position in pixels from the left
@@ -250,6 +263,23 @@
int yend, u32 colour);
/**
+ * video_draw_box() - Draw a box
+ *
+ * Draw a rectangle on the display within the given bounds
+ *
+ * @dev: Device to update
+ * @x0: X start position in pixels from the left
+ * @y0: Y start position in pixels from the top
+ * @x1: X end position in pixels from the left
+ * @y1: Y end position in pixels from the top
+ * @width: width in pixels
+ * @colour: Value to write
+ * Return: 0 if OK, -ENOSYS if the display depth is not supported
+ */
+int video_draw_box(struct udevice *dev, int x0, int y0, int x1, int y1,
+ int width, u32 colour);
+
+/**
* video_sync() - Sync a device's frame buffer with its hardware
*
* @vid: Device to sync
@@ -259,8 +289,9 @@
* @return: 0 on success, error code otherwise
*
* Some frame buffers are cached or have a secondary frame buffer. This
- * function syncs these up so that the current contents of the U-Boot frame
- * buffer are displayed to the user.
+ * function syncs the damaged parts of them up so that the current contents
+ * of the U-Boot frame buffer are displayed to the user. It clears the damage
+ * buffer.
*/
int video_sync(struct udevice *vid, bool force);
@@ -335,6 +366,16 @@
void video_set_default_colors(struct udevice *dev, bool invert);
/**
+ * video_set_white_on_black() - Change the setting for white-on-black
+ *
+ * This does nothing if the setting is already the same.
+ *
+ * @dev: video device
+ * @white_on_black: true to use white-on-black, false for black-on-white
+ */
+void video_set_white_on_black(struct udevice *dev, bool white_on_black);
+
+/**
* video_default_font_height() - Get the default font height
*
* @dev: video device
@@ -343,42 +384,29 @@
*/
int video_default_font_height(struct udevice *dev);
-#ifdef CONFIG_VIDEO_COPY
+#ifdef CONFIG_VIDEO_DAMAGE
/**
- * vidconsole_sync_copy() - Sync back to the copy framebuffer
- *
- * This ensures that the copy framebuffer has the same data as the framebuffer
- * for a particular region. It should be called after the framebuffer is updated
- *
- * @from and @to can be in either order. The region between them is synced.
+ * video_damage() - Notify the video subsystem about screen updates.
*
- * @dev: Vidconsole device being updated
- * @from: Start/end address within the framebuffer (->fb)
- * @to: Other address within the frame buffer
- * Return: 0 if OK, -EFAULT if the start address is before the start of the
- * frame buffer start
- */
-int video_sync_copy(struct udevice *dev, void *from, void *to);
-
-/**
- * video_sync_copy_all() - Sync the entire framebuffer to the copy
+ * @vid: Device to sync
+ * @x: Upper left X coordinate of the damaged rectangle
+ * @y: Upper left Y coordinate of the damaged rectangle
+ * @width: Width of the damaged rectangle
+ * @height: Height of the damaged rectangle
*
- * @dev: Vidconsole device being updated
- * Return: 0 (always)
+ * Some frame buffers are cached or have a secondary frame buffer. This
+ * function notifies the video subsystem about rectangles that were updated
+ * within the frame buffer. They may only get written to the screen on the
+ * next call to video_sync().
*/
-int video_sync_copy_all(struct udevice *dev);
+void video_damage(struct udevice *vid, int x, int y, int width, int height);
#else
-static inline int video_sync_copy(struct udevice *dev, void *from, void *to)
-{
- return 0;
-}
-
-static inline int video_sync_copy_all(struct udevice *dev)
+static inline void video_damage(struct udevice *vid, int x, int y, int width,
+ int height)
{
- return 0;
+ return;
}
-
-#endif
+#endif /* CONFIG_VIDEO_DAMAGE */
/**
* video_is_active() - Test if one video device it active
diff --git a/include/video_console.h b/include/video_console.h
index 723d231..8f3f58f 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -6,6 +6,7 @@
#ifndef __video_console_h
#define __video_console_h
+#include <alist.h>
#include <video.h>
struct abuf;
@@ -52,6 +53,7 @@
* @row_saved: Saved Y position in pixels (0=top)
* @escape_buf: Buffer to accumulate escape sequence
* @utf8_buf: Buffer to accumulate UTF-8 byte sequence
+ * @quiet: Suppress all output from stdio
*/
struct vidconsole_priv {
struct stdio_dev sdev;
@@ -76,6 +78,7 @@
int col_saved;
char escape_buf[32];
char utf8_buf[5];
+ bool quiet;
};
/**
@@ -120,6 +123,19 @@
};
/**
+ * vidconsole_mline - Holds information about a line of measured text
+ *
+ * @bbox: Bounding box of the line, assuming it starts at 0,0
+ * @start: String index of the first character in the line
+ * @len: Number of characters in the line
+ */
+struct vidconsole_mline {
+ struct vidconsole_bbox bbox;
+ int start;
+ int len;
+};
+
+/**
* struct vidconsole_ops - Video console operations
*
* These operations work on either an absolute console position (measured
@@ -228,18 +244,26 @@
int (*select_font)(struct udevice *dev, const char *name, uint size);
/**
- * measure() - Measure the bounds of some text
+ * measure() - Measure the bounding box of some text
*
- * @dev: Device to adjust
+ * The text can include newlines
+ *
+ * @dev: Console device to use
* @name: Font name to use (NULL to use default)
* @size: Font size to use (0 to use default)
* @text: Text to measure
+ * @limit: Width limit for each line, or -1 if none
* @bbox: Returns bounding box of text, assuming it is positioned
* at 0,0
+ * @lines: If non-NULL, this must be an alist of
+ * struct vidconsole_mline inited by caller. A separate
+ * record is added for each line of text
+ *
* Returns: 0 on success, -ENOENT if no such font
*/
int (*measure)(struct udevice *dev, const char *name, uint size,
- const char *text, struct vidconsole_bbox *bbox);
+ const char *text, int limit,
+ struct vidconsole_bbox *bbox, struct alist *lines);
/**
* nominal() - Measure the expected width of a line of text
@@ -320,19 +344,27 @@
*/
int vidconsole_select_font(struct udevice *dev, const char *name, uint size);
-/*
- * vidconsole_measure() - Measuring the bounding box of some text
+/**
+ * vidconsole_measure() - Measure the bounding box of some text
*
- * @dev: Console device to use
- * @name: Font name, NULL for default
- * @size: Font size, ignored if @name is NULL
- * @text: Text to measure
- * @bbox: Returns nounding box of text
- * Returns: 0 if OK, -ve on error
+ * The text can include newlines
+ *
+ * @dev: Device to adjust
+ * @name: Font name to use (NULL to use default)
+ * @size: Font size to use (0 to use default)
+ * @text: Text to measure
+ * @limit: Width limit for each line, or -1 if none
+ * @bbox: Returns bounding box of text, assuming it is positioned
+ * at 0,0
+ * @lines: If non-NULL, this must be an alist of
+ * struct vidconsole_mline inited by caller. The list is emptied
+ * and then a separate record is added for each line of text
+ *
+ * Returns: 0 on success, -ENOENT if no such font
*/
int vidconsole_measure(struct udevice *dev, const char *name, uint size,
- const char *text, struct vidconsole_bbox *bbox);
-
+ const char *text, int limit,
+ struct vidconsole_bbox *bbox, struct alist *lines);
/**
* vidconsole_nominal() - Measure the expected width of a line of text
*
@@ -470,6 +502,23 @@
int vidconsole_put_char(struct udevice *dev, char ch);
/**
+ * vidconsole_put_stringn() - Output part of a string to the current console pos
+ *
+ * Outputs part of a string to the console and advances the cursor. This
+ * function handles wrapping to new lines and scrolling the console. Special
+ * characters are handled also: \n, \r, \b and \t.
+ *
+ * The device always starts with the cursor at position 0,0 (top left). It
+ * can be adjusted manually using vidconsole_position_cursor().
+ *
+ * @dev: Device to adjust
+ * @str: String to write
+ * @maxlen: Maximum chars to output, or -1 for all
+ * Return: 0 if OK, -ve on error
+ */
+int vidconsole_put_stringn(struct udevice *dev, const char *str, int maxlen);
+
+/**
* vidconsole_put_string() - Output a string to the current console position
*
* Outputs a string to the console and advances the cursor. This function
@@ -537,56 +586,12 @@
*/
int vidconsole_get_font_size(struct udevice *dev, const char **name, uint *sizep);
-#ifdef CONFIG_VIDEO_COPY
-/**
- * vidconsole_sync_copy() - Sync back to the copy framebuffer
- *
- * This ensures that the copy framebuffer has the same data as the framebuffer
- * for a particular region. It should be called after the framebuffer is updated
- *
- * @from and @to can be in either order. The region between them is synced.
- *
- * @dev: Vidconsole device being updated
- * @from: Start/end address within the framebuffer (->fb)
- * @to: Other address within the frame buffer
- * Return: 0 if OK, -EFAULT if the start address is before the start of the
- * frame buffer start
- */
-int vidconsole_sync_copy(struct udevice *dev, void *from, void *to);
-
/**
- * vidconsole_memmove() - Perform a memmove() within the frame buffer
+ * vidconsole_set_quiet() - Select whether the console should output stdio
*
- * This handles a memmove(), e.g. for scrolling. It also updates the copy
- * framebuffer.
- *
- * @dev: Vidconsole device being updated
- * @dst: Destination address within the framebuffer (->fb)
- * @src: Source address within the framebuffer (->fb)
- * @size: Number of bytes to transfer
- * Return: 0 if OK, -EFAULT if the start address is before the start of the
- * frame buffer start
+ * @dev: vidconsole device
+ * @quiet: true to suppress stdout/stderr output, false to enable it
*/
-int vidconsole_memmove(struct udevice *dev, void *dst, const void *src,
- int size);
-#else
-
-#include <string.h>
-
-static inline int vidconsole_sync_copy(struct udevice *dev, void *from,
- void *to)
-{
- return 0;
-}
-
-static inline int vidconsole_memmove(struct udevice *dev, void *dst,
- const void *src, int size)
-{
- memmove(dst, src, size);
-
- return 0;
-}
-
-#endif
+void vidconsole_set_quiet(struct udevice *dev, bool quiet);
#endif
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index ab50a69..cf050e5 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -37,7 +37,7 @@
obj-y += efi_dt_fixup.o
obj-y += efi_fdt.o
obj-y += efi_file.o
-obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o
+obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o efi_hii_config.o
obj-y += efi_image_loader.o
obj-y += efi_load_options.o
obj-y += efi_memory.o
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index d0f7da3..94ba7c5 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -215,12 +215,11 @@
* Return: status code
*/
static efi_status_t efi_binary_run_dp(void *image, size_t size, void *fdt,
- void *initrd, size_t initd_sz,
+ void *initrd, size_t initrd_sz,
struct efi_device_path *dp_dev,
struct efi_device_path *dp_img)
{
efi_status_t ret;
- struct efi_device_path *dp_initrd;
/* Initialize EFI drivers */
ret = efi_init_obj_list();
@@ -234,11 +233,7 @@
if (ret != EFI_SUCCESS)
return ret;
- dp_initrd = efi_dp_from_mem(EFI_LOADER_DATA, (uintptr_t)initrd, initd_sz);
- if (!dp_initrd)
- return EFI_OUT_OF_RESOURCES;
-
- ret = efi_initrd_register(dp_initrd);
+ ret = efi_install_initrd(initrd, initrd_sz);
if (ret != EFI_SUCCESS)
return ret;
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index f220daa..dbebb37 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -3195,7 +3195,7 @@
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;
efi_status_t ret;
- void *info;
+ struct efi_loaded_image *info;
efi_handle_t parent_image = current_image;
efi_status_t exit_status;
jmp_buf exit_jmp;
@@ -3213,7 +3213,7 @@
return EFI_EXIT(EFI_SECURITY_VIOLATION);
ret = EFI_CALL(efi_open_protocol(image_handle, &efi_guid_loaded_image,
- &info, NULL, NULL,
+ (void **)&info, NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
if (ret != EFI_SUCCESS)
return EFI_EXIT(EFI_INVALID_PARAMETER);
@@ -3266,7 +3266,8 @@
current_image = image_handle;
image_obj->header.type = EFI_OBJECT_TYPE_STARTED_IMAGE;
- EFI_PRINT("Jumping into 0x%p\n", image_obj->entry);
+ EFI_PRINT("Starting image loaded at 0x%p, entry point 0x%p\n",
+ info->image_base, image_obj->entry);
ret = EFI_CALL(image_obj->entry(image_handle, &systab));
/*
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index 4593975..3abb47d 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -26,6 +26,7 @@
* @ops: graphical output protocol interface
* @info: graphical output mode information
* @mode: graphical output mode
+ * @vdev: backing video device
* @bpix: bits per pixel
* @fb: frame buffer
*/
@@ -34,6 +35,7 @@
struct efi_gop ops;
struct efi_gop_mode_info info;
struct efi_gop_mode mode;
+ struct udevice *vdev;
/* Fields we only have access to during init */
u32 bpix;
void *fb;
@@ -122,6 +124,7 @@
u32 *fb32 = gopobj->fb;
u16 *fb16 = gopobj->fb;
struct efi_gop_pixel *buffer = __builtin_assume_aligned(bufferp, 4);
+ bool blt_to_video = (operation != EFI_BLT_VIDEO_TO_BLT_BUFFER);
if (delta) {
/* Check for 4 byte alignment */
@@ -245,6 +248,9 @@
dlineoff += dwidth;
}
+ if (blt_to_video)
+ video_damage(gopobj->vdev, dx, dy, width, height);
+
return EFI_SUCCESS;
}
@@ -551,6 +557,7 @@
gopobj->info.pixels_per_scanline = col;
gopobj->bpix = bpix;
gopobj->fb = map_sysmem(fb_base, fb_size);
+ gopobj->vdev = vdev;
return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 3936139..19fb5d0 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -623,6 +623,35 @@
}
/**
+ * efi_install_initrd() - install initrd
+ *
+ * Install the initrd located at @initrd using the EFI_LOAD_FILE2
+ * protocol.
+ *
+ * @initrd: address of initrd or NULL if none is provided
+ * @initrd_sz: size of initrd
+ * Return: status code
+ */
+efi_status_t efi_install_initrd(void *initrd, size_t initd_sz)
+{
+ efi_status_t ret;
+ struct efi_device_path *dp_initrd;
+
+ if (!initrd)
+ return EFI_SUCCESS;
+
+ dp_initrd = efi_dp_from_mem(EFI_LOADER_DATA, (uintptr_t)initrd, initd_sz);
+ if (!dp_initrd)
+ return EFI_OUT_OF_RESOURCES;
+
+ ret = efi_initrd_register(dp_initrd);
+ if (ret != EFI_SUCCESS)
+ efi_free_pool(dp_initrd);
+
+ return ret;
+}
+
+/**
* do_bootefi_exec() - execute EFI binary
*
* The image indicated by @handle is started. When it returns the allocated
diff --git a/lib/efi_loader/efi_hii_config.c b/lib/efi_loader/efi_hii_config.c
index 37d8c66..521481a 100644
--- a/lib/efi_loader/efi_hii_config.c
+++ b/lib/efi_loader/efi_hii_config.c
@@ -4,10 +4,6 @@
*
* Copyright (c) 2017 Leif Lindholm
* Copyright (c) 2018 AKASHI Takahiro, Linaro Limited
- *
- * As this is still a non-working stub and the protocol is neither required
- * by the EFI shell nor by the UEFI SCT this module has been removed from
- * the Makefile.
*/
#define LOG_CATEGORY LOGC_EFI
diff --git a/lib/efi_loader/efi_root_node.c b/lib/efi_loader/efi_root_node.c
index 74225ed..e5246f6 100644
--- a/lib/efi_loader/efi_root_node.c
+++ b/lib/efi_loader/efi_root_node.c
@@ -80,6 +80,9 @@
/* HII database protocol */
&efi_guid_hii_database_protocol,
&efi_hii_database,
+ /* EFI HII Configuration Routing Protocol */
+ &efi_guid_hii_config_routing_protocol,
+ &efi_hii_config_routing,
#endif
NULL);
efi_root->type = EFI_OBJECT_TYPE_U_BOOT_FIRMWARE;
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index f09c992..c38738b 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1708,7 +1708,7 @@
gd->fdt_src = FDTSRC_BLOBLIST;
log_debug("Devicetree is in bloblist at %p\n",
gd->fdt_blob);
- ret = 0;
+ goto setup_fdt;
} else {
log_debug("No FDT found in bloblist\n");
ret = -ENOENT;
@@ -1752,6 +1752,7 @@
}
}
+setup_fdt:
if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
setup_multi_dtb_fit();
diff --git a/lib/gunzip.c b/lib/gunzip.c
index 5200771..a05dcde 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -299,7 +299,7 @@
if (stoponerr == 1 && r != Z_STREAM_END &&
(s.avail_in == 0 || s.avail_out == 0 || r != Z_BUF_ERROR)) {
printf("Error: inflate() returned %d\n", r);
- err = -1;
+ err = r;
break;
}
} while (r == Z_BUF_ERROR);
diff --git a/lib/of_live.c b/lib/of_live.c
index 90b9459..c162061 100644
--- a/lib/of_live.c
+++ b/lib/of_live.c
@@ -11,6 +11,7 @@
#define LOG_CATEGORY LOGC_DT
#include <abuf.h>
+#include <event.h>
#include <log.h>
#include <linux/libfdt.h>
#include <of_live.h>
@@ -321,6 +322,7 @@
int of_live_build(const void *fdt_blob, struct device_node **rootp)
{
int ret;
+ union event_data evt;
debug("%s: start\n", __func__);
ret = unflatten_device_tree(fdt_blob, rootp);
@@ -335,6 +337,15 @@
}
debug("%s: stop\n", __func__);
+ if (CONFIG_IS_ENABLED(EVENT)) {
+ evt.of_live_built.root = *rootp;
+ ret = event_notify(EVT_OF_LIVE_BUILT, &evt, sizeof(evt));
+ if (ret) {
+ log_debug("Failed to notify livetree build event: err=%d\n", ret);
+ return ret;
+ }
+ }
+
return ret;
}
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 079add4..ba30652 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -94,6 +94,7 @@
%_defconfig: $(obj)/conf
$(Q)$(CPP) -nostdinc -P -I $(srctree) -undef -x assembler-with-cpp $(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
+ $(Q)sed -i -e 's/^[[:space:]]//' generated_defconfig
$(Q)$< $(silent) --defconfig=generated_defconfig $(Kconfig)
# Added for U-Boot (backward compatibility)
diff --git a/scripts/make_pip.sh b/scripts/make_pip.sh
index d2639ff..33ad51a 100755
--- a/scripts/make_pip.sh
+++ b/scripts/make_pip.sh
@@ -106,6 +106,10 @@
mkdir ${dir}/tests
cd ${dir}
+# Use virtual environment
+python3 -m venv .venv
+source .venv/bin/activate
+
# Make sure the tools are up to date
python3 -m pip install --upgrade build
python3 -m pip install --upgrade twine
@@ -122,6 +126,8 @@
echo "Completed upload of ${tool}"
fi
+# Finish using virtual environment
+deactivate
rm -rf "${dir}"
echo -e "done\n\n"
diff --git a/test/dm/video.c b/test/dm/video.c
index e347c14..ecf7460 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -17,8 +17,10 @@
#include <asm/sdl.h>
#include <dm/test.h>
#include <dm/uclass-internal.h>
+#include <test/lib.h>
#include <test/test.h>
#include <test/ut.h>
+#include <test/video.h>
/*
* These tests use the standard sandbox frame buffer, the resolution of which
@@ -44,53 +46,46 @@
}
DM_TEST(dm_test_video_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
-/**
- * compress_frame_buffer() - Compress the frame buffer and return its size
- *
- * We want to write tests which perform operations on the video console and
- * check that the frame buffer ends up with the correct contents. But it is
- * painful to store 'known good' images for comparison with the frame
- * buffer. As an alternative, we can compress the frame buffer and check the
- * size of the compressed data. This provides a pretty good level of
- * certainty and the resulting tests need only check a single value.
- *
- * If the copy framebuffer is enabled, this compares it to the main framebuffer
- * too.
- *
- * @uts: Test state
- * @dev: Video device
- * Return: compressed size of the frame buffer, or -ve on error
- */
-static int compress_frame_buffer(struct unit_test_state *uts,
- struct udevice *dev)
+int video_compress_fb(struct unit_test_state *uts, struct udevice *dev,
+ bool use_copy)
{
struct video_priv *priv = dev_get_uclass_priv(dev);
- struct video_priv *uc_priv = dev_get_uclass_priv(dev);
uint destlen;
void *dest;
int ret;
+ if (!IS_ENABLED(CONFIG_VIDEO_COPY))
+ use_copy = false;
+
destlen = priv->fb_size;
dest = malloc(priv->fb_size);
if (!dest)
return -ENOMEM;
ret = BZ2_bzBuffToBuffCompress(dest, &destlen,
- priv->fb, priv->fb_size,
+ use_copy ? priv->copy_fb : priv->fb,
+ priv->fb_size,
3, 0, 0);
free(dest);
if (ret)
return ret;
- /* Check here that the copy frame buffer is working correctly */
- if (IS_ENABLED(CONFIG_VIDEO_COPY)) {
- ut_assertf(!memcmp(uc_priv->fb, uc_priv->copy_fb,
- uc_priv->fb_size),
- "Copy framebuffer does not match fb");
- }
-
return destlen;
}
+int video_check_copy_fb(struct unit_test_state *uts, struct udevice *dev)
+{
+ struct video_priv *priv = dev_get_uclass_priv(dev);
+
+ if (!IS_ENABLED(CONFIG_VIDEO_COPY))
+ return 0;
+
+ video_sync(dev, false);
+ ut_assertf(!memcmp(priv->fb, priv->copy_fb, priv->fb_size),
+ "Copy framebuffer does not match fb");
+
+ return 0;
+}
+
/*
* Call this function at any point to halt and show the current display. Be
* sure to run the test with the -l flag.
@@ -153,25 +148,31 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "8x16", 0));
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_putc_xy(con, 0, 0, 'a');
- ut_asserteq(79, compress_frame_buffer(uts, dev));
+ ut_asserteq(79, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
vidconsole_putc_xy(con, 0, 0, ' ');
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(273, compress_frame_buffer(uts, dev));
+ ut_asserteq(273, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
vidconsole_set_row(con, 0, WHITE);
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(273, compress_frame_buffer(uts, dev));
+ ut_asserteq(273, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -189,25 +190,31 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "12x22", 0));
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_putc_xy(con, 0, 0, 'a');
- ut_asserteq(89, compress_frame_buffer(uts, dev));
+ ut_asserteq(89, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
vidconsole_putc_xy(con, 0, 0, ' ');
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(363, compress_frame_buffer(uts, dev));
+ ut_asserteq(363, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
vidconsole_set_row(con, 0, WHITE);
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
for (i = 0; i < 20; i++)
vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i);
- ut_asserteq(363, compress_frame_buffer(uts, dev));
+ ut_asserteq(363, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -224,7 +231,8 @@
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "8x16", 0));
vidconsole_put_string(con, test_string);
- ut_asserteq(466, compress_frame_buffer(uts, dev));
+ ut_asserteq(466, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -245,20 +253,24 @@
/* reference clear: */
video_clear(con->parent);
video_sync(con->parent, false);
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
/* test clear escape sequence: [2J */
vidconsole_put_string(con, "A\tB\tC"ANSI_ESC"[2J");
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
/* test set-cursor: [%d;%df */
vidconsole_put_string(con, "abc"ANSI_ESC"[2;2fab"ANSI_ESC"[4;4fcd");
- ut_asserteq(143, compress_frame_buffer(uts, dev));
+ ut_asserteq(143, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
/* test colors (30-37 fg color, 40-47 bg color) */
vidconsole_put_string(con, ANSI_ESC"[30;41mfoo"); /* black on red */
vidconsole_put_string(con, ANSI_ESC"[33;44mbar"); /* yellow on blue */
- ut_asserteq(272, compress_frame_buffer(uts, dev));
+ ut_asserteq(272, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -290,24 +302,28 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
ut_assertok(vidconsole_select_font(con, "8x16", 0));
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
/* Check display wrap */
for (i = 0; i < 120; i++)
vidconsole_put_char(con, 'A' + i % 50);
- ut_asserteq(wrap_size, compress_frame_buffer(uts, dev));
+ ut_asserteq(wrap_size, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
/* Check display scrolling */
for (i = 0; i < SCROLL_LINES; i++) {
vidconsole_put_char(con, 'A' + i % 50);
vidconsole_put_char(con, '\n');
}
- ut_asserteq(scroll_size, compress_frame_buffer(uts, dev));
+ ut_asserteq(scroll_size, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
/* If we scroll enough, the screen becomes blank again */
for (i = 0; i < SCROLL_LINES; i++)
vidconsole_put_char(con, '\n');
- ut_asserteq(46, compress_frame_buffer(uts, dev));
+ ut_asserteq(46, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -381,7 +397,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1368, compress_frame_buffer(uts, dev));
+ ut_asserteq(1368, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -400,7 +417,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1247, compress_frame_buffer(uts, dev));
+ ut_asserteq(1247, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -423,7 +441,8 @@
&src_len));
ut_assertok(video_bmp_display(dev, dst, 0, 0, false));
- ut_asserteq(3700, compress_frame_buffer(uts, dev));
+ ut_asserteq(3700, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -446,7 +465,8 @@
&src_len));
ut_assertok(video_bmp_display(dev, dst, 0, 0, false));
- ut_asserteq(3656, compress_frame_buffer(uts, dev));
+ ut_asserteq(3656, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -469,7 +489,8 @@
&src_len));
ut_assertok(video_bmp_display(dev, dst, 0, 0, false));
- ut_asserteq(6827, compress_frame_buffer(uts, dev));
+ ut_asserteq(6827, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -487,7 +508,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(2024, compress_frame_buffer(uts, dev));
+ ut_asserteq(2024, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -503,7 +525,8 @@
ut_assertok(read_file(uts, "tools/logos/denx-comp.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1368, compress_frame_buffer(uts, dev));
+ ut_asserteq(1368, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -522,7 +545,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(2024, compress_frame_buffer(uts, dev));
+ ut_asserteq(2024, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -541,7 +565,8 @@
ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
- ut_asserteq(1247, compress_frame_buffer(uts, dev));
+ ut_asserteq(1247, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -556,7 +581,9 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_put_string(con, test_string);
- ut_asserteq(12174, compress_frame_buffer(uts, dev));
+ vidconsole_put_stringn(con, test_string, 30);
+ ut_asserteq(13184, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -577,7 +604,8 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_put_string(con, test_string);
- ut_asserteq(34287, compress_frame_buffer(uts, dev));
+ ut_asserteq(34287, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
@@ -598,8 +626,300 @@
ut_assertok(video_get_nologo(uts, &dev));
ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
vidconsole_put_string(con, test_string);
- ut_asserteq(29471, compress_frame_buffer(uts, dev));
+ ut_asserteq(29471, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
return 0;
}
DM_TEST(dm_test_video_truetype_bs, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
+/* Test partial rendering onto hardware frame buffer */
+static int dm_test_video_copy(struct unit_test_state *uts)
+{
+ struct sandbox_sdl_plat *plat;
+ struct video_uc_plat *uc_plat;
+ struct udevice *dev, *con;
+ struct video_priv *priv;
+ const char *test_string = "\n\tCriticism may not be agreeable, but it is necessary.\t";
+ ulong addr;
+
+ if (!IS_ENABLED(CONFIG_VIDEO_COPY))
+ return -EAGAIN;
+
+ ut_assertok(uclass_find_first_device(UCLASS_VIDEO, &dev));
+ ut_assertnonnull(dev);
+ uc_plat = dev_get_uclass_plat(dev);
+ uc_plat->hide_logo = true;
+ plat = dev_get_plat(dev);
+ plat->font_size = 32;
+ ut_assert(!device_active(dev));
+ ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev));
+ ut_assertnonnull(dev);
+ priv = dev_get_uclass_priv(dev);
+
+ ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr));
+ ut_assertok(video_bmp_display(dev, addr, 0, 0, false));
+
+ ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+ vidconsole_put_string(con, "\n\n\n\n\n");
+ vidconsole_put_string(con, test_string);
+ vidconsole_put_string(con, test_string);
+
+ ut_asserteq(6678, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
+
+ /*
+ * Secretly clear the hardware frame buffer, but in a different
+ * color (black) to see which parts will be overwritten.
+ */
+ memset(priv->copy_fb, 0, priv->fb_size);
+
+ /*
+ * We should have the full content on the main buffer, but only
+ * 'damage' should have been copied to the copy buffer. This consists
+ * of a while rectangle with the Denx logo and four lines of text. The
+ * rest of the display is black.
+ *
+ * An easy way to try this is by changing video_sync() to call
+ * sandbox_sdl_sync(priv->copy_fb) instead of priv->fb then running the
+ * unit test:
+ *
+ * ./u-boot -Tl
+ * ut dm dm_test_video_copy
+ */
+ vidconsole_put_string(con, test_string);
+ vidconsole_put_string(con, test_string);
+ video_sync(dev, true);
+ ut_asserteq(7589, video_compress_fb(uts, dev, false));
+ ut_asserteq(7704, video_compress_fb(uts, dev, true));
+
+ return 0;
+}
+DM_TEST(dm_test_video_copy, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
+/* Test video damage tracking */
+static int dm_test_video_damage(struct unit_test_state *uts)
+{
+ struct sandbox_sdl_plat *plat;
+ struct udevice *dev, *con;
+ struct video_priv *priv;
+ const char *test_string_1 = "Criticism may not be agreeable, ";
+ const char *test_string_2 = "but it is necessary.";
+ const char *test_string_3 = "It fulfils the same function as pain in the human body.";
+
+ if (!IS_ENABLED(CONFIG_VIDEO_DAMAGE))
+ return -EAGAIN;
+
+ ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev));
+ ut_assert(!device_active(dev));
+ plat = dev_get_plat(dev);
+ plat->font_size = 32;
+
+ ut_assertok(video_get_nologo(uts, &dev));
+ ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+ priv = dev_get_uclass_priv(dev);
+
+ vidconsole_position_cursor(con, 14, 10);
+ vidconsole_put_string(con, test_string_2);
+ ut_asserteq(449, priv->damage.xstart);
+ ut_asserteq(325, priv->damage.ystart);
+ ut_asserteq(661, priv->damage.xend);
+ ut_asserteq(350, priv->damage.yend);
+
+ vidconsole_position_cursor(con, 7, 5);
+ vidconsole_put_string(con, test_string_1);
+ ut_asserteq(225, priv->damage.xstart);
+ ut_asserteq(164, priv->damage.ystart);
+ ut_asserteq(661, priv->damage.xend);
+ ut_asserteq(350, priv->damage.yend);
+
+ vidconsole_position_cursor(con, 21, 15);
+ vidconsole_put_string(con, test_string_3);
+ ut_asserteq(225, priv->damage.xstart);
+ ut_asserteq(164, priv->damage.ystart);
+ ut_asserteq(1280, priv->damage.xend);
+ ut_asserteq(510, priv->damage.yend);
+
+ video_sync(dev, true);
+ ut_asserteq(priv->xsize, priv->damage.xstart);
+ ut_asserteq(priv->ysize, priv->damage.ystart);
+ ut_asserteq(0, priv->damage.xend);
+ ut_asserteq(0, priv->damage.yend);
+
+ ut_asserteq(7339, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
+
+ return 0;
+}
+DM_TEST(dm_test_video_damage, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+
+/* Test font measurement */
+static int dm_test_font_measure(struct unit_test_state *uts)
+{
+ const char *test_string = "There is always much\nto be said for not "
+ "attempting more than you can do and for making a certainty of "
+ "what you try. But this principle, like others in life and "
+ "war, has its exceptions.";
+ const struct vidconsole_mline *line;
+ struct vidconsole_bbox bbox;
+ struct video_priv *priv;
+ struct udevice *dev, *con;
+ const int limit = 0x320;
+ struct alist lines;
+ int nl;
+
+ ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev));
+ priv = dev_get_uclass_priv(dev);
+ ut_asserteq(1366, priv->xsize);
+ ut_asserteq(768, priv->ysize);
+
+ /* this is using the Nimbus font with size of 18 pixels */
+ ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con));
+ vidconsole_position_cursor(con, 0, 0);
+ alist_init_struct(&lines, struct vidconsole_mline);
+ ut_assertok(vidconsole_measure(con, NULL, 0, test_string, -1, &bbox,
+ &lines));
+ ut_asserteq(0, bbox.x0);
+ ut_asserteq(0, bbox.y0);
+ ut_asserteq(0x3ea, bbox.x1);
+ ut_asserteq(0x24, bbox.y1);
+ ut_asserteq(2, lines.count);
+
+ nl = strchr(test_string, '\n') - test_string;
+
+ line = alist_get(&lines, 0, struct vidconsole_mline);
+ ut_assertnonnull(line);
+ ut_asserteq(0, line->bbox.x0);
+ ut_asserteq(0, line->bbox.y0);
+ ut_asserteq(0x8c, line->bbox.x1);
+ ut_asserteq(0x12, line->bbox.y1);
+ ut_asserteq(0, line->start);
+ ut_asserteq(20, line->len);
+ ut_asserteq(nl, line->len);
+
+ line++;
+ ut_asserteq(0x0, line->bbox.x0);
+ ut_asserteq(0x12, line->bbox.y0);
+ ut_asserteq(0x3ea, line->bbox.x1);
+ ut_asserteq(0x24, line->bbox.y1);
+ ut_asserteq(21, line->start);
+ ut_asserteq(nl + 1, line->start);
+ ut_asserteq(163, line->len);
+ ut_asserteq(strlen(test_string + nl + 1), line->len);
+
+ /* now use a limit on the width */
+ ut_assertok(vidconsole_measure(con, NULL, 0, test_string, limit, &bbox,
+ &lines));
+ ut_asserteq(0, bbox.x0);
+ ut_asserteq(0, bbox.y0);
+ ut_asserteq(0x31e, bbox.x1);
+ ut_asserteq(0x36, bbox.y1);
+ ut_asserteq(3, lines.count);
+
+ nl = strchr(test_string, '\n') - test_string;
+
+ line = alist_get(&lines, 0, struct vidconsole_mline);
+ ut_assertnonnull(line);
+ ut_asserteq(0, line->bbox.x0);
+ ut_asserteq(0, line->bbox.y0);
+ ut_asserteq(0x8c, line->bbox.x1);
+ ut_asserteq(0x12, line->bbox.y1);
+ ut_asserteq(0, line->start);
+ ut_asserteq(20, line->len);
+ ut_asserteq(nl, line->len);
+ printf("line0 '%.*s'\n", line->len, test_string + line->start);
+ ut_asserteq_strn("There is always much",
+ test_string + line->start);
+
+ line++;
+ ut_asserteq(0x0, line->bbox.x0);
+ ut_asserteq(0x12, line->bbox.y0);
+ ut_asserteq(0x31e, line->bbox.x1);
+ ut_asserteq(0x24, line->bbox.y1);
+ ut_asserteq(21, line->start);
+ ut_asserteq(nl + 1, line->start);
+ ut_asserteq(129, line->len);
+ printf("line1 '%.*s'\n", line->len, test_string + line->start);
+ ut_asserteq_strn("to be said for not attempting more than you can do "
+ "and for making a certainty of what you try. But this "
+ "principle, like others in",
+ test_string + line->start);
+
+ line++;
+ ut_asserteq(0x0, line->bbox.x0);
+ ut_asserteq(0x24, line->bbox.y0);
+ ut_asserteq(0xc8, line->bbox.x1);
+ ut_asserteq(0x36, line->bbox.y1);
+ ut_asserteq(21 + 130, line->start);
+ ut_asserteq(33, line->len);
+ printf("line2 '%.*s'\n", line->len, test_string + line->start);
+ ut_asserteq_strn("life and war, has its exceptions.",
+ test_string + line->start);
+
+ /*
+ * all characters should be accounted for, except the newline and the
+ * space which is consumed in the wordwrap
+ */
+ ut_asserteq(strlen(test_string) - 2,
+ line[-2].len + line[-1].len + line->len);
+
+ return 0;
+}
+DM_TEST(dm_test_font_measure, UTF_SCAN_FDT);
+
+/* Test silencing the video console */
+static int dm_test_video_silence(struct unit_test_state *uts)
+{
+ struct udevice *dev, *con;
+ struct stdio_dev *sdev;
+
+ ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev));
+
+ /*
+ * use the old console device from before when dm_test_pre_run() was
+ * called, since that is what is in stdio / console
+ */
+ sdev = stdio_get_by_name("vidconsole");
+ ut_assertnonnull(sdev);
+ con = sdev->priv;
+ ut_assertok(vidconsole_clear_and_reset(con));
+ ut_unsilence_console(uts);
+
+ printf("message 1: console\n");
+ vidconsole_put_string(con, "message 1: video\n");
+
+ vidconsole_set_quiet(con, true);
+ printf("second message: console\n");
+ vidconsole_put_string(con, "second message: video\n");
+
+ vidconsole_set_quiet(con, false);
+ printf("final message: console\n");
+ vidconsole_put_string(con, "final message: video\n");
+
+ ut_asserteq(3892, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
+
+ return 0;
+}
+DM_TEST(dm_test_video_silence, UTF_SCAN_FDT);
+
+/* test drawing a box */
+static int dm_test_video_box(struct unit_test_state *uts)
+{
+ struct video_priv *priv;
+ struct udevice *dev;
+
+ ut_assertok(video_get_nologo(uts, &dev));
+ priv = dev_get_uclass_priv(dev);
+ video_draw_box(dev, 100, 100, 200, 200, 3,
+ video_index_to_colour(priv, VID_LIGHT_BLUE));
+ video_draw_box(dev, 300, 100, 400, 200, 1,
+ video_index_to_colour(priv, VID_MAGENTA));
+ video_draw_box(dev, 500, 100, 600, 200, 20,
+ video_index_to_colour(priv, VID_LIGHT_RED));
+ ut_asserteq(133, video_compress_fb(uts, dev, false));
+ ut_assertok(video_check_copy_fb(uts, dev));
+
+ return 0;
+}
+DM_TEST(dm_test_video_box, UTF_SCAN_FDT);
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 780e981..4f05aa0 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1663,6 +1663,16 @@
+.. _etype_nxp_header_ddrfw:
+
+Entry: nxp-header-ddrfw: add a header to DDR PHY firmware images
+----------------------------------------------------------------
+
+This entry is used to combine DDR PHY firmware images and their byte counts
+together. See imx95_evk.rst for how to get DDR PHY Firmware Images.
+
+
+
.. _etype_opensbi:
Entry: opensbi: RISC-V OpenSBI fw_dynamic blob
diff --git a/tools/binman/etype/nxp_header_ddrfw.py b/tools/binman/etype/nxp_header_ddrfw.py
new file mode 100644
index 0000000..655699e
--- /dev/null
+++ b/tools/binman/etype/nxp_header_ddrfw.py
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2025 NXP
+
+from binman.etype.section import Entry_section
+
+class Entry_nxp_header_ddrfw(Entry_section):
+ """Add a header to DDR PHY firmware images
+
+ This entry is used for i.MX95 to combine DDR PHY firmware images and their
+ byte counts together.
+
+ See imx95_evk.rst for how to get DDR PHY Firmware Images.
+ """
+
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node)
+
+ def BuildSectionData(self, required):
+ section_data = bytearray()
+ header_data = bytearray()
+
+ for entry in self._entries.values():
+ entry_data = entry.GetData(required)
+
+ section_data += entry_data
+ header_data += entry.contents_size.to_bytes(4, 'little')
+
+ return header_data + section_data
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 92df2a0..fa17490 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -104,6 +104,8 @@
PRE_LOAD_HDR_SIZE = 0x00001000.to_bytes(4, 'big')
TI_BOARD_CONFIG_DATA = b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'
TI_UNSECURE_DATA = b'unsecuredata'
+IMX_LPDDR_IMEM_DATA = b'qwertyuiop1234567890'
+IMX_LPDDR_DMEM_DATA = b'asdfghjklzxcvbnm'
# Subdirectory of the input dir to use to put test FDTs
TEST_FDT_SUBDIR = 'fdts'
@@ -202,6 +204,8 @@
TestFunctional._MakeInputFile('fsp_m.bin', FSP_M_DATA)
TestFunctional._MakeInputFile('fsp_s.bin', FSP_S_DATA)
TestFunctional._MakeInputFile('fsp_t.bin', FSP_T_DATA)
+ TestFunctional._MakeInputFile('lpddr5_imem.bin', IMX_LPDDR_IMEM_DATA)
+ TestFunctional._MakeInputFile('lpddr5_dmem.bin', IMX_LPDDR_DMEM_DATA)
cls._elf_testdir = os.path.join(cls._indir, 'elftest')
elf_test.BuildElfTestFiles(cls._elf_testdir)
@@ -7848,6 +7852,13 @@
"""Test that binman can produce an iMX8 image"""
self._DoTestFile('339_nxp_imx8.dts')
+ def testNxpHeaderDdrfw(self):
+ """Test that binman can add a header to DDR PHY firmware images"""
+ data = self._DoReadFile('346_nxp_ddrfw_imx95.dts')
+ self.assertEqual(len(IMX_LPDDR_IMEM_DATA).to_bytes(4, 'little') +
+ len(IMX_LPDDR_DMEM_DATA).to_bytes(4, 'little') +
+ IMX_LPDDR_IMEM_DATA + IMX_LPDDR_DMEM_DATA, data)
+
def testFitSignSimple(self):
"""Test that image with FIT and signature nodes can be signed"""
if not elf.ELF_TOOLS:
diff --git a/tools/binman/test/346_nxp_ddrfw_imx95.dts b/tools/binman/test/346_nxp_ddrfw_imx95.dts
new file mode 100644
index 0000000..889f6f2
--- /dev/null
+++ b/tools/binman/test/346_nxp_ddrfw_imx95.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ imx-lpddr {
+ type = "nxp-header-ddrfw";
+
+ imx-lpddr-imem {
+ filename = "lpddr5_imem.bin";
+ type = "blob-ext";
+ };
+
+ imx-lpddr-dmem {
+ filename = "lpddr5_dmem.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+};
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index c5feb74..e31e6c7 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -987,7 +987,7 @@
diff = self.call_make_environment(tchn, full_path=True)[0]
self.assertEqual({b'LC_ALL': b'C'}, diff)
- # Test that virtualenv is handled correctly
+ # Test that Python sandbox is handled correctly
tchn.override_toolchain = False
sys.prefix = '/some/venv'
env = dict(os.environb)
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index f4c832b..5e5bb4b 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -217,7 +217,7 @@
elif self.cross:
env[b'CROSS_COMPILE'] = tools.to_bytes(wrapper + self.cross)
- # Detect a Python virtualenv and avoid defeating it
+ # Detect a Python sandbox and avoid defeating it
if sys.prefix != sys.base_prefix:
paths = env[b'PATH'].split(b':')
new_paths = []
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index a0fd174..1d7d2a1 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -90,6 +90,7 @@
help2man \
iasl \
imagemagick \
+ inetutils-telnet \
iputils-ping \
libconfuse-dev \
libgit2-dev \
@@ -124,7 +125,7 @@
python3-dev \
python3-pip \
python3-sphinx \
- python3-virtualenv \
+ python3-venv \
rpm2cpio \
sbsigntool \
socat \
@@ -136,7 +137,6 @@
texinfo \
util-linux \
uuid-dev \
- virtualenv \
vboot-kernel-utils \
vboot-utils \
xilinx-bootgen \
@@ -233,10 +233,18 @@
RUN git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git /tmp/tf-a && \
cd /tmp/tf-a/ && \
git checkout v2.12.0 && \
- cd tools/fiptool && \
- make -j$(nproc) && \
- mkdir -p /usr/local/bin && \
- cp fiptool /usr/local/bin && \
+ make CROSS_COMPILE=/opt/gcc-${TCVER}-nolibc/aarch64-linux/bin/aarch64-linux- \
+ PLAT=fvp BL33=/dev/null -j$(nproc) all fip && \
+ mkdir -p /usr/local/bin /opt/tf-a/vexpress_fvp && \
+ cp tools/fiptool/fiptool /usr/local/bin && \
+ cp build/fvp/release/fip.bin build/fvp/release/bl1.bin \
+ /opt/tf-a/vexpress_fvp/ && \
+ rm -rf build/fvp && \
+ make CROSS_COMPILE=/opt/gcc-${TCVER}-nolibc/aarch64-linux/bin/aarch64-linux- \
+ PLAT=fvp BL33=/dev/null TRANSFER_LIST=1 -j$(nproc) all fip && \
+ mkdir -p /opt/tf-a/vexpress_fvp_bloblist && \
+ cp build/fvp/release/fip.bin build/fvp/release/bl1.bin \
+ /opt/tf-a/vexpress_fvp_bloblist/ && \
rm -rf /tmp/tf-a
# Download the Arm Architecture FVP platform. This file is double compressed.
@@ -313,7 +321,7 @@
RUN wget -O /tmp/buildman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/buildman/requirements.txt
RUN wget -O /tmp/patman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/patman/requirements.txt
RUN wget -O /tmp/u_boot_pylib-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/u_boot_pylib/requirements.txt
-RUN virtualenv -p /usr/bin/python3 /tmp/venv && \
+RUN python3 -m venv /tmp/venv && \
. /tmp/venv/bin/activate && \
pip install -r /tmp/pytest-requirements.txt \
-r /tmp/sphinx-requirements.txt \
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 0135b19..a333ded 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -7,6 +7,7 @@
#include "imx8image.h"
#include <image.h>
+#include <linux/sizes.h>
static int p_idx;
static int sector_size;
@@ -54,7 +55,9 @@
{CMD_CONTAINER, "CONTAINER", "new container", },
{CMD_IMAGE, "IMAGE", "new image", },
{CMD_DATA, "DATA", "new data", },
- {-1, "", "", },
+ {CMD_DUMMY_V2X, "DUMMY_V2X", "v2x", },
+ {CMD_HOLD, "HOLD", "hold", },
+ {-1, "", "", }
};
static table_entry_t imx8image_core_entries[] = {
@@ -66,7 +69,9 @@
{CFG_A55, "A55", "A55 core", },
{CFG_A53, "A53", "A53 core", },
{CFG_A72, "A72", "A72 core", },
- {-1, "", "", },
+ {CFG_OEI, "OEI", "OEI", },
+ {CFG_M33, "M33", "M33 core", },
+ {-1, "", "", }
};
static table_entry_t imx8image_sector_size[] = {
@@ -144,6 +149,14 @@
exit(EXIT_FAILURE);
}
break;
+ case CMD_DUMMY_V2X:
+ param_stack[p_idx].option = DUMMY_V2X;
+ param_stack[p_idx++].entry = (uint32_t)strtoll(token, NULL, 0);
+ break;
+ case CMD_HOLD:
+ param_stack[p_idx].option = HOLD;
+ param_stack[p_idx].entry = (uint32_t)strtoll(token, NULL, 0);
+ param_stack[p_idx++].filename = NULL;
default:
break;
}
@@ -220,6 +233,16 @@
param_stack[p_idx].option =
(*cmd == CMD_DATA) ? DATA : AP;
param_stack[p_idx].filename = token;
+ break;
+ case CFG_OEI:
+ param_stack[p_idx].option = OEI;
+ param_stack[p_idx].filename = token;
+ param_stack[p_idx].ext = CORE_CM4_0;
+ break;
+ case CFG_M33:
+ param_stack[p_idx].option = M40;
+ param_stack[p_idx].ext = 0;
+ param_stack[p_idx].filename = token;
break;
}
break;
@@ -238,9 +261,15 @@
case CFG_A53:
case CFG_A55:
case CFG_A72:
+ case CFG_M33:
param_stack[p_idx++].entry =
(uint32_t)strtoll(token, NULL, 0);
break;
+ case CFG_OEI:
+ param_stack[p_idx].dst = (uint32_t)strtoll(token, NULL, 0);
+ param_stack[p_idx].entry = param_stack[p_idx].dst + 1;
+ p_idx++;
+ break;
}
default:
break;
@@ -549,6 +578,7 @@
char *tmp_filename, bool dcd_skip)
{
uint64_t entry = image_stack->entry;
+ uint64_t dst = image_stack->dst;
uint64_t core = image_stack->ext;
uint32_t meta;
char *tmp_name = "";
@@ -558,7 +588,9 @@
img->offset = offset; /* Is re-adjusted later */
img->size = size;
- set_image_hash(img, tmp_filename, IMAGE_HASH_ALGO_DEFAULT);
+ if (type != DUMMY_V2X) {
+ set_image_hash(img, tmp_filename, IMAGE_HASH_ALGO_DEFAULT);
+ }
switch (type) {
case SECO:
@@ -580,6 +612,27 @@
img->dst = 0xe4000000; /* S400 IRAM base */
img->entry = 0xe4000000;
break;
+ case OEI:
+ if (soc != IMX9) {
+ fprintf(stderr, "Error: invalid core id: %" PRIi64 "\n", core);
+ exit(EXIT_FAILURE);
+ }
+
+ img->hab_flags |= IMG_TYPE_OEI;
+ if (core == CORE_CM4_0) {
+ img->hab_flags |= CORE_ULP_CM33 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ meta = CORE_IMX95_M33P;
+
+ } else {
+ img->hab_flags |= CORE_ULP_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ meta = CORE_IMX95_A55C0;
+ }
+ tmp_name = "OEI";
+ img->dst = (dst ? dst : entry);
+ img->entry = entry;
+ img->meta = meta;
+ custom_partition = 0;
+ break;
case AP:
if (soc == QX && core == CORE_CA35) {
meta = IMAGE_A35_DEFAULT_META(custom_partition);
@@ -587,8 +640,10 @@
meta = IMAGE_A53_DEFAULT_META(custom_partition);
} else if (soc == QM && core == CORE_CA72) {
meta = IMAGE_A72_DEFAULT_META(custom_partition);
- } else if (((soc == ULP) || (soc == IMX9)) && core == CORE_CA35) {
+ } else if ((soc == ULP) && core == CORE_CA35) {
meta = 0;
+ } else if ((soc == IMX9) && core == CORE_CA35) {
+ meta = CORE_IMX95_A55C0;
} else {
fprintf(stderr,
"Error: invalid AP core id: %" PRIu64 "\n",
@@ -687,6 +742,15 @@
img->entry = 0x28300200;
}
break;
+ case DUMMY_V2X:
+ img->hab_flags |= IMG_TYPE_V2X_DUMMY;
+ img->hab_flags |= CORE_SC << BOOT_IMG_FLAGS_CORE_SHIFT;
+ tmp_name = "V2X Dummy";
+ set_image_hash(img, "/dev/null", IMAGE_HASH_ALGO_DEFAULT);
+ img->dst = entry;
+ img->entry = entry;
+ img->size = 0; /* dummy image has no size */
+ break;
default:
fprintf(stderr, "unrecognized image type (%d)\n", type);
exit(EXIT_FAILURE);
@@ -709,15 +773,26 @@
fprintf(stdout, "container flags: 0x%x\n", container->flags);
}
-static int get_container_image_start_pos(image_t *image_stack, uint32_t align)
+static int get_container_image_start_pos(image_t *image_stack, uint32_t align, uint32_t *v2x)
{
image_t *img_sp = image_stack;
/*8K total container header*/
int file_off = CONTAINER_IMAGE_ARRAY_START_OFFSET;
FILE *fd = NULL;
- flash_header_v3_t header;
+ flash_header_v3_t *header;
+ flash_header_v3_t *header2;
+ void *p;
int ret;
+ p = calloc(1, SZ_4K);
+ if (!p) {
+ fprintf(stderr, "Fail to alloc 4K memory\n");
+ exit(EXIT_FAILURE);
+ }
+
+ header = p;
+ header2 = p + FIRST_CONTAINER_HEADER_LENGTH;
+
while (img_sp->option != NO_IMG) {
if (img_sp->option == APPEND) {
fd = fopen(img_sp->filename, "r");
@@ -726,7 +801,7 @@
exit(EXIT_FAILURE);
}
- ret = fread(&header, sizeof(header), 1, fd);
+ ret = fread(header, SZ_4K, 1, fd);
if (ret != 1) {
printf("Failure Read header %d\n", ret);
exit(EXIT_FAILURE);
@@ -734,19 +809,27 @@
fclose(fd);
- if (header.tag != IVT_HEADER_TAG_B0) {
- fprintf(stderr, "header tag mismatched file %s\n", img_sp->filename);
+ if (header->tag != IVT_HEADER_TAG_B0) {
+ fprintf(stderr, "header tag mismatched \n");
exit(EXIT_FAILURE);
} else {
- file_off +=
- header.img[header.num_images - 1].size;
- file_off = ALIGN(file_off, align);
+ if (header2->tag != IVT_HEADER_TAG_B0) {
+ file_off += header->img[header->num_images - 1].size;
+ file_off = ALIGN(file_off, align);
+ } else {
+ file_off = header2->img[header2->num_images - 1].offset + FIRST_CONTAINER_HEADER_LENGTH;
+ file_off += header2->img[header2->num_images - 1].size;
+ file_off = ALIGN(file_off, align);
+ fprintf(stderr, "Has 2nd container %x\n", file_off);
+ *v2x = true;
+ }
}
}
img_sp++;
}
+ free(p);
return file_off;
}
@@ -838,6 +921,7 @@
char *tmp_filename = NULL;
uint32_t size = 0;
uint32_t file_padding = 0;
+ uint32_t v2x = false;
int ret;
int container = -1;
@@ -861,7 +945,7 @@
set_imx_hdr_v3(&imx_header, 0);
set_imx_hdr_v3(&imx_header, 1);
- file_off = get_container_image_start_pos(image_stack, sector_size);
+ file_off = get_container_image_start_pos(image_stack, sector_size, &v2x);
fprintf(stdout, "container image offset (aligned):%x\n", file_off);
/* step through image stack and generate the header */
@@ -870,6 +954,7 @@
/* stop once we reach null terminator */
while (img_sp->option != NO_IMG) {
switch (img_sp->option) {
+ case OEI:
case AP:
case M40:
case M41:
@@ -892,6 +977,30 @@
file_off += ALIGN(sbuf.st_size, sector_size);
break;
+ case DUMMY_V2X:
+ if (container < 0) {
+ fprintf(stderr, "No container found\n");
+ exit(EXIT_FAILURE);
+ }
+ tmp_filename = "dummy";
+ set_image_array_entry(&imx_header.fhdr[container],
+ soc,
+ img_sp,
+ file_off,
+ 0,
+ tmp_filename,
+ dcd_skip);
+ img_sp->src = file_off;
+ break;
+
+ case HOLD:
+ if (container < 0) {
+ fprintf(stderr, "No container found\n");
+ exit(EXIT_FAILURE);
+ }
+ file_off += ALIGN(img_sp->entry, sector_size);
+ break;
+
case SECO:
case SENTINEL:
if (container < 0) {
@@ -963,11 +1072,15 @@
do {
if (img_sp->option == APPEND) {
copy_file(ofd, img_sp->filename, 0, 0);
- file_padding += FIRST_CONTAINER_HEADER_LENGTH;
+ if (v2x)
+ file_padding += FIRST_CONTAINER_HEADER_LENGTH * 2;
+ else
+ file_padding += FIRST_CONTAINER_HEADER_LENGTH;
}
img_sp++;
} while (img_sp->option != NO_IMG);
+ fprintf(stderr, "%s: %x %d\n", __func__, file_padding, v2x);
/* Add padding or skip appended container */
ret = lseek(ofd, file_padding, SEEK_SET);
if (ret < 0) {
@@ -980,6 +1093,7 @@
/* Note: Image offset are not contained in the image */
tmp = flatten_container_header(&imx_header, container + 1,
&size, file_padding);
+ fprintf(stderr, "error writing image hdr %x\n", size);
/* Write image header */
if (write(ofd, tmp, size) != size) {
fprintf(stderr, "error writing image hdr\n");
@@ -1000,7 +1114,8 @@
img_sp->option == AP || img_sp->option == DATA ||
img_sp->option == SCD || img_sp->option == SCFW ||
img_sp->option == SECO || img_sp->option == MSG_BLOCK ||
- img_sp->option == UPOWER || img_sp->option == SENTINEL) {
+ img_sp->option == UPOWER || img_sp->option == SENTINEL ||
+ img_sp->option == OEI) {
copy_file_aligned(ofd, img_sp->filename, img_sp->src,
sector_size);
}
@@ -1031,7 +1146,7 @@
fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version);
build_container(soc, sector_size, emmc_fastboot,
- img_sp, dcd_skip, fuse_version, sw_version, outfd);
+ img_sp, false, fuse_version, sw_version, outfd);
return 0;
}
diff --git a/tools/imx9_image.sh b/tools/imx9_image.sh
index ca78a57..6523d1a 100755
--- a/tools/imx9_image.sh
+++ b/tools/imx9_image.sh
@@ -18,6 +18,14 @@
continue
fi
+ if [ $f = "m33-oei-ddrfw.bin" ]; then
+ continue
+ fi
+
+ if [ $f = "u-boot.bin" ]; then
+ continue
+ fi
+
if [ ! -f $tmp ]; then
echo "WARNING '$tmp' not found, resulting binary may be not-functional" >&2
diff --git a/tools/mkimage.c b/tools/mkimage.c
index ac62ebb..2954626 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -196,6 +196,7 @@
{ "verbose", no_argument, NULL, 'v' },
{ "version", no_argument, NULL, 'V' },
{ "xip", no_argument, NULL, 'x' },
+ { /* sentinel */ },
};
static void process_args(int argc, char **argv)
diff --git a/tools/u_boot_pylib/test_util.py b/tools/u_boot_pylib/test_util.py
index 4835847..637403f 100644
--- a/tools/u_boot_pylib/test_util.py
+++ b/tools/u_boot_pylib/test_util.py
@@ -64,7 +64,7 @@
if build_dir:
prefix = 'PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools ' % build_dir
- # Detect a Python virtualenv and use 'coverage' instead
+ # Detect a Python sandbox and use 'coverage' instead
covtool = ('python3-coverage' if sys.prefix == sys.base_prefix else
'coverage')