tree 528c31bde055e3541e4e913a10f7832886614d7e
parent c50054fb5d2ceef6bcf8a5bd907d82b2c1f3e4cd
author Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 1508589312 +0300
committer Alexey Brodkin <abrodkin@synopsys.com> 1512981382 +0300

ARC: HSDK: Fixup DW SDIO CIU frequency to 50000000Hz

DW SDIO controller has external CIU clock divider controlled via
register in the SDIO IP. Due to its unexpected default value
(we expected it to divide by 1 but in reality it divides by 8)
SDIO IP uses wrong CIU clock (it should be 100000000Hz but actual
is 12500000Hz) and works unstable (see STAR 9001204800).

So increase SDIO CIU frequency from actual 12500000Hz to 50000000Hz
by switching from the default divisor value (div-by-8) to the
minimum possible value of the divisor (div-by-2) in HSDK platform
code.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>