commit 5d489bf30e34b932ba65e85ca5d32425b98fb434
author Ley Foon Tan <ley.foon.tan@intel.com> Mon Apr 20 16:17:27 2020 +0800
committer Marek Vasut <marex@denx.de> Mon Apr 27 09:14:52 2020 +0200
tree 67951aa90a1bbe41c72036ea8713ab155d87ad23
parent 0bf9acc6ea98c8bac40558a2a71649b5b5e09587

arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset

Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.

Reported-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

arch/arm/mach-socfpga/include/mach/clock_manager_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index e710aa2..9d2b3ba 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -85,7 +85,7 @@
 #define CLKMGR_S10_MAINPLL_VCOCALIB			0x8c
 /* Periphpll group */
 #define CLKMGR_S10_PERPLL_EN				0xa4
-#define CLKMGR_S10_PERPLL_BYPASS			0xac
+#define CLKMGR_S10_PERPLL_BYPASS			0xb0
 #define CLKMGR_S10_PERPLL_CNTR2CLK			0xbc
 #define CLKMGR_S10_PERPLL_CNTR3CLK			0xc0
 #define CLKMGR_S10_PERPLL_CNTR4CLK			0xc4