andes: Unify naming policy for Andes related source
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e20ef6..fa3b016 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -80,7 +80,7 @@
Sifive core devices that uses L2 cache to store SPL.
# board-specific options below
-source "board/AndesTech/ae350/Kconfig"
+source "board/andestech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
@@ -93,7 +93,7 @@
source "board/xilinx/mbv/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/andes/Kconfig"
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andes/Kconfig
similarity index 91%
rename from arch/riscv/cpu/andesv5/Kconfig
rename to arch/riscv/cpu/andes/Kconfig
index e3efb0d..120fec5 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andes/Kconfig
@@ -1,4 +1,4 @@
-config RISCV_NDS
+config RISCV_ANDES
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
@@ -8,7 +8,7 @@
imply ANDES_PLMT_TIMER
imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply V5L2_CACHE
+ imply ANDES_L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andes/Makefile
similarity index 100%
rename from arch/riscv/cpu/andesv5/Makefile
rename to arch/riscv/cpu/andes/Makefile
diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andes/cache.c
similarity index 89%
rename from arch/riscv/cpu/andesv5/cache.c
rename to arch/riscv/cpu/andes/cache.c
index 269bb27..7d3df87 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -12,21 +12,21 @@
#include <dm/uclass-internal.h>
#include <asm/arch-andes/csr.h>
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
void enable_caches(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_CACHE,
- DM_DRIVER_GET(v5l2_cache),
+ DM_DRIVER_GET(andes_l2_cache),
&dev);
if (ret) {
- log_debug("Cannot enable v5l2 cache\n");
+ log_debug("Cannot enable Andes L2 cache\n");
} else {
ret = cache_enable(dev);
if (ret)
- log_debug("v5l2 cache enable failed\n");
+ log_debug("Failed to enable Andes L2 cache\n");
}
}
@@ -78,7 +78,7 @@
asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_enable);
#endif
}
@@ -89,7 +89,7 @@
asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_disable);
#endif
}
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andes/cpu.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/cpu.c
rename to arch/riscv/cpu/andes/cpu.c
diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andes/spl.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/spl.c
rename to arch/riscv/cpu/andes/spl.c