tree 8e3ba14866674209e364e7617efc647da1d21168
parent ff2d134cde51dd109997085c66210f22e761c7dd
author Grzegorz Bernacki <gjb@semihalf.com> 1200492767 +0100
committer Wolfgang Denk <wd@denx.de> 1200558718 +0100

Set ips dividor to 1/4 of csb clock.

Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>